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Old 12th September 2007, 04:30 PM   #241
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Default Ekv

Hi Andy,

What's that (undefined?) $vt thingy? A global variable? If so, sloppy programming.

As for "else z0 = 1", maybe it should read (in C) as "else if( fv < -15.0 ) z0 = 1;"

Cheers, Edmond.
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Old 12th September 2007, 05:09 PM   #242
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Default Re: Ekv

Quote:
Originally posted by estuart
Hi Andy,

What's that (undefined?) $vt thingy? A global variable? If so, sloppy programming.

As for "else z0 = 1", maybe it should read (in C) as "else if( fv < -15.0 ) z0 = 1;"
Hi Edmond,

I'm not a Verilog-A guy, but comparing the Verilog-A code to the equations in the EKV manual, it looks like $vt is a Verilog-A reserved variable for kT/q, where T is the simulation temperature. I suspect it can't be assigned like a normal variable, so it seems to be a safe practice.

Yes, it's very sloppy coding. I'd call it a hack in fact. Also, the interpolation "function" is just coded inline as many times as it's called (3). I found an article on the web that states that the open-source ADMS compiler (what they use to convert Verilog-A to C) does not support functions! So that's probably why they did it that way. I've been looking for the C source for this model, but all I can find is notices that say the license does not allow redistribution of EKV C source code. Some public domain model!

I tried the "else if" thing, but the code does not follow that branch, so it has no effect. My detailed experience is in this usenet post
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Old 12th September 2007, 06:42 PM   #243
PB2 is offline PB2  United States
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Quote:
Originally posted by andy_c


That's a simplified version of the actual code. I'm not sure why they put that there. I've attached the Verilog code I downloaded to this message. The interpolation function of the actual code looks buggy. Notice the if the first "if" statement evaluates to true, it will be overwritten in the "else" of the next "if" statement.

// Forward current (43-44)
fv=(VP-VS)/$vt;

if (fv >= -0.35)
z0=2.0/(1.3 + fv - ln(fv+1.6));

if (fv>=-15 && fv<-0.35)
z0= 1.55 + exp(-fv);
else
z0=1;

z1=(2.0 + z0) / (1.0 + fv + ln(z0));

if (fv > -15.0)
y=(1.0 + fv + ln(z1)) / (2.0 + z1);
else
y= 1.0 / (2.0 + exp(-fv));

iff = y*(1.0 + y);

I can't seem to get indenting to work.

My main HDL experience is with VHDL, but I have done some Verilog, not that it really matters. Verilog is C like, and VHDL is ADA like, just another programming language. HDLs of course have the required features to describe hardware as I'm sure you know.

About poor code quality, and really also poor hardware design practice these could probably make for a long conversation. Seems the industry assumes that if a person is college trained that they know and understand what is required to solve real world engineering problems. You probably know how far off the mark this is, LOL. I've seen my good share of bad code and hardware design in my career. "No Silver Bullet" comes to mind which makes some good points but I do not agree with completely:
http://en.wikipedia.org/wiki/No_Silver_Bullet

This should be required reading for every professional programmer:
http://en.wikipedia.org/wiki/The_Ele...ramming_Style_(book)


It seems you're saying that the first if is dead code?
And if I had to guess, I'd say that the first if statement was the coder's first attempt, the second was a bug fix. The first if was left in probably with the intention of deleting it after debugging was finished. Yes, it is very sloppy, but the code might work correctly if my guess is right. Just throwing the idea out there.

Pete B.
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Old 12th September 2007, 07:00 PM   #244
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Quote:
Originally posted by PB2
It seems you're saying that the first if is dead code?
And if I had to guess, I'd say that the first if statement was the coder's first attempt, the second was a bug fix. The first if was left in probably with the intention of deleting it after debugging was finished. Yes, it is very sloppy, but the code might work correctly if my guess is right. Just throwing the idea out there.
In searching around, I found some VHDL code for EKV written by the EKV authors themselves. It's in "ekv26.vhd" inside this zip file. In there, the structure of the "if" statement is much more clear. I'm going to translate the VHDL into VBA and see if that gives results consistent with the SPICE simulators.
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Old 12th September 2007, 07:02 PM   #245
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Default Re: Re: Re: Re: Re: EKV modeling of power MOSFETs

Quote:
Originally posted by andy_c


Thanks for trying this out.

Looks like LTSpice and Micro-Cap are really close here. The current reported by LTSpice is 10.7944 uA. I'd love to get the VBA code that close.



Hmmm. When I use this interpolation function I get 8.69 uA. So it's not just the interpolation function that's causing the discrepancy.



Yes, it's a small device taken from the EKV chapter (chapter 7) in the book I linked to in this post. The author is using AIM Spice, and it looks like he is getting just a bit less than 11 uA also.

My complete tale of woe on this subject can be found in the newsgroup sci.electronics.cad.
This reminds me of processor emulation where we have to get exact agreement.

I've not followed the problem too closely but believe that I understand the issue. One obvious question is precision, it is difficult to determine the required precision for a long string of calculations and often single precision floating point is not enough. I believe Knuth has a chapter covering this issue.

It seems that the SPICE calculations agree and so it is probably reasonable to suspect the VB code. I trust your programming Andy and therefore I would not be surprised if you find a bug in VB, assuming it is not a precision issue.

The tedious debug method would be to single step the VB and compare intermediate values. Is there a source for the correct intermediate values? I would think that the Verilog-A code would complie as C code fairly easily, I think you mentioned a translator.

I'd guess that you already had these thoughts Andy, just offering them for discussion.

Pete B.
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Old 12th September 2007, 07:21 PM   #246
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Quote:
Originally posted by andy_c


In searching around, I found some VHDL code for EKV written by the EKV authors themselves. It's in "ekv26.vhd" inside this zip file. In there, the structure of the "if" statement is much more clear. I'm going to translate the VHDL into VBA and see if that gives results consistent with the SPICE simulators.

Yes the if statement is better, I should have looked at the EKV paper.

Pete B.
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Old 12th September 2007, 07:26 PM   #247
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Default Re: Re: Re: Re: Re: Re: EKV modeling of power MOSFETs

Quote:
Originally posted by PB2
One obvious question is precision, it is difficult to determine the required precision for a long string of calculations and often single precision floating point is not enough. I believe Knuth has a chapter covering this issue.
Fortunately, VBA allows explicit declaration of variable types. I've declared all my variables as type double, which makes them 64-bit. So I think I'm okay there.

Quote:
It seems that the SPICE calculations agree and so it is probably reasonable to suspect the VB code. I trust your programming Andy and therefore I would not be surprised if you find a bug in VB, assuming it is not a precision issue.
I hope it's not a bug in VB itself. That would be hard to find! My suspicion is there's some algorithm difference between the SPICE code and the Verilog-A code. Given that the two SPICE simulators have such good agreement, it's likely they are using the same algorithm, and the tiny difference is just the precision of the solution of the nonlinear equations. Now that I found the VHDL code, I'll be able to look for algorithm differences. Right away, I see the interpolation functions differ somewhat.

Quote:
The tedious debug method would be to single step the VB and compare intermediate values. Is there a source for the correct intermediate values? I would think that the Verilog-A code would complie as C code fairly easily, I think you mentioned a translator.
This problem is I don't have the source code of a "known good" reference. I'm suspicious of the Verilog-A code, and I'd trust the VHDL more I think, just because it has somebody's name on it, and that guy is one of the EKV model developers.

Quote:
I'd guess that you already had these thoughts Andy, just offering them for discussion.
Thanks. Any ideas are welcome! I'm about ready to try version number 3, translated from the VHDL.
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Old 12th September 2007, 07:41 PM   #248
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I notice that VHDL type real is used in ekv26.vhd which is usually double precision floating point according to this reference:
http://www.csee.umbc.edu/help/VHDL/types.html

Other net references state that it is single.

This statment in ekv26.vhd requires double precision:
yk:=exp(v)+1.0e-64;

Something to keep in mind also with the VB types. Just saw your post above that you've got them declared as doubles, I figured that you would!

Pete B.
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Old 12th September 2007, 07:49 PM   #249
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Default Re: Re: Re: Re: Re: Re: Re: EKV modeling of power MOSFETs

Quote:
Originally posted by andy_c


Fortunately, VBA allows explicit declaration of variable types. I've declared all my variables as type double, which makes them 64-bit. So I think I'm okay there.



I hope it's not a bug in VB itself. That would be hard to find! My suspicion is there's some algorithm difference between the SPICE code and the Verilog-A code. Given that the two SPICE simulators have such good agreement, it's likely they are using the same algorithm, and the tiny difference is just the precision of the solution of the nonlinear equations. Now that I found the VHDL code, I'll be able to look for algorithm differences. Right away, I see the interpolation functions differ somewhat.



This problem is I don't have the source code of a "known good" reference. I'm suspicious of the Verilog-A code, and I'd trust the VHDL more I think, just because it has somebody's name on it, and that guy is one of the EKV model developers.



Thanks. Any ideas are welcome! I'm about ready to try version number 3, translated from the VHDL.
Yes, I agree completely that the SPICE simulators might be using the same algorithm that might have a bug. Also about a known good reference. I'll enjoy hearing the answer to this mystery.

Pete B.
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Old 12th September 2007, 08:50 PM   #250
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Pete, your point about the debugger gave me an idea. The EKV manual spells out a sequential algorithm with no looping and a standard mathematical - not programming - notation. This would be the perfect thing for MathCad. I could format the equations such that MathCad would display them identically to the equations in the EKV manual. Then I could look at each intermediate result in MathCad and compare it with the values in the VBA debugger. This would rule out any possibility that I might have misplaced some parentheses or some stupid error like that in my VBA code.

So that will be the next step - then the VHDL translation.
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