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|25th July 2007, 11:18 PM||#181|
Join Date: Sep 2006
An unpleasant surprize
Call me a whiner, but I've got a beef.
This weekend I was evaluating some OnSemi ThermalTrak devices. As part of my investigation, I wanted to run some Gummel plots up to a couple of amps. So that I could keep heating to a minimum, I went to attach the device to a heatsink. Low and behold, the darn hole in the part is just a smidge too small for a 6-32 screw. Go figure. What were they thinking? (Metric?). I just drilled the sucker out a smidge, but what an extra pain!
BTW, the OnSemi SPICE model appears to stink in regard to modeling Vbe vs IC (that doesn't mean SPICE is not tremendously useful!).
The good news is that the real P and N devices match REALLY well in both Beta and Vbe. For those interested, the thermal tracking diode has the same junction drop as the transistor when it is conducting about 1/4 the collector current of the transistor.
|26th July 2007, 09:42 PM||#182|
Join Date: Sep 2003
For anyone desiring to simulate Bob Cordell's ThermalTrak circuits, andy_c developed improved Spice models for On-Semi Qmjl3281 and Qmjl1302. These models have given me good results with LTSPICE.
I would appreciate Spice models for any of the large Sanken Bipolar output devices, especially the
You can find more details on andy_c thread.
.MODEL Qmjl3281a_mod npn
+IS=6.5498e-11 BF=139.247 NF=1.00176 VAF=46.776
+IKF=10 ISE=7.75232e-12 NE=3.34341 BR=4.98985
+NR=1.09511 VAR=4.32026 IKR=4.37516 ISC=3.25e-13
+NC=3.96875 RB=11.988 IRB=0.111742 RBM=0.102914
+RE=0.00127227 RC=0.209833 XTB=0.115253 XTI=1.03146
+EG=1.11986 CJE=1.0531e-08 VJE=0.4 MJE=0.450375
+TF=2.6464e-9 XTF=1000 VTF=2.06045 ITF=175
+CJC=5e-10 VJC=0.4 MJC=0.85 XCJC=0.959922
+FC=0.1 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
.MODEL Qmjl1302a_mod pnp
+IS=3.25053e-12 BF=60.3363 NF=0.992063 VAF=19.8199
+IKF=7.18352 ISE=3.25712e-12 NE=3.42487 BR=5.15499
+NR=1.03617 VAR=2.77936 IKR=9.38159 ISC=2.5e-13
+NC=3.89405 RB=0.776136 IRB=0.0998107 RBM=0.776136
+RE=0.000613663 RC=0.0424163 XTB=1.43773 XTI=1
+EG=1.05 CJE=1.0690e-08 VJE=0.728073 MJE=0.42161
+TF=2.9458e-9e-09 XTF=1000 VTF=4.11586 ITF=380
+CJC=1.79861e-09 VJC=0.814822 MJC=0.473271 XCJC=1
+FC=0.8 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
|3rd August 2007, 09:56 AM||#183|
Join Date: Dec 2006
I am very pleased to see that the T topology is considered as optimal for the output stage.
This is not what J.Curl told me in his post 406 ??
Having read the different posts and opinions on biasing and gm doubling I am giving hereunder a summary of HP Oliver paper on the subject. This paper has some typo’s errors making it difficult to read (IMHO) therefore I tried to clarify it.
This development clarifies the matter, shows how much ‘the old wise guys’ are correct but raises ( IMHO) some questions.
Calculation of Ro output resistance of a push pull stage in function of total current
(See annexed drawing)
Re emitter resistor
Rb source and base resistor
R half resistance referred to the emitter (emitter base bias loop)
= Rb/(beta+1) + Re
Io bias current
Io+i1 total current in collector of transistor 1
Io+i2 total current in collector of transistor 2
e Thevenin output test voltage
i= i2-i1 test current
Ro output resistance with vin = 0
2Vo bias voltage
Vt thermal voltage kT/q
gm trans-conductance of one transistor at Io
Find i1 and i2 function of e
Calculate R1 = -de/di1 ( minus sign because e is increasing with i1 decreasing which gives a negative derivative)
Calculate R2 = de/di2
Ro = R1//R2
Plot Ro in function of i with Re as parameter
An easier way is to plot gmÄRo where ÄRo is the difference between Ro at crossover (i=o) and Ro at large signal and this with gmR as parameter. The multiplication by gm normalizes ÄRo and then gmÄRo is a number without dimension. This is plotted as second drawing in the attached file.
R= Rs /(1+â) + Re
Vt ln(1+ (Io+ i1 )/Is) + R(Io+ i1) = Vo – e (1)
Vt ln( 1+(Io+ i2 )/Is) + R(Io+ i2) = Vo + e (2)
At idle e= i = 0
Vt ln( 1+(Io/Is)) + R(Io) = Vo
Replacing Vo in (1) gives and executing:
Vtln(Is+Io+ i1) –VtlnIs +RIo + Ri1 = RIo –VtlnIs +Vtln(Is+Io) - e
Neglecting Is and dividing both sides by Vt gives with gm = Io/Vt:
Ln(1+ i1/Io) + gmR (i1/Io) = -e/Vt (3)
Ln(1+ i2/Io) + gmR (i2/Io) = e/Vt (4)
For each value of i2 e is found by (4) and i1 is found by solving (3) by successive approximation numerically.
The result gives numerically e function of i1 and i2 or i
We can now calculate Ro or better gmRo
gmRo = gmR1//gmR2 with
gmR1 = -gmde/di1 = gmR + 1/(1+ i1/Io) using dln(1+ax)/dx = a/1+ax
gmR2 = gmde/di2 = gmR + 1/(1+ i2/Io)
Estimation of Ro at crossover and for large signal
At crossover i=e=0 = i1 = i2
R1=R + 1/gm
R2=R + 1/gm and Ro = R/2 + 1/2gm
If i2/Io is very large then R2 = R and Io+ i1 = 0 because T1 is cut off , then i1 / Io =-1
And R1 is infinite which make sense
Then Ro= R2=R Ro=R
We can now plot in function of i/Io gmÄRo = gm(Ro – R) the normalized difference between Ro and Ro at large signal. This plot gives the variation of Ro with signal for different values of gmR
The conclusion is:
The key parameter for biasing is the product gmR
For i large then Ro = R
For i = 0 then R0 = R/2 + 1/2gm
Then Ro increases with i decreasing
Then Ro stays constant with i except for a small bump at i= about 4Io
Then Ro decreases with i decreasing except for a bump at i = 4Io where it increases
The Gm of the stage is =1/Ro because the voltage forward gain (( Vo/Vin) for iout =0 )of this quadripole is 1
The voltage gain is RL/(Ro+RL) RL being the load. Variation in Gm with iout gives distortion.
Depending on gmR, the stage Gm will decrease or increase.
Gm can only increase with i decreasing if gmR>1. In this case Ro comes close to R/2 halving therefore Gm doubles. This is in the no realistic case of gmR very large. A better sentence would be : Gm increasing and not doubling
In this way, Leach is more or less right but his Spice simulation is misleading because he made it with Rgm=1. Of course then you will see no variation in the plot of the voltage gain, the bump being to small to be seen.
As M. Curl is saying, the best is to bias at Rgm=1, drive with a voltage source and use many output transistors in //, this makes class A operation larger and the bump in Ro decreases because //. Also the bump appears at a rather large power in the load making it less audible.
The influence of the source Rb is obvious and makes in some cases the concept of critical biasing ( gmR=1) not realistic.
If gmR=1 is pertinent, then this should remain constant with temperature which means that gm should remain constant with temperature and not Io in the biasing scheme. This is dangerous but could perhaps be well implemented with Thermaltrak transistors.
What do you think?
|3rd August 2007, 05:49 PM||#184|
Join Date: Jul 2003
Location: berkeley ca
Chas, to be exact, it would seem to me that we would have to include higher order distortion (especially 7th harmonic) weighting. Has anyone done this with Spice?
|4th August 2007, 03:23 AM||#185|
Join Date: May 2003
With MicroCap (even the the free eval version), you can let it run multiple sweeps while stepping the value of the emitter resistors. It is pretty obvious which resistor value is best for a given bias voltage (or vice-versa).
|4th August 2007, 11:31 AM||#186|
Join Date: Sep 2006
Actually, I think Charles is about three chapters ahead:
1. He has made successful product with vertical MOSFETs.
2. He is using ThermalTrak BJT's, which overcome significant problems with BJTs.
3. He uses SPICE.
|4th August 2007, 03:45 PM||#187|
Join Date: Apr 2003
There's an interesting thing about the "kinks" in the FET SPICE plots.
The Oliver paper deals with output stage nonlinearity in terms of the variation of the output impedance with current, while Self looks at the variation of voltage gain in a similar way - taking the derivative of Vout with respect to Vin. What I like about Oliver's approach is that it removes the load from consideration. Back in post 555 on page 23 of this thread I did some plots where I swept a DC current source at the output of a complementary EF and SF and plotted the derivative of the output voltage with respect to the swept current. This was to show the incremental low-frequency output impedance vs. current. If you look at the one for the FET, you'll see the "kinks". It's clear that the slope of the simulated output impedance is discontinuous in two places. Since the output impedance itself is defined as a slope, then it's a "slope of the slope" or second derivative phenomenon.
Let's look at the second derivative of the Id-Vgs equations that SPICE uses in the simple FET model (in this case, level 1). The equations are:
Id = 0 for Vgs < Vto
Id = K(Vgs - Vto)2 for Vgs >= Vto
So for Vgs < Vto, the second derivative is 0. But for Vgs >= Vto, the second derivative is 2K. There's a discontinuity in the second derivative of Id vs. Vgs at Vgs = Vto. A reasonable hypothesis might be that the discontinuity in the second derivative of Id vs. Vgs is causing a discontinuity in the second derivative of Vout vs Iout. This is equivalent to a discontinuity in the slope of the output impedance vs. output current.
How can we test this hypothesis? Well, the BSIM3 FET SPICE model has equations for Id vs. Vgs for which all the derivatives are continuous (reference here). Also, Edmond Stuart (estuart) has created subcircuit models for the 2SJ201 and 2SK1530 that use the BSIM3 FET model internally. If we take my circuit from the post on page 23 and replace the FETs with Edmond's models, we can look at the output impedance vs. current. I have done so, adjusting the bias for 150 mA per device. I've plotted the output impedance vs. current using the same scale as the plots on page 23. I've attached the plot below. Notice there are no kinks at all, and the plot is indeed very smooth.
So my conclusion is that the kinky behavior of the FET SPICE plots (both in Self's book and on page 23 of this thread) is due to a deficiency in the level 1 SPICE models and not the devices themselves. BSIM3 seems to fix this.
|4th August 2007, 04:04 PM||#188|
Join Date: Jul 2003
Location: berkeley ca
Fellow designers, let me give you a short history of my experience with power amps that might clarify the situation.
In the 1970's I designed a small power amp that was single sided called the JC-3 that became the ML-2 in order that I not receive any royalties. This is a well known product that was single sided, BUT it became unreliable with power supply voltages over +/- 25V because of the dreaded second breakdown known to all amp designers as an evil in power transistors.
For a more powerful amplifier, I switched over to the balanced bridge output design in order to make a 250W/channel power amp for Gale Electronics in London, in 1975-76. This design was superficially similar to what Charles makes today, except that I used negative feedback, slower output devices, (that's all that Motorola made at the time) choke input power supply, stepped power supply, only a complementary Darlington configuration, instead of a triple Darlington. However, Charles I used the FAMED NEC complementary V-fets that you seem to like on the input, (until they pulled the plug on the manufacture of them), and I achieved 100V/us slew rate. The prototype is last owned by Ira Gale.
Then in 1977, I designed a 100W/channel bridged power amp for Symmetry, that also used a bridge configuration, and it sounded better, because it used faster and more linear Motorola complementary output transistors. The point that is important here is that my PRIMARY protection for the output stages was a CIRCUIT BREAKER, not an elaborate V-I scheme, electronic crowbar, or plain fuse. This prototype is owned by Noel Lee
Because of my success with this technique, I moved on in 1980 to make a 250W bridged amp with ring emitter transistors that had a slew rate over 1000V/us and CIRCUIT BREAKER protection only. Once again, the circuit breaker beat the output devices in limiting the current. Brian Cheney of VMPS owns this prototype.
Then in 1984, I thought that I could make a 100W amplifier with Vmosfets that only took a single side. In other words, I could go from the +/- 25V to +/- 40V for the bipolars to +/- 45V for a single sided Vmosfet output stage using 100V devices.
I made the prototype, and it worked well and sounded great, EXCEPT that a simple circuit breaker would NOT protect it from shorts.
What to do? Faster circuit breaker? That was expensive. Bigger output devices? I tried the 140 devices, and I still had problems. Paralleled bigger output devices? Better, but not perfect, and finally I was working on advanced V-I protection when the stock market crash of 1987, made our company fall into the ocean, and that was the end of that.
In 1989, I started working as a consultant for Parasound. They had a design (from the Toshiba handbook) that was similar to what I normally designed, and they wanted some help with it. This design had a PROVEN V-I protection circuit that allowed single sided operation with fair amounts of power such as 100-250W without any problem, except for the output relay that was a necessary component in this scheme. Still, it worked then, and it still works today. We have pushed the voltage from +/- 60V in the early days to +/- 90V today, all because of that protection scheme.
Is it perfect? NO WAY! But it is a good solution, especially when you want high power and reasonably low cost.
Each one of these designs has been made without extensive Spice sumulation. What a concept! Some people don't even need calculators, (but I am not one of them)
Now, Bob thinks that I did something wrong in my initial Vmosfet design. I haven't found any evidence yet that I made a real mistake, just that I believed the designers data sheet a little too literally, and Vmosfets were not as safe from V-I problems as they implied.
|5th August 2007, 02:15 PM||#190|
Join Date: May 2002
Location: Great City of Turnhout, Belgium
Blog Entries: 7
Great story. I always find it fascinating to read about how you guys, accomplished designers, get ahead step by step.
I have one question though. At a certain point you decided that the bridged approach with the circuit breaker was not (or no longer) satisfactory and you switched to single ended design and all the accompanying issues for the V/I protection. (If I read you correctly). Why did you make the switch in the first place?
I won't make the tactical error to try to dislodge with rational arguments a conviction that is beyond reason - Daniel Dennett
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