| Searching for high hfe, low noise and cob PNP BJT - Click HERE for Original Thread |
| roender |
I need a low power PNP BJT which will work at only 0.7V Vce and Ic 2.5mA.
It must have low cob, over 200 hfe at 1V Vce and very high ft and very low noise. |
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| roender |
Hi Mike,
I already use bc560c (you know were) but it has a big problem. It has very unstable hfe with temperature, so unstable that it can't keep bias stable when cold air is blow over it.
ps Did you receive my e-mail with PowerSymasym EGLE files?
Mihai |
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| AMV8 |
Hi
You have probably already thought of this but here goes. All I do with the BC 550 and BC 560 is to press them against a common heat sink to keep the temperature low and constant.
My "special " transistor for preamps and low noise is the lm394 ( in a can ) which does may meet all your needs but it is excellant.
Don |
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| AndrewT |
Hi,
all silicon transistors have a similar Ic vs Vbe characteristic that varies markedly with junction temperature.
I think hFE has the same variation with temp.
These variations are normally reduced by using an LTP to balance out changes.
Even better balance is achieved by thermally coupling the devices and better still with a dual device. |
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| Tim__x |
| Perhaps if we could see your circuit we could suggest modifications to make the bias less device dependant. |
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| roender |
Ok, this is my amplifier.
R12 and R13 is no longer in circuit |
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| tomahauk |
i think if you connect q8 and q9 that will resolve your problem
i think the bias stability will rise if you connect together q16 + q14; q7 + q6 + q15
i think you could even connect transistors in first differential stage, j1 + j2, q21 + q18 |
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| AndrewT |
Hi Roender,
what is D1? a Zener or a 1mA CCS?
your output stage currents seem astray.
70mA through R5 generates 1.54V.
The bias across the emitter resistors will be about (1.54-1.3)=0.24V this generates Iq=2.4A.
Reduce Ir5 to about 61mA and the bias reduces to about 420mA , Vre~=21mV. Iq=2*[(22r*0.07A)-1.3V]/(0r1*2)
Note how sensitive Iq is to small changes in Ir5.
How will you adjust Vbias? 4diodes will not achieve accuracy. Are any on the output heatsink for temperature compensation?
You have cascoded the second LTP and achieved good HF response then killed that response by fiiting a Miller comp cap. Why have you fitted C14 to the collector of q10 rather than the collector of Q16?
Why have you fitted R12 & R13?
Tomahauk,
connect those transistors?
Do you mean match their parameters? |
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| AndrewT |
Hi,
your choice of values for C19 & C21 produce RC time constants near 220mS.
If you adopt the philosophy of setting the PSU RC to half an octave above this (330mS) then you are forced to adopt +-40mF/channel for 8ohm speakers and +-80mF/ch for 4ohm speakers.
Is C19 in series with a DC blocking cap in your source?
The combined RC of the input could usefully be reduced to 80mS and still retain good bass response. Then C21 can be reduced to 220uF and that allows smoothing to be reduced by half.
The input filters should set the frequency response of you amp. All the internal circuitry should exceed the bandwidth of the filters by a margin, that you select. |
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| MikeB |
| quote: | Originally posted by AndrewT
4diodes will not achieve accuracy. Are any on the output heatsink for temperature compensation?
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Hi Andrew, Roender uses NJL-output devices, they have built in diodes.
Mike |
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| AndrewT |
| they are not wired into his schematic. and still no adjustment. |
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| roender |
| quote: | Originally posted by AndrewT
Hi Roender,
what is D1? a Zener or a 1mA CCS?
your output stage currents seem astray.
70mA through R5 generates 1.54V.
The bias across the emitter resistors will be about (1.54-1.3)=0.24V this generates Iq=2.4A.
Reduce Ir5 to about 61mA and the bias reduces to about 420mA , Vre~=21mV. Iq=2*[(22r*0.07A)-1.3V]/(0r1*2)
Note how sensitive Iq is to small changes in Ir5.
How will you adjust Vbias? 4diodes will not achieve accuracy. Are any on the output heatsink for temperature compensation?
You have cascoded the second LTP and achieved good HF response then killed that response by fiiting a Miller comp cap. Why have you fitted C14 to the collector of q10 rather than the collector of Q16?
Why have you fitted R12 & R13?
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Hi Andrew
First thing first, the schematic is derived from MikeB symasym, thank you Mike.
D1 is a 12V zener connected as a cascode reference voltage and as a load for 1mA CCS (upper one)
R5 is 15ohm in reality, 20ohm in LTspice to achieve the same driver current as in reality.
R35 is a 500ohm trimpot connected in parallel with 220ohm metal film resistor.
Two NJL (ThermalTrack) diodes are connected in series with two BE junction (5551/5401) for properly bias tracking.
C14 is not a miller cap, is more like phase lead compensator and it helps to stop HF ringing. The voltage developed across this capacitor has very little variation, in range of 1-2V
R12 and R13 are no longer in use, was a wrong way to liniarize the VAS stage |
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| tomahauk |
| quote: | Originally posted by AndrewT
...
Tomahauk,
connect those transistors?
Do you mean match their parameters? |
i mean thermal connection, for example glue them (the easiest) or gird them with metal clamp, then parameters will change the same in both of transistors (junctions will have almos the same temp in both transistors) |
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| roender |
| quote: | Originally posted by AndrewT
Hi,
your choice of values for C19 & C21 produce RC time constants near 220mS.
If you adopt the philosophy of setting the PSU RC to half an octave above this (330mS) then you are forced to adopt +-40mF/channel for 8ohm speakers and +-80mF/ch for 4ohm speakers.
Is C19 in series with a DC blocking cap in your source?
The combined RC of the input could usefully be reduced to 80mS and still retain good bass response. Then C21 can be reduced to 220uF and that allows smoothing to be reduced by half.
The input filters should set the frequency response of you amp. All the internal circuitry should exceed the bandwidth of the filters by a margin, that you select. |
Andrew,
Now you lost me ... I have no DC blocking cap in DAC output.
How this will solve my problem?
Tomahauk
All BJT peers are thermaly bounded
Best regards,
Mihai |
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| AndrewT |
Hi Roe,
no need to feel lost in this community.| quote: | | The input filters should set the frequency response of you amp. All the internal circuitry should exceed the bandwidth of the filters by a margin, that you select |
If the 10uF is the sole DC blocking cap then it sets the high pass filter. That 10uF value and 22k input impedance set the -3db of the high pass to 0.7Hz.
The NFB is set too high for this and I suspect the PSU will be at least an octave too high and maybe 2 or 3 octaves too high.
The rule seems to be that:-
bandwidth is set by input filter.
The NFB turn over frequency should be at least half an octave below the input filter.
The PSU effective turn over frequency should be at least half an octave below the NFB F-3db.
If you want extended low low bass I recommend that F-3db should be a full decade below 20Hz i.e. below 2Hz.
To match this NFB should be below input F-3db/1.4
and PSU should be below NFB F-3db/1.4
take an example
set input HP filter to 90mS (1.7Hz)
NFB=140mS
PSU=200mS This requires +-25mF/ch for 8ohm speakers. |
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| roender |
Thank you Andrew.
I know very well what you talking about (I don't want to be rude, don't get me wrong) but what this had to do with my thermal stability problem? |
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| jacco vermeulen |
Mihai,
don't you agree that you end up in Tokyo if you need something with better than 300MHz, 2.5pF, 500 hFe and low noise ? |
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| AndrewT |
Hi Roe,| quote: | Now you lost me ... I have no DC blocking cap in DAC output.
How this will solve my problem? |
you asked a question, I answered it.
I see now you were referring back to the initial question.
Solve what is wrong with the amp before blaming the variable hFE. As said before ALL transistors suffer from variable hFE and all amplifiers should be designed to be substantially impervious to variations in this parameter.
Sort the amp, instead of looking for perfect transistors that don't exist.
Would you care to comment on the philosophy of matching the RC time constants as described? I am always open to modifying my beliefs/recommendations particularly if backed up by contrary, but well argued, evidence. |
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| MikeB |
| quote: | Originally posted by AndrewT
Sort the amp, instead of looking for perfect transistors that don't exist.
Would you care to comment on the philosophy of matching the RC time constants as described? I am always open to modifying my beliefs/recommendations particularly if backed up by contrary, but well argued, evidence. |
Andrew, about the RC times, i choosed that input filter in the original symasym because it seemed the best compromise between bandwidth and linear inputimpedance up to ~20khz. Symasym can be forced to slewrate limits with inputsignal, but seemed to be no problem.
About the highpass, that's my fault, i always forgot to adjust it.
About the cause of the unstable biasing, i don't know what causes it here, the original symasym has very stable biasing. I suspect that the very low Vce (caused by the cascodes) to the devices in 2nd diffamp causes large variations in vbe from thermal changes. In the worst case you have to replace the 68ohm by a ccs.
On the other hand, with that low Vce, how can these devices heat up?
Roender, are you sure that these 2 transistors are the problem, and not surrounding parts like cascode/LED ? Have you measured VCE to the LTP devices?
Mike |
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| roender |
Hi Mike, Andrew,
Thank you for your care.
I made a small experiment with a help of a small piece of ice cube covered in a plastic bag and placed over all bjt peers. Definitely second LTP is the culprit for thermal runaway ... actually is not a true runaway, is only a very slowly bias stabilization (30-40min). What is worse is bias sensitivity at cold air, it decrease very sharply at a small airflow like an open window or a person running in my lab room - Andrei, my 3 years old child :nownow: :D
The VAS LTP Vce at cold is 710mV and after warming up 690mV. |
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| roender |
| quote: | Originally posted by jacco vermeulen
Mihai,
don't you agree that you end up in Tokyo if you need something with better than 300MHz, 2.5pF, 500 hFe and low noise ? |
Yes Mr. Vermeulen,
Here in Romania is very hard to get most of the Japanese BJTs, same like the silver mica caps :D
Where is located your source of such yummies? |
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| MikeB |
| quote: | Originally posted by roender
The VAS LTP Vce at cold is 710mV and after warming up 690mV. |
I guess you meant Vbe? This is a 3% variance... The Vbe values set the bias in 2nd stage.
What are your differences in outputstage bias?
Mike |
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| roender |
No Mike, is VCE. I don't measure yet VBE
The bias variance in outputstage is 40-45mA |
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| AndrewT |
Hi,
Vbe~=650mV and Vce=690 to 710mV.
Does that mean the VAS are saturated?
If so then you will be getting wierd characteristics.
I would reset the cascode reference to give at least 2Vce or maybe as high as 5Vce.
BTW,
what you are describing does not sound like hFE variation, more like Vbe variation with temp. Again abolutely normal for all transistors. |
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| wojtek5001 |
Maybe just try connect anode of D8 to LTP emiters instead VCC.
By the way.. this configuration always look very risky for me. If voltage
on R18 is so low, then small change VBE (due to temperature drift for
example) can largely change VAS bias. Mayby do as MikeB suggested: replace R18 with ccs? |
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| CBS240 |
:yes:CCS for R18. R21 & R22 are the reference for the second diff emitter voltage. Loose D6 & D7.
:idea:If you tied R21 & R22 to the emitters of the second diff instead of the positive rail, with a CCS for R18, there would be no voltage reference for the emitters and it will fall out of bias. Now if you then use a P-channel J-fet, with a source resistor to the positive rail, gate to the emitters of the second diff, and the drain to the source resistor on J3 to control the bias current of the first diff to bias correctly the second diff in sort of a common mode bias feedback loop. Both differentials' bias currents would then be referenced to the source current of the CCS in place of R18. Do you guys think this approach could achieve better CM operation and bias stability? Opinions?
:2c: |
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| MikeB |
| quote: | Originally posted by CBS240
:yes:CCS for R18. R21 & R22 are the reference for the second diff emitter voltage. Loose D6 & D7.
:2c: |
D6/7 can't be skipped, without them the 2nd diffamp would enter badly reversebias when amp clips.
A high CMRR is not needed for 2nd diffamp as it is fed balanced by first diffamp, creating minimal voltage changes to r18 during normal operation.
Roender, have you already measured vbe variance in 2nd diffamp?
How big is the bias change in vas? (simply measure V across r18)
"bias variance in outputstage is 40-45mA", does that mean bias in outputstage varies by 40ma, or between 40-45ma?
Most of the amplifiers have a vas bias dependent on the Vbe of the vas devices, typically even much stronger than here, using emitter resistors to vas devices much smaller than 68ohm.
A ccs shouldn't be necessary here.
Maybe the outputstage is too sensitive to vas bias variation?
My suggestions:
- try a diode in series to the LED, this will increase Vce to the diffamp devices by 0.6v, maybe they are too close to Vce-sat
- try 2n5401 instead of bc560c, you don't need very high hfe here.
Mike |
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| roender |
Variation over VAS 68ohm tail resistor:
275mV ~ 4.04mA at room temperature
343mV ~ 5.04mA hot
LTP current variation (on negative rail CCS)
4.77mA at room temperature
5.03mA hot
I_final stage variation (on a single pair of final devices)
75mA cold
119mA hot |
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| roender |
| quote: | Originally posted by MikeB
My suggestions:
- try a diode in series to the LED, this will increase Vce to the diffamp devices by 0.6v, maybe they are too close to Vce-sat
Mike |
But we will loose some output swing voltage ... :bawling: |
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| MikeB |
| quote: | Originally posted by roender
Variation over VAS 68ohm tail resistor:
275mV ~ 4.04mA at room temperature
343mV ~ 5.04mA hot
LTP current variation (on negative rail CCS)
4.77mA at room temperature
5.03mA hot
I_final stage variation (on a single pair of final devices)
75mA cold
119mA hot |
The variation in 1st stage is bad... That changes the output from 1st stage, changing bias. ~0.15ma over 470ohm gives a change of ~70mv, quite exactly the bias drift you measured at r18...
Looks like the 2bjt-ccs was a better choice here. (the sensing bjt keeps cold having vce of ~1.2v, heating it up even lowers the current supplied)
The variation at output from 1st stage in my symasym was ~1-2mv... thats ~30 times less.
Can you confirm that by measuring r21/22?
Mike |
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| roender |
| quote: | Originally posted by MikeB
Can you confirm that by measuring r21/22?
Mike |
The voltage over r21/22 is 925mV at room temperature (1.968mA) and 960mV after the amp became warm (2.043mA) => deltaV=35mV
This is only one part of the problem because the LTP CCS has a short settle time, 1-2min.
The other part of our problem is in VAS LTP. BC560c has a very sensitive hfe/Vbe with temperature |
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| CBS240 |
Hi Mike,
Sorry for trying to change your circuit around, that was bad form. You are correct that a CCS is not really needed. However, I wonder if using an active bias would correct for the changes in temperature. In this simplified sketch, the idea is to balance the bias currents of both LTP's on Vgs of the p-channel j-fet (I X R18) with a control loop so that if Hfe and Vbe change with temperature, the p-channel j-fet adjusts the bias source of the first LTP to correct the voltage across R21 & R22 to maintain a constant current in the second LTP regardless of Vbe. Choose a source resistor so the j-fet will self bias across R18, at the point where the transfer characteristics have no change in Vgs vs Id with regard to temperature. The j-fet's temperature would not change as much anyway and thus both circuits' bias would not be as temperature dependent. All this may be valid...
Of course then agian, I might just have had too many beers, eh? :drink: |
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| wojtek5001 |
Did You sad :"The VAS LTP Vce"? if that means Q8 and Q9 Vce, then their Vbe or beta variations has not much to do with their Vce, which is determined by Q14, Q16 and D8.
A second thing: D4 and D5 has large dynamic resistance. If you use some kind Vbe-multiplier (Vd4 and Vd5 dependent), then output stage bias will be much less depend on VAS bias. |
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