| Fanuc |
Hello,
A good while back some one posted this to work out 300W rms into a 8 ohms load. Obviously there will be some voltage lost etc. due to rail sag, device/CCS headroom etc and so on.
Now a question I have is this is obviously for a resistive load and not a reactive load. I was wondering how to factor in phase margins in to the equations.
I am beleiver in having serious current available for low impedance but even a 2 ohm load calculation does not factor in the phase margin.
Just wondering if anyone has a good link or post regarding working this out. I have heard of a 60 degree phase margin being touted about but i wonder what we should really aim for assuming floorstander speakers as a ballpark figure.
Any help/advice appreciatted
Kevin
To work out the voltage rails required all you need to know is:
P = I x V (1)
and
V = I x R (2)
Combining the two gives:
P = V^2 / R (3a)
or V^2 = P x R (3b)
where P = RMS power, I = RMS current, V = RMS voltage and R = resistance, or impedance in this case.
For 300W RMS @ 8 ohms, and using equation (3b):
V^2 = P x R = 300 x 8 = 2400
Therefore V = sqrt(2400) = 48.99V (RMS)
To get peak voltage we have to multiply this by sqrt(2):
V(Peak) = 48.99 x 1.414... = 69.28V
As you said, there will be losses, so you will want a few volts higher than this to achieve the required 300W @ 8 ohms. |
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| unclejed613 |
actually the phase margin is most important with capacitive loads, and not so important with inductive loads. the reason is that there are phase delays in EVERY amp, and they are unavoidable, and they effect the stability of an amp. the better the phase margin, the better the amp can drive capacitive loads without oscillating. the phase margin is derived by measuring the output phase across the whole unity gain bandwidth of the amp, and subtracting the highest phase angle from 180 degrees. if the amp phase angle crosses 180 degrees before reaching the unity gain frequency of the amp, the amp is prone to oscillation at that frequency, and is unstable. if your phase margin is less than about 45 degrees, you want to avoid capacitive loads. 60 degrees is really good, and probably would be stable with capacitive loads.
the unity gain frequency of most amps is somewhere around 1-3 MHZ |
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| jcx |
you have the language slightly wrong, load phase angle is not "phase margin"
[edit: crossing posts; #2 above relates to "phase margin", below I show a sim that calcs device power when the load current phase angle varies - approximating a complex impedance load]
sim can do this too, LtSpice calcs device pwr (hold down alt after tran analysis, click on device body when thermometer appears)
E = sine Voltage
Z = impedance magnitude
phase = load phase angle (degrees) - stepped from 0 to 90 in 30 deg increments
approx slightly off from using independent Isource as load but close enough for most purposes
The huge peak device power with 90 degree (pure imaginary) load is clearly visible in the plots
LtSpice file, runs in free Linear Technology Switchercad iii
http://www.linear.com/company/software.jsp
(rename without .txt) |
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| AndrewT |
Hi Fanuc,
Bensen posted a spreadsheet that combined load phase angle with FET output stage and incorporated device SOA to allow modelling of reactive loads vs SOAR.
This is based on an article by David Eather, "A Practical Approach to Amplifier Output Design", Silicon Chip, February 1991, pp.14~18 and April 1991, pp.64~67
I have modified that sheet for FETs and for BJTs and included temperature derating, second breakdown, protection locus (for some BJTs).
Email if you require copies. |
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| Fanuc |
Hello,
Thanks for the replies. Yeah you were right JCX, I shouldn't of used the term phase margin - this caused some confusion. Sorry about that. Should be load phase angle!
| quote: | Originally posted by jcx
you have the language slightly wrong, load phase angle is not "phase margin"
[edit: crossing posts; #2 above relates to "phase margin", below I show a sim that calcs device power when the load current phase angle varies - approximating a complex impedance load]
|
Thanks for the simulation looks interesting.
A question for you by the way (off topic), regarding Walt Jung's super regulator. I remember you discussing with Walt about using a different type of compensation that permitted large C's on the output. Is it difficult to use that sort of compensation ?
| quote: | Originally posted by AndrewT
Hi Fanuc,
Bensen posted a spreadsheet that combined load phase angle with FET output stage and incorporated device SOA to allow modelling of reactive loads vs SOAR.
This is based on an article by David Eather, "A Practical Approach to Amplifier Output Design", Silicon Chip, February 1991, pp.14~18 and April 1991, pp.64~67
I have modified that sheet for FETs and for BJTs and included temperature derating, second breakdown, protection locus (for some BJTs).
Email if you require copies. |
I would love a copy Andrew if you would. Thanks
Kevin.dabson(@)gmail.com - Please remove the brackets |
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| Bonsai |
| Fanuc, yes Walt Jung SR is off topic. I ran some simulations and yep, it does not like it. It scared me off using these other than for localised regulation. |
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| G.Kleinschmidt |
Here is a little program I wrote a while ago for this kind of thing.
It's only very primitive; the green line is the 1sec SOA for the MJL21193/4. The program does not allow for temp-derating, but it will tell you important things such as the average and peak power dissipations of both the transistors and the load for 0-90 degree phase shift.
This information can give you an instant idea of your heatsinking requirements (which is what I mostly wrote the program for).
One day I'll write a fully featured version, with the SOA's for all popular audio output devices included, with temperature derating of the SOA curves, as well as Iq selection to make it usefull for class A designs as well.
The .exe file here:
http://homepages.picknowl.com.au/glenk/calc.exe
For the program to run, this file must be placed in the same folder:
http://homepages.picknowl.com.au/glenk/VBRUN300.DLL
Cheers,
Glen |
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| Fanuc |
Hello Glen,
Nifty! I like it! |
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| G.Kleinschmidt |
| quote: | Originally posted by Fanuc
Hello Glen,
Nifty! I like it! |
No worries :)
Oh, and in case anyone is wondering, the average transistor and load power dissipation values are not calculated nor approximated with a simple formula.
The program computes the average from the summation of the several thousand instantaneous current and voltage calculations made to plot the graph. In other words, they’re rather accurate.
Cheers,
Glen |
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| G.Kleinschmidt |
One minor little idiosyncrasy of my program that’s worth a mention (before someone picks me out on it :D ) In order to calculate a pedantically accurate power dissipation figure for the output transistors, the program takes into account the power dissipated in the emitter ballast resistors. The “Vpeak Load” setting in this regard is a bit misleading. The voltage set by this slider bar is in fact the voltage at the emitter(s) of the output transistor(s). This is why, when you change the “Emitter res.” value, you’ll see the load voltage and current values alter slightly. In order to compensate for the voltage drop across the ballast resistor(s), you just have to bump the “Vpeak Load” value up a little bit.
I never got around to adding the single line of code required to do this compensation automatically!
Cheers,
Glen |
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| AndrewT |
Hi,
average power dissipation of the output devices in reactive loads sounds very useful.
That allows one to insert sensible Tc values into Bensen's sheet to see the long term and transient excursion towards the dre-rated SOARs. |
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| janneman |
| quote: | Originally posted by G.Kleinschmidt
One minor little idiosyncrasy of my program that’s worth a mention (before someone picks me out on it :D ) In order to calculate a pedantically accurate power dissipation figure for the output transistors, the program takes into account the power dissipated in the emitter ballast resistors. The “Vpeak Load” setting in this regard is a bit misleading. The voltage set by this slider bar is in fact the voltage at the emitter(s) of the output transistor(s). This is why, when you change the “Emitter res.” value, you’ll see the load voltage and current values alter slightly. In order to compensate for the voltage drop across the ballast resistor(s), you just have to bump the “Vpeak Load” value up a little bit.
I never got around to adding the single line of code required to do this compensation automatically!
Cheers,
Glen |
Hi Glen,
I am working on a spreadsheet to caslculate protection circuit component values related to SOA and (reactive) load lines. Problem is (for me and MS Exel) that it is difficult to have a Vce - Ic based graph and include the reactive load line into it.
There are a whole family of reactive load lines dependent on instanteneous frequency anyway, isn't it.
Douglas Self recommends using a straight line as the "envelope" of all possible reactive lines.
The result wopuld be as follows. Suppose you have 8 ohms resistive, this is a line through Ic=0, Vce=Vsupply (ignoring losses etc) and Vce=0, Ic=Vsupp/Rload; then the envelope of all possible reactive 8 ohms load lines would be a line through Ic=0, Vce=2*Vsupply, and Vce=0, Ic=Vsupp/8ohms.
Can you agree to this logic?
Jan Didden |
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| mikeks |
| quote: | Originally posted by janneman
Douglas Self recommends using a straight line as the "envelope" of all possible reactive lines.
Jan Didden |
Douglas Self is wrong in this regard. |
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| AndrewT |
Hi Janneman,
have you read David Eather, "A Practical Approach to Amplifier Output Design", Silicon Chip, February 1991, pp.14~18 Part 1 and Part 2 of the same article, from Silicon Chip, April 1991, pp.64~67
appendix 4 of http://home.alphalink.com.au/~cambi...Web.htm#DiffAmp
The number cruching in there was the basis of Bensen's spreadsheet. It shows SOAR and reactive load lines on log/log graphs. Excellent for constant value signals.
I don't know how it could be extended to transient signals. The transient SOAs are easily added on. It's the transient signals and transient protection locus that I cannot get to. |
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| janneman |
Andrew thanks, I will study the material.
I'm not at transient stuff yet, but have got the steady-state stuff pretty well covered I think. except that reactive load line.
Jan |
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| janneman |
| quote: | Originally posted by mikeks
Douglas Self is wrong in this regard. |
Mike,
Any pointers to how I should approach it?
See attached.
Jan Didden |
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| mikeks |
| Refer to SOA prot. paper. |
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| AndrewT |
Hi,
I started with graphs like your PDF posting.
I could not make sense of it when trying to extend to reactive loads.
Bensen pointed me to Eather. |
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| janneman |
| quote: | Originally posted by mikeks
Refer to SOA prot. paper. |
Yes, I know exactly where it is. Some 228km from here. It'll have to wait till Friday...
Jan |
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| janneman |
| quote: | Originally posted by AndrewT
Hi,
I started with graphs like your PDF posting.
I could not make sense of it when trying to extend to reactive loads.
Bensen pointed me to Eather. |
Andrew, Mike,
Thanks, but I think I posed the wrong question. I know how to calc the reactive loadline, see attached.
The problem is that I cannot for the life of me get that graph on the SOA graph.
This maybe an Exel issue. The SOA graph is organized as pairs Vce, Ic, in increasing Vce.
The reactive thing is in increasing phi and also the steps are unlike the SOA Vce steps. If i include the columns of the reactive table with the SOA tables it looks gobbledigook...
Jan Didden |
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| Fanuc |
| quote: | Originally posted by mikeks
Refer to SOA prot. paper. |
Hello Mikeks,
A question I was going to ask you as we are talking about protection circuits now. Is why Douglas Self in his designs and other amps that use miller comp. do not include a current limiter over the base of the VAS to offer protection on the negative swing on a output short circuit.
The CCS for the VAS offers protection on a output short circuit on the positive going swing.
Or is this to do with the current limiter interfering with the miller compensation and causing instability or something like that ?
Not sure on that one.
Kevin |
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| Fanuc |
| Coming to think of it, maybe this only applies when the VAS drives the outputs directly. |
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| janneman |
| quote: | Originally posted by G.Kleinschmidt
Here is a little program I wrote a while ago for this kind of thing.
It's only very primitive; the green line is the 1sec SOA for the MJL21193/4. The program does not allow for temp-derating, but it will tell you important things such as the average and peak power dissipations of both the transistors and the load for 0-90 degree phase shift.
This information can give you an instant idea of your heatsinking requirements (which is what I mostly wrote the program for).
One day I'll write a fully featured version, with the SOA's for all popular audio output devices included, with temperature derating of the SOA curves, as well as Iq selection to make it usefull for class A designs as well.
The .exe file here:
http://homepages.picknowl.com.au/glenk/calc.exe
For the program to run, this file must be placed in the same folder:
http://homepages.picknowl.com.au/glenk/VBRUN300.DLL
Cheers,
Glen |
Hi Glen,
Nice little gem!
I understand it assumes an inductive load? Any way to use neg phase shift as in cap load?
jan Didden |
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| AndrewT |
Hi Janneman,
here's how Bensen did it for a FET. http://www.diyaudio.com/forums/atta...tamp=1116447049
If you want to see a BJT version with second breakdown then Email me.
Hey,
you stole my word "gobbledigook...":xeye: I charge a licence fee on it's usage;) |
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| AndrewT |
| quote: | Originally posted by Fanuc
Hello Mikeks,
A question I was going to ask you as we are talking about protection circuits now. Is why Douglas Self in his designs and other amps that use miller comp. do not include a current limiter over the base of the VAS to offer protection on the negative swing on a output short circuit.
The CCS for the VAS offers protection on a output short circuit on the positive going swing.
Or is this to do with the current limiter interfering with the miller compensation and causing instability or something like that ?
Not sure on that one.
Kevin |
Leach protects the VAS. |
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| janneman |
| quote: | Originally posted by AndrewT
Hi Janneman,
here's how Bensen did it for a FET. http://www.diyaudio.com/forums/atta...tamp=1116447049
If you want to see a BJT version with second breakdown then Email me.
Hey,
you stole my word "gobbledigook...":xeye: I charge a licence fee on it's usage;) |
Yes! That did it, it dawned on me when I saw how he combined those graphs. Now I can even combine graphs from different Exel files!
Thanks,
Jan Didden |
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| janneman |
| quote: | Originally posted by AndrewT
[snip]Hey,
you stole my word "gobbledigook...":xeye: I charge a licence fee on it's usage;) |
How about 'pupucaca', that still free?:D
Jan |
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| Fanuc |
| quote: | Originally posted by AndrewT
Leach protects the VAS. |
I've never seen the full leach schematics you have have referred to, including the full compensation etc but if I recall from memory he uses a fully complimentary input stage and different VAS arrangement.
Also we do not know what happens when C.dom becomes current starved by the Input stage when the current limiter activates. Slew rate would definately be affected.
Frankly I don't have a clue, but there seems to be alot of designers of miller amps that exclude protection of the VAS for some reason.
Maybe Mikeks could enlighten us..... |
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| mikeks |
| quote: | Originally posted by Fanuc
I've never seen the full leach schematics you have have referred to, including the full compensation etc but if I recall from memory he uses a fully complimentary input stage and different VAS arrangement.
Also we do not know what happens when C.dom becomes current starved by the Input stage when the current limiter activates. Slew rate would definately be affected.
Frankly I don't have a clue, but there seems to be alot of designers of miller amps that exclude protection of the VAS for some reason.
Maybe Mikeks could enlighten us..... |
The "VAS" needs protection if such is used in the output stage. |
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| G.Kleinschmidt |
| quote: | Originally posted by janneman
Hi Glen,
Nice little gem!
I understand it assumes an inductive load? Any way to use neg phase shift as in cap load?
jan Didden |
G'day Jan.
The I phase shift can be either leading or lagging. It doesn't make any difference to the plotted reactive load lines.
Cheers,
Glen |
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| G.Kleinschmidt |
| quote: | Originally posted by janneman
Douglas Self recommends using a straight line as the "envelope" of all possible reactive lines.
The result wopuld be as follows. Suppose you have 8 ohms resistive, this is a line through Ic=0, Vce=Vsupply (ignoring losses etc) and Vce=0, Ic=Vsupp/Rload; then the envelope of all possible reactive 8 ohms load lines would be a line through Ic=0, Vce=2*Vsupply, and Vce=0, Ic=Vsupp/8ohms.
Can you agree to this logic?
Jan Didden |
Unfortunately, I do not agree. It simply isn't possible to approximate with a decent degree of accuracy all possible reactive load lines with a single straight line, least of all an "envelope" to safely inclose them.
Having a play with that spreadsheet Andrew mentioned or my program will give you a good idea of just how dramatically the shape of the load lines change when the load becomes reactive.
Cheers,
Glen
Edit:
On second thoughts, the method you describe would probably be an adequate compromise for simple, fixed I-limiting output device protection.
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| Pingrs |
I’ve spent many happy? hours calculating and manipulating Mikeks’s (fig 27) method for dual slope protection in order to utilize standard resistor values where possible. Eventually I attempted an Excel spreadsheet model (my first!) based on Mike’s article to ease this task.
I then applied the Bensen arrangement (an invaluable source of inspiration) alongside this to display the SOA and load lines, in linear form to fit in with the protection slopes. Working with log-log’s isn’t intuitive, to me.
By inputting the required data, it may be useful as a general model.
It is with much trepidation that I attach this, since I’m no mathematician, much less a macro-modeller, so if I could impose upon those who are to corroborate, or demolish (and correct?), I would be grateful.
Best regards,
Brian. |
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| janneman |
| quote: | Originally posted by G.Kleinschmidt
Unfortunately, I do not agree. It simply isn't possible to approximate with a decent degree of accuracy all possible reactive load lines with a single straight line, least of all an "envelope" to safely inclose them.
Having a play with that spreadsheet Andrew mentioned or my program will give you a good idea of just how dramatically the shape of the load lines change when the load becomes reactive.
Cheers,
Glen
Edit:
On second thoughts, the method you describe would probably be an adequate compromise for simple, fixed I-limiting output device protection.
|
Hi Glen,
I was not really happy with Doug Self's recommendation either; he didn't elaborate on it. I have since found out how I can include a reactive load line, calculated separately, in the graph of the SOA and protection loci.
I am using the spreadsheet to automagically calculate the protection circuit component values interactively by setting the breakpoints on the graph to follow any required shape with two breakpoints.
Jan Didden |
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| janneman |
| quote: | Originally posted by Pingrs
I’ve spent many happy? hours calculating and manipulating Mikeks’s (fig 27) method for dual slope protection in order to utilize standard resistor values where possible. Eventually I attempted an Excel spreadsheet model (my first!) based on Mike’s article to ease this task.
I then applied the Bensen arrangement (an invaluable source of inspiration) alongside this to display the SOA and load lines, in linear form to fit in with the protection slopes. Working with log-log’s isn’t intuitive, to me.
By inputting the required data, it may be useful as a general model.
It is with much trepidation that I attach this, since I’m no mathematician, much less a macro-modeller, so if I could impose upon those who are to corroborate, or demolish (and correct?), I would be grateful.
Best regards,
Brian. |
Brian, looks good!
I do something similar but with a different circuit. I never felt quite comfortable with Mike's circuit, too many variables to juggle!
I have two zeners in my ciruit to set the breakpoints, but I can use the Exel solver to manipulate one or more values to get to (at least one) "nice" zener value.
Jan Didden |
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| Pingrs |
Thanks, Jan,
I'd love to see your method.
Regards,
Brian. |
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| janneman |
Brian, Glen,
Please se the attached.
There is a Icprot protection locus (plus the Spice results; not quite the same, but I'm working on it;) ). But that's not my point right now.
You also see that the reactive (8 ohms @ -45 deg) load line is inside the 100mS SOA but outside the DC SOA.
My question is: would you accept this SOA situation, because since the reactive load only comes into play at AC signals, the lowest audio is 20Hz or more, and the reactive line is within the 100mS (10Hz equivalent) SOA?
Jan Didden |
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| mikeks |
| quote: | Originally posted by janneman
Brian, Glen,
Please se the attached.
There is a Icprot protection locus (plus the Spice results; not quite the same, but I'm working on it;) ). But that's not my point right now.
You also see that the reactive (8 ohms @ -45 deg) load line is inside the 100mS SOA but outside the DC SOA.
My question is: would you accept this SOA situation, because since the reactive load only comes into play at AC signals, the lowest audio is 20Hz or more, and the reactive line is within the 100mS (10Hz equivalent) SOA?
Jan Didden |
A 100mS pulse represents a frequency of roughly 5Hz (unity mark-space ratio assumed).
Thus we can reasonably assume that these pulses are outside the audio band.
Solution:
Design for your DC SOA and then apply single or double pole filter attenuating these pulses by say 0.5 at ten times 5Hz.
In other words you're right. |
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| janneman |
| quote: | Originally posted by mikeks
A 100mS pulse represents a frequency of roughly 5Hz (unity mark-space ratio assumed).
Thus we can reasonably assume that these pulses are outside the audio band.
Solution: Design for your DC SOA and then apply single or double pole filter attenuating these pulses by say 0.5 at ten times 5Hz.
[snip] |
Mike, thank you. Most helpful.
But if I attenuate this lf signals it will destroy my freq response, or did I misunderstand you?
I need to somehow protect the amp against short circuit and that is the DC SOA at the supply voltage. I cannot at the same time do a short circuit protection AND a, say 100mS SOA protection against signals above a few 10's of Herz.
| quote: | Originally posted by mikeks
[snip]In other words you're right. |
I think I will frame this and hang it on my lab wall :D
Jan Didden |
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| AndrewT |
Hi,
filter the protection signal sent to the base of the trigger transistor.
Then you can set up the DC protection to match the DC SOAR and use the filter to allow transient peaks to be attenuated before the trigger activates.
A very short transient could reach 2 to 3 times the DC current and a longer duration transient maybe just 150% of the permitted DC current. These variable attenuation values follow roughly what a low pass filter lets through to the base and match up with the transient SOAs that are published.
Can some one tell me how to test/measure that the trigger is operating at the predicted levels on both DC and longer term transients?
A word of caution.
The manufacturers state consistently that the transient values apply to single shot currents only. A long term note could pass many hundred of cycles and the one shot limits must surely be reduced for repeated cycles.
I suggest that a 1mS current limit repeated 10 times should remain under the 100mS SOA, similarly 100uS transient under the 1mS SOA. What do you think?
A mid or treble frequency tends to be quite short duration, in terms of number of cycles that are repeated, whereas a bass note may repeat for considerably more cycles.
I think that bass note overload should be the criterion to design for and that 100mS SOA is inappropriate if the one decade reduction rule is applied. Keep in mind that the filter will still attenuate and thus let through short term peak and thus delay triggering on single event overloads.
Pingrs,
I note that you have de-rated Vce for operational Tc values. I think you should be de-rating Ic. The effect is not the same. Have a look at your log/log graph and compare it to the data sheet graph. The permissible maximum Vce is not reduced, it is the permissible current that is reduced. Similarly the max current value should be reduced for increased Tc. The graphical effect is to move the whole graph downwards rather than sideways. Mathematically both reductions are easily achieved. Any further thoughts? |
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| janneman |
| quote: | Originally posted by AndrewT
Hi,
filter the protection signal sent to the base of the trigger transistor.
Then you can set up the DC protection to match the DC SOAR and use the filter to allow transient peaks to be attenuated before the trigger activates.
A very short transient could reach 2 to 3 times the DC current and a longer duration transient maybe just 150% of the permitted DC current. These variable attenuation values follow roughly what a low pass filter lets through to the base and match up with the transient SOAs that are published. [snip] |
... but of course, I didn't read that in it. In fact, I have it in my circuit. :xeye:
| quote: | Originally posted by AndrewT
[snip]Can some one tell me how to test/measure that the trigger is operating at the predicted levels on both DC and longer term transients?
[snip] |
I am using a circuit developed by Peter Baxandall of Quad. It involves loading the amp with 40uF in series with 1 ohms. Then drive it with a 20Hz sinewave, superimposed on which are short (50uS) pulses with a 500Hz rate. The sine does exercise the Vce (without actually loading the amp because of the 20Hz/40uF), but the (asynchronous) pulses cause high current load pulses at varying Vce's. So the protection circuit moves through the 'landscape' of all possible Vce/Ic combinations.
If you now make an x-y display of Vce and Ic you will see that envelope of the allowed combinations of Vce and Ic.
I did get it to work but not really as well as Baxandall described in his article; it's still a work in progress.
Jan Didden |
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| mikeks |
| quote: | Originally posted by janneman
Mike, thank you. Most helpful.
But if I attenuate this lf signals it will destroy my freq response, or did I misunderstand you? |
Yes you misunderstood. The filters are implemented in the SOA protection network. |
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| janneman |
| quote: | Originally posted by mikeks
Yes you misunderstood. The filters are implemented in the SOA protection network. |
Indeed. I have those in as well, just didn't realise that was meant. My bad.
Jan Didden |
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| G.Kleinschmidt |
| quote: | Originally posted by janneman
Brian, Glen,
Please se the attached.
There is a Icprot protection locus (plus the Spice results; not quite the same, but I'm working on it;) ). But that's not my point right now.
You also see that the reactive (8 ohms @ -45 deg) load line is inside the 100mS SOA but outside the DC SOA.
My question is: would you accept this SOA situation, because since the reactive load only comes into play at AC signals, the lowest audio is 20Hz or more, and the reactive line is within the 100mS (10Hz equivalent) SOA?
Jan Didden |
Looks good to me! |
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| janneman |
| quote: | Originally posted by G.Kleinschmidt
Looks good to me! |
Thanks! |
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| Fanuc |
| quote: | Originally posted by janneman
Thanks! |
Hello Jan,
Slightly off topic!!...we can attribute that to the bourbon effect ie. Jack D etc :) I prefer Scotch malt anyway....
A problem I am having at the moment is sourcing or trying to obtain the PCB's you designed for the super regulators when the AA article was done in '95.
I am not interested in ALW's pcb's or others people's PCBs.
The last time I seen them for sale was from Audio Xpress, they do not appear to sell them anymore, and I can not no longer locate any. If you know of any sources that would be great!
Alternatively, if you have any detailed photo's, gerber files of the PCB that would be great. I would still need to modify them for two or three reasons.
Anyway my e-mail is
kevin.dabson(@)gmail.com - Please remove the brackets.
Thanks Kevin
PS. I am glad I never showed vulnerability (dumbness) in asking about Pdiss into reactive loads! |
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| janneman |
Kevin,
I'm sorry but I no longer have any files for these boards. They were done long time ago, and they disappeared during one of my frequent moves.
However, they are still for sale at audioXpress:
http://www.audioxpress.com/bksprods...ts/pcbd-3ab.htm .
Alternatively, I think ALW's boards are excellent and more flexible than my boards. Don't know about the pricing though.
Jan Didden |
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| AndrewT |
Hi all,
you have gone very quiet.
Any comment on survival of output devices when repetitive transient currents are passed that match the single shot limits set by the device manufacturers?
Any feedback on de-rating currents for the operational Tc at each Vce rather than de-rating Vce? |
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| janneman |
Anderw,
Give me a break, I have a job to take care of!;)
That single shot thing is not clear to me. I assume that if I do a single shot today I can do another one tomorrow? So, what's the duty cycle of a single shot? One per second, after thermal eqilibrium has been restored?
I have not yet looked at the current derating with temperature, been busy to get Exel do my bidding rather than having all numbers exactly right. But yes, that has to be confronted.
Jan Didden |
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| AndrewT |
Hi Janneman,
I am asking all for their comment, you have already nailed your 100mS to the flagpole. A couple have agreed with you.
Let's look at a senario.
one single shot at the 100uS limit, followed by 100 current excursions that are near the 1mS limit and also many thousand excursions approaching the DC current limit for each of the Vce that are existing at the time of each transient.
When does the junction get a chance to return to quiescent conditions? When one replaces the disc for another?
Will the next 100uS current transient prove too much?
I cannot see a method of calculating this.
I suspect manufacturers test to destruction and assess what they had to do to make it fail, then compare real life conditions to the failure conditions and either release the product to market, or make it more robust, or make it cheaper. The last two of course requiring more testing.
As earlier, limiting the single shot to a lower limit may give enough reserve to pass all the other peaks without the junction suffering damage. But this is just my best guess. Quasi some time ago confirmed he designs for 100mS, I design for DC and hopefully the filtered protection allow much higher but short term transients to pass without triggering the protection. My method may be far too conservative. Maybe push the protection locus much higher to allow all extreme signals to pass through without interfering with sound quality.
I would like to hear other opinions. |
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| Pingrs |
Andrew,
Thanks for your comments.
"I note that you have de-rated Vce for operational Tc values. I think you should be de-rating Ic. The effect is not the same. Have a look at your log/log graph and compare it to the data sheet graph. The permissible maximum Vce is not reduced, it is the permissible current that is reduced. Similarly the max current value should be reduced for increased Tc. The graphical effect is to move the whole graph downwards rather than sideways. Mathematically both reductions are easily achieved. Any further thoughts?"
I take your point, and I must admit it was with some uncertainty that I used the Vce to derate, but this appeared to be the way the Bensen data applied it, so I sought more info, and came across the OnSemi application note AN875 (as commented in the table) which discussed derating Vce, since that was the more vulnerable parameter (at least, that’s the way I read it). On that basis I chose to do it that way.
Paragraphs from AN875.(OnSemi)
Perhaps I have totally misread the intentions of this note.
You have an excellent reputation for knowing what you’re talking about, so I’ll try to effect the alterations you suggest. If I have any queries, may I contact you?
Best regards,
Brian.
I've noticed the AN875 quotes I've chosen are missing, so here's the doc. 1st para of "Voltage sensitivity" and start of page three apply. |
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| AndrewT |
Hi Pingrs,
thanks for the pdf.
First thought, where do the two different de-rating factors fit in, keeping in mind that the power de-rating still applies after the second breakdown? (not both factors applied together but that it's the lower of one or other).
I think there is an anomally.
(thinking on the hoof here)
what if we consider the knee of the SOA?
just above the knee the power de-rating clearly applies and at Tc=60degC factor=(150-60)/(150-25) = 0.72 for a 150degC plastic package.
just below the knee the second breakdown factor applies but this time a higher value of factor is applied (from the graph fig4. for Tc =60degC 2ndBkFactor=0.9)
A 200W device operating at 50Vce with the knee at exactly that same voltage (hypothetical ~=15003,15034,4281 & 2sa1943~45degC) the permissible current @ 49.99Vce is (200*0.72)/50=2.88Apk , above the knee the de-rated current is (200*0.9)/50=3.6Apk but we are told the lower power applies, so the effective peak current at 50Vce either above or below the knee is limited to 2.88Apk.
This lesser of the two rules effectively means that one has to calculate at what voltage the two rules predict the same de-rated power. At this higher voltage one will find that the power has been de-rated much less than second breakdown power*power de-rating factor i.e. a higher permissible power in the second breakdown region.
That is the anomally. Exactly where ONsemi are telling us that voltage sensitivity is critical their method allows a higher factor to be applied and the effect becomes worse as Tc increases. Again this is counter intuitive.
Is my logic out the window? is it a lower voltage where the predictions match?
Going back to de-rating Ic or Vce.
Read page 3 and the steps ONsemi ask you to follow. I'll paraphrase:-
select a voltage.
select the operating Tc.
choose the factor.
reduce the power.
divide by the voltage
the result is the de-rated current. not the de-rated voltage. |
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| Fanuc |
Hello Jan,
Thanks for the link. I must of missed it!
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| janneman |
| quote: | Originally posted by janneman
[snip]That single shot thing is not clear to me. I assume that if I do a single shot today I can do another one tomorrow? So, what's the duty cycle of a single shot? One per second, after thermal eqilibrium has been restored?[snip] |
Some further research showed me that the sibnle shot pulse is the maximum pulse power that can be absorbed and still keep the die below the max temp (generally 150deg Celcius), starting at the steady state temp, whatever that happens to be. It has to do with the transient thermal resistance from die to the package. So it's not single shot in the sense that it cannot be repeated. But if it is a repetitive puls that comes back before the die has cooled to the steady state temp, each "single shot" pulse has to be smaller because the temp rise starts above the steady state temp.
Does that make sense?
Jan Didden |
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| AndrewT |
Hi Janneman,
I agree.
a single shot starting from Tc=25degC (the graphs are plotted for such) and equal to the max extracted from the SOA will take the device to the manufacturers specified limit. The selected limit depending on whether it is a short pulse or a longer one.
What happens after that pulse becomes the history that affects the next pulse. If the histroy is adverse and the next pulse happens to also be at the limit then one has exceeded the specified limitations.
An adverse history could be any combination of the following.
a string of repeated low level signals, a few high level signals, a very few medium level pulses, a single high level pulse approaching a specified limit, anything that causes the Tc or Tj to be above the 25deg C condition just before the critical pulse arrives, including high ambient temperature.
That, I see as the problem. As the history becomes older it is less relevant, as the time frame shortens it is more relevant. A string of repeated high level pulses that are half of the 10us limit followed by a 100uS pulse at the 100uS limit all delivered in 1mS must be worse than a single shot arriving during a 25degC quiescent condition.
Then we apply the relevant Tc de-rating factor and go through the corrected pulse currents for the last few time increments. Electronically controlled or selected protection locii to achieve this sounds quite complex. There must be an economical method of suiting number of devices to the V-I requirement rather than simply pouring devices into the solution. DC SOAR approaches the pouring method, protection filtering moves towards more economical. |
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| janneman |
That's also how I see it, Andrew.
As far as the current derating is concerned, note that the protection transistor has a tempco that tends to automagically decrease the limit current at elevated temperatures (of the transistor).
Maybe we should look at mounting this transistor somewhere on the heatsink or near the output stage to follow the steady-state temp.
Then the transient stuff could be taken care of with lp filtering.
Jan Didden |
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| mikeks |
| quote: | Originally posted by Pingrs
........ discussed derating Vce, since that was the more vulnerable parameter (at least, that’s the way I read it). On that basis I chose to do it that way......... |
I think you'll find this more useful. |
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| janneman |
| quote: | Originally posted by mikeks
I think you'll find this more useful. |
Mike, this is a great document! Thanks,
Jan Didden |
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| Pingrs |
Mike,
Just read your post. Thanks for that.
I already have that doc., but I'm too dumb to see its relevance as to what to derate, V or I (or a combination?)
What's your opinion?
Best regards,
Brian. |
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| Fanuc |
OK as a design example, what if I wanted to drive a loudspeaker that went down to 2 ohms. (monkey box)
Quad ELS57, Logans & Magneplaner Ribbons and some others will drop very low at HF, but these are mostly exceptions to the rule. Most moving coil speakers will do this at LF. <500Hz.
If I wanted a amp to drive 2 ohms continoius into a moderately reactively load, what sort of load phase angle should one look for ?
30 degrees, 45 or even 60 degress.
Advice welcome :)
Kevin |
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| mikeks |
| quote: | Originally posted by Pingrs
Mike,
Just read your post. Thanks for that.
I already have that doc., but I'm too dumb to see its relevance as to what to derate, V or I (or a combination?)
What's your opinion?
Best regards,
Brian. |
You derate power (V*I)
Refer to attachment: |
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| AndrewT |
| quote: | Originally posted by Fanuc
OK as a design example, what if I wanted to drive a loudspeaker that went down to 2 ohms. (monkey box)
Quad ELS57, Logans & Magneplaner Ribbons and some others will drop very low at HF, but these are mostly exceptions to the rule. Most moving coil speakers will do this at LF. <500Hz.
If I wanted a amp to drive 2 ohms continoius into a moderately reactively load, what sort of load phase angle should one look for ?
30 degrees, 45 or even 60 degress.
Advice welcome :)
Kevin |
If the minimum impedance (or near it) occurs over a significant bandwidth and thus becomes the significant load for the time being considered then I would design for the minimum impedance. If wide phase angles also co-incided with that minimum impedance then I would design for the combination of low impedance and high phase angle. If the highest phase angles only applied when the impedance was well above minimum, then it seems that this new loading becomes a second operational condition to consider.
You may want to look at a series of these combinations and then pick the few that stress the output stage most severely.
low impedance at very high frequency (whether combined with high phase angle or not) will come in very short bursts (=real transients) and although they may repeat an extreme number of times each individual peak is very short. This is where I would look at 10uS peaks and use the 100uS current limit for that device/temp (if I had a speaker like that).
I take the easier route. I drive each half of the crossover with it's own amplifier. Bandwidth (and combinations likewise) to be considered is much reduced. |
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| janneman |
| quote: | Originally posted by mikeks
You derate power (V*I)
Refer to attachment: |
I would keep it simpler:
Given:
The transistor die rises 125deg wrt the case if it dissipates 200W.
Therefore:
If the case is already at 70deg, the allowed rise is only 150-70=80deg, thus allowed dissipation is (80/125)*200=128W. Right?
Jan Didden |
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| mikeks |
| quote: | Originally posted by janneman
I would keep it simpler:
Given:
The transistor die rises 125deg wrt the case if it dissipates 200W. |
True, but only if the case is at 25 deg. in the first place.
It is conceptually analogous to Ohm's Law: Current~Power dissipated, Voltage~Temp., Resistance~Thermal resistance.
This is the basis for my example and, somewhat less obviously, your analysis below.
| quote: | Originally posted by janneman
Therefore:
If the case is already at 70deg, the allowed rise is only 150-70=80deg, thus allowed dissipation is (80/125)*200=128W. Right? |
Right. |
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| janneman |
| quote: | Originally posted by mikeks
True, but only if the case is at 25 deg. in the first place.
It is conceptually analogous to Ohm's Law: Current~Power dissipated, Voltage~Temp., Resistance~Thermal resistance.
This is the basis for my example and, somewhat less obviously, your analysis below.
Right. |
Mike, that's two times in les than half a day you agree with someone else. You're losing your touch :D
Jan Didden |
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| AndrewT |
| I do like it when Mikeks actually takes the time to talk with us. |
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| john_ellis |
Hi all
some simple maths can be used to calculate phase angles and power.
Suppose we have a load impedance consisting of a series reactance z and resistance R. The current flow is V/(R+z). Get rid of the "j" in the denominator by multiplying by conjugate gives
i=V(R-z)/(R*R+z*z)
which gives the power in the load as the real term V*V*R/(R*R+z*z).
The phase angle is tan-1(z/R)
The power dissipated by the power transistors is simply the power supplied by the PSU minus the real power in the load as above. The power into the amplifier is Vcc*Iav, which does not care about phase angles as the average current is just the average current, whatever. Use the magnitude of the load [zeff=sqrt(R*R+z*z)]
to give the current and take sine-average Ipk*2/pi
In practice this means for a pure reactance the power trannys have to dissipate the full monty. Not a pretty sight when one supposes that the reactance dissipates nothing!
You have to consider the power dissipation as a function of frequency to calculate the worst case because z is frequency dependent. Having got the total power, the power per transistor can be calculated as an average for the frequency in question, giving a "power pulse" equivalent which you can use for heatsink calculations.
cheers
John |
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| Fanuc |
| quote: | Originally posted by john_ellis
Hi all
some simple maths can be used to calculate phase angles and power.
Suppose we have a load impedance consisting of a series reactance z and resistance R. The current flow is V/(R+z). Get rid of the "j" in the denominator by multiplying by conjugate gives
i=V(R-z)/(R*R+z*z)
which gives the power in the load as the real term V*V*R/(R*R+z*z).
The phase angle is tan-1(z/R)
The power dissipated by the power transistors is simply the power supplied by the PSU minus the real power in the load as above. The power into the amplifier is Vcc*Iav, which does not care about phase angles as the average current is just the average current, whatever. Use the magnitude of the load [zeff=sqrt(R*R+z*z)]
to give the current and take sine-average Ipk*2/pi
In practice this means for a pure reactance the power trannys have to dissipate the full monty. Not a pretty sight when one supposes that the reactance dissipates nothing!
You have to consider the power dissipation as a function of frequency to calculate the worst case because z is frequency dependent. Having got the total power, the power per transistor can be calculated as an average for the frequency in question, giving a "power pulse" equivalent which you can use for heatsink calculations.
cheers
John |
Where have you been John ? :)
A dissection of Bob Cordell's compensation schema would be most welcome. Lag over the drains of the jfet LTP, but does it improve HF THD with respect to the output stage? . Output stage error correction is ignored for the time being.
Also, dual pole on the lag of PLIL. Enticing.....
I asked you this as you seem pretty sharp!. It isn't a competition or anything but just wanted to know your views....
http://www.diyaudio.com/forums/show...755#post1160755
Post 764 on the BJT vs. MOSFET thread.
Look forward to your response.
Kevin |
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| mikeks |
So-called PLIL covered in detail here.
P.S. Check your mail, Kevin. |
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| Fanuc |
My first visit to the USA was indeed Boston, Massachusetts. The so-called third largest shipping dock of the British Empire. Had a good look around harvard and much more importantly MIT.
MIT wins for me, harvard scholars are too into law, when scientists where defying gravity and putting a man on the moon at 18,000mph....
Cultures are different no doubt. Do like USA though.
Now that is a different phase angle to a reactive load. :p |
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| john_ellis |
Hi Mikeks
Otala proposed, way back in 1973 in his (in)famous paper, to use input phase lag and phase lead compensation.
I used the term PLIL to describe an approach where Otala's recommendations were used, but instead of using local feedback, with conventional global feedback. There is nothing wrong with Otala's original recommendations. Only thing he got wrong it seems is the need for local feedback. Distortion with global nfb can be made a lot lower.
cheers
John |
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| mikeks |
| quote: | Originally posted by john_ellis
...Distortion with global nfb can be made a lot lower.
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True. :nod: |
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| unclejed613 |
monkey box?
how about a real PA bass cabinet or a musician pairing a couple of 4 ohm Ampeg bass cabinets..... i wouldn't exactly call these applications "monkey boxes"......
ahhh..... i think i just got it...... subwoofer boxes with the small round ports that one can reach into, but not remove one's hand if grasping something that fell into the box?...... actually i have repaired a few of these that had mice go into and gnaw the spider wires on the woofer, or the tasty insulation on the internal wiring....... i'm trying to come up with a way to keep mice out of these ports.... maybe a wad of fiberglass stuffed into the port??????? |
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| Pingrs |
Mike et al,
Can I backtrack here.
I don’t have a problem with finding the derated POWER. I’m querying how it should be translated into graphical form, to provide the protection locus envelope.
If derated power/rated power = k, then I can draw two graphs which demonstrate that power i.e. P=kVce*Ic, or P = Vce*kIc. These are shown on my linear graph attached.
So, which is the one that should be used, and why. Some suggest the latter; Bensen used the former, from which I took mine.
Note that the worst case scenario is when Vce is derated. The curve is depressed to a greater extent at the critical Vcc< Vce<2*Vcc region. So, in the absence of definitive evidence, might it not be prudent to use that?
On another note, presumably R1+R2a (Mike’s) or R68? (Leach doesn’t show this) is used as the transient protection resistor value for the time constant?
Regards,
Brian. |
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| Pingrs |
Attachment didn't go. Try again
Brian. |
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| AndrewT |
Hi,
if you de-rate Power and divide by a fixed Vce value, you obtain the derated Ic =k*Ic.
At 10Vce the max Ic is 15A at 10.1Vce the max is ~13A (for elevated Tc).
The anomally is eliminated if you also derate the max Ic from 15A down to the lower value k*Icmax. |
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| john_ellis |
Brian
Agree with Andrew T.
From what I read in the data sheets, the second breakdown locus holds virtually constant, but the temperature derating in the left hand (low Vce) side of the graph alters (moving downward with increasing temp). I believe this is because the second breakdown effects are driven by a high temperature, and are abnormally high. Chip temperature is normally lower, but at high temperatures on the chip, the power derating may be lower than Isb derating.
So using kIc for the derated power does this.
cheers
John |
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| janneman |
I agree with Andrew for another eason: I think SB is driven by high Vce and NOT by high temp (it is in the end but only because SB leads to local hotspots). So, actual die temp doesn't influence SB so much.
Jan Didden |
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| mikeks |
| quote: | Originally posted by Pingrs
I don’t have a problem with finding the derated POWER. I’m querying how it should be translated into graphical form, to provide the protection locus envelope. |
Elementary my dear Watson:
Take this example.
The maximum permissible dissipation, assuming your heat sink maintains a transistor case temperature of 70 deg. C, is 128W.
Merely divide the later by Ic (or Vce) on your graph and obtain the corresponding Vce (or Ic); repeat several times.
The resulting hyperbola drawn through the points thus calculated is your new derated power limit. |
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| mikeks |
| quote: | Originally posted by john_ellis
.......the second breakdown locus holds virtually constant..... |
Depends on the device: refer to figure 2B here. |
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| john_ellis |
Jan
| quote: | | I think SB is driven by high Vce and NOT by high temp (it is in the end but only because SB leads to local hotspots) |
I agree that SB is initiated by Vce but it is relatively high temperatures which causes the run-away. Damaging the silicon requires the hotspot to reach ~1000C or more. This is what I meant by "driven by high temperature"- that is if damage occurs.
John |
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| Pingrs |
Andrew, John, Jan, Mike,
Up with me you have put, with patience. I thank you.
Bye for now
Brian.
:att'n:
:) |
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| janneman |
| quote: | Originally posted by john_ellis
Jan
I agree that SB is initiated by Vce but it is relatively high temperatures which causes the run-away. Damaging the silicon requires the hotspot to reach ~1000C or more. This is what I meant by "driven by high temperature"- that is if damage occurs.
John |
Hi John,
Agree fully. But I still have a question that is relevant to what I am trying to do.
My protection system gets two pieces of information: one is the instanteneous Ic, the other is the instantaneous Vce. Now, if the temp is increasing, I must derate the Pc/Ic meaning start the limiting at lower Ic. But should I then also start limiting at lower Vce, or can I leave that as is? Because, as we seem to agree, the onset of SB doesn't start earlier with higher temp. And as long as SB is not initiated, the higher temp doesn't matter - for SB. That's how I understood it, at least.
Jan Didden |
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| janneman |
| quote: | Originally posted by Pingrs
Andrew, John, Jan, Mike,
Up with me you have put, with patience. I thank you.
Bye for now
Brian.
:att'n:
:) |
You were asking very relevant questions. I at least learned. Thank you!
Jan Didden |
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| AndrewT |
| quote: | Originally posted by janneman
My protection system gets two pieces of information: one is the instanteneous Ic, the other is the instantaneous Vce. Now, if the temp is increasing, I must derate the Pc/Ic meaning start the limiting at lower Ic. But should I then also start limiting at lower Vce, or can I leave that as is? Because, as we seem to agree, the onset of SB doesn't start earlier with higher temp. And as long as SB is not initiated, the higher temp doesn't matter - for SB. |
Hi,
the trigger transistor obtains it's base current from the I sensor AND from the V sensor. It effectively adds these two sensor currents and this raises the base voltage towards the trigger voltage. (I guess it's a soft trigger as it starts to conduct).
Assume for a moment that Ic has stayed constant and that Vce is moving up as the waveform progresses. The sum of those two sensor currents will trigger as the Vce sensor supplies sufficient extra current for the protection transistor to start conducting.
If the output transistors have become hotter than the cold set up then you rightly want an earlier trigger voltage i.e. at a lower Vce at the fixed Ic we assumed.
This could be approximated by your heatsink coupled protection transistor (this was discussed some months ago and although probably not exactly what is required at least moves the trigger point in the right direction) Certainly my modified Bensen sheet shows quite clearly the lower protection locus as the trigger voltage is re-set to a lower value.
It matters little whether the Ic moves while Vce is fixed or if both sensor currents are changing. The protection transistor is still instananeously summing the two currents.
The adding of the two sensor currents is possibly the equivalent to mutiplying V * I since the result follows a power law for a small portion of the protection locus. It is certainly not multiplication for the highest currents (low Vce) nor for the lowest currents (high Vce) but this error in the shape of the curve is fortuitously just what we need to mimic the DC SOA at the asymtotes.
To me it seems, the much more important parameter that needs changing is short term transient trigger voltages (the RC delay) to prevent early triggering on short peaks that the output stages can easily pass and survive. |
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| janneman |
| quote: | Originally posted by AndrewT
[snip]If the output transistors have become hotter than the cold set up then you rightly want an earlier trigger voltage i.e. at a lower Vce at the fixed Ic we assumed.[snip] |
That I question! Why should we trigger earlier on a specific Vce because the transistor is hotter? I want an earlier trigger with Ic, but not Vce. IOW, the network sensing Vce and providing a related input to the protection transistor doesn't need to be temp sensitive. The network that samples Ic and provides an input does need to be temp sensitive.
(Forget for the moment that many practical implementations cannot separate the two effects, we're talking principles here).
Jan Didden |
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| john_ellis |
Hi Jan
I think what we agree on is that for higher temperatures, the protection circuit needs to trigger at a lower Ic. This automatically reduces the power allowed in the transistor. The Vce needs to be left alone, as it were, because this does not change!
In a classical protection circuit of the type Andrew suggests the base sees a signal from Vce and another from Ie which is being summed and the two form a load line which needs to be large enough to avoid being triggered by pulses/reactive load lines etc.
Maybe a simple temperature compensation would be to put the protection transistor onto the same heatsink as the output devices. As this warms, the protection load line reduces. I haven't thought this fully out as to whether the temperature compensation is sufficient. But as we also agree on the ISB limit not being as critical as the overall dissipation at higher temperatures, maybe this will be enough.
It is also quite permissible to allow the pulse power rating to be used, increasing the power output capability on a temporary basis, and a delayed turn-on in the protection can do this. But then some additional protection is needed to prevent overloads during the delay time... so I'm sure that there is scope for a comprehensive protection arrangement to be designed.
cheers
John |
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| AndrewT |
Hi John & Jan,
we are on the same wavelength.| quote: | | Assume for a moment |
| quote: | | It matters little whether the Ic moves while Vce is fixed or if both sensor currents are changing. The protection transistor is still instantaneously summing the two currents. |
| quote: | | summed and the two form a load line |
and once these are summed then| quote: | | I want an earlier trigger with Ic |
is achieved.| quote: | | possibly the equivalent to mutiplying V * I since the result follows a power law for a small portion of the protection locus |
confirms we are de-rating power at least on part of the protection locus.
There was an extended discussion on mounting the protection transistor on the sink and whether it came close to compensating correctly or at all.
The consensus was that the temperature compensation was not accurate but that it undercompensated. It was also agreed that linking sink to prot Q did move the protection locus in the correct direction for operation at elevated temperatures (anything above 25degC).
RC filtering is pretty effective in providing a delay that adjusts itself inversely with signal level. That inverse property is exactly what the semiconductors need.
Significant attenuation on very short lived spikes and little attenuation of near DC signals. Similarly small delay on very high signal levels and higher delay on signals that just exceed the trigger levels. I think the simple RC connected protection transistor can do the job we need, particularly if I knew how to design the RC part of it. I wish simulators were within my intellectual grasp. |
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| AndrewT |
Hi Mikeks,
wiki upload..... file size 5GB.
Does thatmean you want us to download a 5GB file?
or was the download hanging saying "done" for another reason? |
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| Netlist |
I've split the pdf.
Here is part one: |
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| janneman |
| quote: | Originally posted by AndrewT
Hi John & Jan,
we are on the same wavelength. and once these are summed then is achieved. confirms we are de-rating power at least on part of the protection locus.
There was an extended discussion on mounting the protection transistor on the sink and whether it came close to compensating correctly or at all.
The consensus was that the temperature compensation was not accurate but that it undercompensated. It was also agreed that linking sink to prot Q did move the protection locus in the correct direction for operation at elevated temperatures (anything above 25degC).
RC filtering is pretty effective in providing a delay that adjusts itself inversely with signal level. That inverse property is exactly what the semiconductors need.
Significant attenuation on very short lived spikes and little attenuation of near DC signals. Similarly small delay on very high signal levels and higher delay on signals that just exceed the trigger levels. I think the simple RC connected protection transistor can do the job we need, particularly if I knew how to design the RC part of it. I wish simulators were within my intellectual grasp. |
Andrew,
You're right of course, I was just looking at it from a principle way, without concern of the way the two information pieces are summed in the "classical" way (but where's the fun in the "classical way" ehh?).
I think we beat this particular horse to death sufficiently.
Jan Didden |
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| janneman |
| quote: | Originally posted by Netlist
Third part: |
Hugo,
Thanks for this. It was exactly what I was looking for a few weeks ago and in the meantime, with a great deal of headscratching, found out myself.
What kept you so long? :D
Jan Didden |
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| Netlist |
That's Mike's PDF. I have hardly an idea what I split. :)
/Hugo |
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| janneman |
| quote: | Originally posted by Netlist
That's Mike's PDF. I have hardly an idea what I split. :)
/Hugo |
Yeah I found that in the mean time.
Thanks anyway.
Jan |
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| mikeks |
While fascinating, this approach is of dubious utility in practice as one is very unlikely to encounter a loudspeaker system capable of generating a 90degree impedance phase shift; this is attested to by Stereophile's impedance response graphs of hundreds of loudspeakers.
The loading presented by a full range loudspeaker system is unlikely to be worse than 4ohms at 60degrees phase shift. |
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| mikeks |
| quote: | Originally posted by janneman
I do something similar but with a different circuit. I never felt quite comfortable with Mike's circuit, too many variables to juggle! |
I disagree; 'would like to see your circuit nevertheless. |
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| Pingrs |
"'would like to see your circuit nevertheless."
Jan,
Me too, and this sounded interesting (similar to mine, which has one breakpoint?):
"the spreadsheet to automagically calculate the protection circuit component values interactively by setting the breakpoints on the graph to follow any required shape with two breakpoints".
Regards,
Brian. |
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