| analogspiceman |
Hi all, :wave:
I am planning to compare the UcD method of class d control against the leap frog method of switching amplifier design using LTspice, an extremely easy-to-use, full-featured, very high performance circuit simulator available for free from Linear Technology (no personal affiliation).
I hope to examine such characteristics as frequency response, output impedance / load independence, distortion, etc. and intend to do this both at the control level (where the diff-amp-to-mosfet-output is treated as an ideal power comparator with delay - of about 200ns) and at the detailed circuit level. As part of this process I will show how to add an active mosfet dv/dt limiter, show an easy way to add output current sensing (necessary for leap frog), and explore some possibilities of improving the UcD's large signal high frequency transient response. (Haven't some people claimed to have noted some small coloration in this regard?)
However, before starting, I would like to set a baseline for the UcD design parameters. Since I neither own nor have access to one, I will need a little help in confirming certain circuit values. From reading this forum I have gleaned the following information about the UcD 180 (which may or may not be correct): Output inductor = 30uH; Output capacitor = 0.68uF film; Voltage feedback lead network = 560pF in series with 910 ohms all in parallel with 4.7k - these in turn feed a 220 ohm resistor to ground at the amp's minus input (probably there is a small capacitor in parallel here as well); Power supplies are plus and minus 45 volts; The mosfet gate resistors are about 33 ohms (maybe smaller?) and the pnp pull down resistors are about 68 ohms; the level shifter npn B-E resistor is 56 ohms and pnp B-E resistors are 110 ohms (?); The differential input's current source is about 10ma.
Any help kindly appreciated. -- analog(spiceman) :angel: |
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| classd4sure |
Hi 'Spiceman,
I'm interested in learning how to best optimize the control loop of the UCD circuit. As well as how to ensure the phase shift transition is sufficiently steep in order to minimize frequency modulation. This is something I haven't been able to do, as I have never done average modeling.
I now have several transient simulations which work very good, and am willing to post one if you're interested in seeing. It's done with orcad but it could provide you with some inspiration?
Since we're not interested in cloning anything but more for educational purposes, and my circuit doesn't qualify as a proper baseline, I recommend simply using the circuit as shown on the patent as the baseline, for which all values are correct, at least for the filter and feedback network, though my circuit would more closely mimic a more complete implementation, which you may be interested in seeing as well.
I'd also like to add that transient sim with Pspice doesn't fair very well for the particular values/circuit shown in the patent, not very surprising or meaningful I know. This would no doubt be alot different with an average model.
The LC filter values you mentioned are what is used in the UCD180 (slightly higher Q than a butterworth), but I believe none of the others are. For instance the feedback and gain resistors are 8.2K and 1.8K, which means the 560p and 910R likely aren't the same as well.
As far as the other values, that will all depends on component selection. I think 10mA for the LTP may give excessive dissipation and reduced input sensitivity. I'm using more in the area of 3mA, or 5mA for a full bridge. So the drivers get ~1.5mA, mosfets ~150mA drive current, which isn't alot but with the state of the art mosfets required anyway it seems to do the trick.
For the sake of experimentation, I've just tried values similar to those you've mentioned. 10mA source, 100ohm Rb for ~9.5mA base (it's a requirement to have it closely match "Is" to lower DC offset), 120R for the PNP turn on, and 68 for the PNP turn off, with 2R as the "on" resistor.
With 110R for turn on the driver was loaded down and providing inadequate drive, and extra 10R was enough to fix that.
In transient it showed respectable shoot through (but worse), less input sensitivity, doubled average power dissipation to about 1.2W, and a 5X increase in THD.
The values I prefer, 3mA for Is, 250R for Rb, 460R for the PNP turn on driver, 320R for the PNP turn off, and I kept the same 2Ohm Ron for both tests.
That gets me better sensitivity at the diff pair, ~0.6W dissipation, almost no current shoot through at all (you'd have to really look for it), and...... and..... OH lookkk..... spice is lying to me again. It usually shows ~.012% THD for these same values, but now it is showing TOTAL HARMONIC DISTORTION = 8.505807E-03 PERCENT, hey, I'll take it.
BTW that's 1V input at 20Khz using the fully differential instrumentation amp like setup.
Which brings me to another issue, a few people have commented on the sound at high frequency, but it is believed that they aren't used to hearing a flat frequency response and so it strikes them as odd. I personally don't believe it is a problem.
Anyway if you'd like to see my schematic I don't mind providing all criticism is of course of the constructive variety (I'm not a professional). I find this topic extremely interesting and look forward to learning all I can from it, hopefully it won't all be done in a manner which would require either a professional with 20 years experience to understand or a team at NASA.
Incidently, I'm using a 15uH inductor and a 1.5uF cap, the patent values were for a 6ohm load, which doesn't interest me.
Best Regards,
Chris |
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| analogspiceman |
Thanks for the help with the values. I checked some more back threads and found the part number for the output mosfets and the post where Bruno mentioned the values for the feedback resistors. I am attaching an LTspice schematic showing my baseline UcD180 core design guesstimate. With no input it oscillates at about 440kHz with 10ns rise and fall times.
Before commenting on loop design, averaged equivalent circuits, etc., I'd like to get the baseline schematic as correct as possible. Component value checks from UcD180 owners would be most appreciated. :)
Once the baseline is finalized I will post its LTspice schematic file and those with the other modifications (dv/dt control, transient damping, leap frog control). |
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| IVX |
Hi analogspiceman,
it's a very interesting idea to compare concepts!
However, I'm not sure about UcD180-400 users, because this amp contain two PCB's: mother PCB 65x65mm, and small modulator PCB, which plugged in the mother.The modulator PCB is coated by untransparent compound. So real value of the res&caps seems secret nowadays even..
Edited: Actually, i've feeling that this product already quite protected by the reasonable cost. |
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| phase_accurate |
| quote: | | Actually, i've feeling that this product already quite protected by the reasonable cost. |
That is admittedly true. But the topic of this thread was the comparison of two feedback methods for class-d amps.
For reasons of simplicity I personally prefer topologies that take feedback from a single point.
Regards
Charles |
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| classd4sure |
Hi,
I agree with all of the above. However I'm still interested in seeing this continue, I might maybe somehow learn something, and it's a nice change from the "how do I plug it in" threads :)
So, there's really no need to mimick the actual animal as closely as possible, simply establish your own baseline and all comparisons will be equally valide. It seems like you've got yourself a baseline right there. Nicely done.
Regards
Chris |
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| IVX |
Chris,
i think, that everyone here awaiting this comparison also, for me would be interesting to build real LF amp(BTW,i'm ready to try) for the sound comparison even. I've just a little doubt about enough equality of the http://www.diyaudio.com/forums/atta...tamp=1110300548 and real product schematics. |
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| analogspiceman |
| quote: | Originally posted by IVX
Chris,
i think, that everyone here awaiting this comparison also, for me would be interesting to build real LF amp(BTW,i'm ready to try) for the sound comparison even. I've just a little doubt about enough equality of the http://www.diyaudio.com/forums/atta...tamp=1110300548 and real product schematics. |
Hi Ivan and All,
I now have the UcD / LF comparison working, both with ac and transient analyses, the later both with a detailed and an idealized circuit. I don't have time to post the results now (perhaps some tonight, then more on Saturday). Just a little progress report for the forum. :) |
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| analogspiceman |
Just to get things started, here is the schematic of a UcD180 power circuit modified to implement leapfrog control (short circuit protection is an inherent, seamless side benefit of leapfrog control). I've also included a very simple, but effective mosfet dv/dt control circuit.
As near as I can tell, LF may be tuned to achieve equal performance to the normal UcD control method, or (unlike UcD) it can be tuned to damp out L-C filter ringing during transient overdrive conditions (where the UcD's feedback loop is momentarily disconnected).
More to follow.... |
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| IVX |
Hi,
1)In my experiments UcD show decent clipping behavior.
2)Why we need the effective mosfet dv/dt control circuit? |
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| analogspiceman |
| quote: | Originally posted by IVX
Hi,
In my experiments UcD show decent clipping behavior.
Why we need the effective mosfet dv/dt control circuit? |
Need? That depends. Are the mosfets failing mysteriously? Does the output stage produce excessive EMI?
C5/R14 and C6/R18 limit mosfet turn-on dv/dt by stealing just enough drive current. This has little or no influence on clipping behavior.
Regards -- analog(spiceman) |
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| analogspiceman |
| Here is a simulation of the LeapFrog controlled UcD power circuit for a 10kHz square wave at two levels into a 6 ohm load. Current in the upper trace compares actual inductor current to its sensed feedback signal. |
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| analogspiceman |
| Here is a simulation of the LeapFrog controlled UcD power circuit for a 10kHz square wave into an open circuit, a 6 ohm load, and a short circuit. Inductor current is shown in the upper trace. |
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| Jaka Racman |
Hi,
thank you very much for your effort. I am eagerly awaiting continuation. Would you care to show and comment results (not immediately but sometime along your analysis) to what I think is the most acid test for classD: square wave output of unloaded amplifier. I think that LF must excell in that region too.
Best regards,
Jaka Racman |
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| analogspiceman |
| quote: | Originally posted by analogspiceman
Here is a simulation of the LeapFrog controlled UcD power circuit for a 10kHz square wave into an open circuit, a 6 ohm load, and a short circuit. Inductor current is shown in the upper trace. |
For comparison, here is a simulation of the unmodified UcD power circuit for a 10kHz square wave into an open circuit, a 6 ohm load, and a short circuit. Inductor current is shown in the upper trace.
Please note that this result is only based on my guess at the UcD180 schematic as shown earlier in this thread. |
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| Jaka Racman |
Hi,
you simulate faster than I type.
Thanks,
Jaka Racman |
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| analogspiceman |
| quote: | Originally posted by Jaka Racman
Hi, thank you very much for your effort. I am eagerly awaiting continuation. Would you care to show and comment results (not immediately but sometime along your analysis) to what I think is the most acid test for classD: square wave output of unloaded amplifier. I think that LF must excel in that region too.
Best regards,
Jaka Racman |
Okay, Jaka, just for you, in order to maximize the cleanliness of the no load response, I've turned down the voltage loop gain a notch or so (I also cut back on the limit level for current a tad, too).
| quote: | Originally posted by Jaka Racman
Hi,
you simulate faster than I type.
Thanks,
Jaka Racman |
Not really. I'm only using an old 266MHz pentium II (I like it because the kids don't want to use it). :)
Regards -- analog(spiceman) |
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| IVX |
| i just now try simulating too, and i've noted worse THD(.2% vs .02% for UcD at the same comparator based) at the low levels .5-1W(fall I-feedback resolution?). However, for mid power up to around clipping THD almost constant (.1%). Clipping itself is very smooth. THD for 1khz vs 10khz almost equal too (AD826 model used). |
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| analogspiceman |
| quote: | Originally posted by IVX
i just now try simulating too, and i've noted worse THD(.2% vs .02% for UcD at the same comparator based) at the low levels .5-1W (fall I-feedback resolution?). However, for mid power up to around clipping THD almost constant (.1%). Clipping itself is very smooth. THD for 1khz vs 10khz almost equal too (AD826 model used). |
Hi Ivan,
Thanks for the report. What simulator are you using? (I use LTspice - the best, IMO, and it's free, too!)
I was planning to zip together my simulation files and post them at some point. I have detailed, componnent level models (I've posted gifs of the schematics for those) and idealized models that run faster and are probably better for comparing the basic concepts rather than the strengths of the particular implimentations. The idealized models can also be set up to do ac analyses (closed loop frequency response, loop gain, output impedance) in addition to the usual switching transient type.
Leapfrog depends on sensed current, the quality of which affects the performance (although the outer voltage loop corrects for current sensing anomolies that are within the reach of the voltage loop's lessor loopgain). The cheap and easy current sensing scheme I've shown seems to have lower distortion with higher dc bias. Note that I haven't investigated its sensitivity to component variations or power supply noise, so whether or not it is the best choice remains to be seen.
Also, note that the voltage loop gain of leapfrog can be increased to where it matches UcD (but then the large signal transient response rings just as much). When these gains are the same, THD may be the same (haven't checked yet). Much to do.
Regards -- analogspiceman |
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| subwo1 |
Hi analogspiceman, thanks for explaining the leapfrog method well. For example, I was unaware of its usefulness in certain applications. That current sensing circuit is indeed interesting.
I think LTspice is excellent too. :) It has cool features like the ability to mirror circuit elements ranging from a single component to an entire circuit. Plus, I find its intuitive user interface very helpful. |
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| IVX |
Hi analogspiceman,
this is Micro-cap 7 -isn't best, but very useful for me. |
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| analogspiceman |
| quote: | Originally posted by IVX
Hi analogspiceman,
this is Micro-cap 7 -isn't best, but very useful for me. |
I recommend that you try LTspice. It's free and in my opinion is faster, more powerful than Pspice (don't know about MicroCap) and easier to use. The link to the download is at the start of this thread (it is only a few megabytes).
By the way, it seems that THD as reported by the .four command is not reliable with these class D simulations. The numbers vary too much with the integration method, tolerance setting, maximum step size, total interval, etc. I can get either of the LeapFrog or the UcD design to come out with better THD by playing around with the simulator settings. Worse, there is no simulator control set up that consistently yields the lowest THD. The numerical noise is just too high to measure low THD reliably. That must wait for the actual hardware, it seems.
Regards -- analogspiceman |
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| subwo1 |
| quote: | Originally posted by analogspiceman
By the way, it seems that THD as reported by the .four command is not reliable with these class D simulations. |
Thanks for mentioning it. I was recently wondering about trying the Fourier analysis. I am not good with math anyway.
Best Regards |
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| IVX |
Do you plan to build LF amp?
My modest DIY experience, in the real implementation of the class D amps, doesn't show even 50% THD matching vs simulations (MC7, P-spice), and i've feeling that it isn't only from the bad quality of the implementation/equipments etc. :-) |
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| lumanauw |
| Pardon me, D5 and D7 are drawn like Zeners, but in the datasheet BAT54 are schottky. What is this dioda, what is the purpose in this CCT? |
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| analogspiceman |
| quote: | Originally posted by IVX
Do you plan to build LF amp?
My modest DIY experience, in the real implementation of the class D amps, doesn't show even 50% THD matching vs simulations (MC7, P-spice), and i've feeling that it isn't only from the bad quality of the implementation/equipments etc. :-) |
I have no immediate plans to build an either of these designs although it might be fun to do a layout - and then, who knows?
Class D THD can be sensitive to layout imperfections via self EMI - bad layout may increase THD. Simulated Class D THD can be sensitive to computational imperfections - bad time step quantization may increase THD. So, in your experiences, which way did it go?
By the way, I am attaching the LTspice files for the two schematics shown earlier. (Remember, the first post in this thread has a link to where one may obtain a free copy of LTspice.)
Regards -- analogspiceman |
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| subwo1 |
| quote: | Originally posted by analogspiceman
By the way, I am attaching the LTspice files for the two schematics shown earlier. (Remember, the first post in this thread has a link to where one may obtain a free copy of LTspice.)
Regards -- analogspiceman |
You've given some great ideas.:treasure: :yes: :up: :D |
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| IVX |
| quote: | Originally posted by analogspiceman
So, in your experiences, which way did it go?
Regards -- analogspiceman |
I don't know..i'm just a DIYer.
!!!Seems your amp will be well work without input+feedbacks_summing opamp. I just now check this out. Sure that opampless circuit much more preferable.
Maybe replacing ifb inverting opamp is possible also, with symmetrical mirrors instead? And all this come to the fully differential view (i'm saw it somewhere without ifb though..;-)? |
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| subwo1 |
| Hi analogspiceman, I played with the UcD circuit to see how I could adjust its performance. I was wondering if you'd like to see what I came up with. I don't think it is as optimized as I could get it, but I thought I'd post the LTspice circuit how I got it after a while. I was wondering how it compares to the leapfrog method, in your opinion. I added rc passive damping to the output and adjusted the feedback. |
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| subwo1 |
| quote: | Originally posted by lumanauw
Pardon me, D5 and D7 are drawn like Zeners, but in the datasheet BAT54 are schottky. What is this dioda, what is the purpose in this CCT? |
Hi lumanauw, those diodes are schottky, and their purpose is to prevent the driver input transistors from saturating. They speed the circuit response and makes its operation smoother and more linear. They are called baker clamps in this application. |
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| Jaka Racman |
Hi Subwo1,
I have not simulated yet, but I have a gut feeling that your added 10R resistor will have a rather high power dissipation.
Hi Analogspiceman,
thank you for posting simulation files. I agree with Subwo1, much food for thought.
I would also be interested in simulations using averaged models. So far I have modified some Ispice buck and boost stage averaged models to classD totem pole stage averaged model. But my model is only useful for constant frequency PWM. Bruno proposed method for devising UcD averaged model, but since it has been some years back when I played with Ispice models, I would have to relearn everything back.
Best regards,
Jaka Racman |
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| subwo1 |
Hi Jaka Racman,
Thanks for the viewpoint. I will be very interested to learn what you find out. Best Regards. |
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| Jaka Racman |
Hi Subwo1,
quite simply, 470nF at 20kHz has 16.94Ohm impedance. So it is a kind like Zobel in IcePower modules. At fully driven output (44Vpeak) at 20kHz you have 25W dissipation. Like it was said in IcePower thread, it can be OK for music, but not for testing.
Best regards,
Jaka Racman |
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| subwo1 |
Hi Jaka Racman,
I was wondering if you remembered that the 10R resistor in series with the capacitor raises the impedance to 27 ohms. Then, I come up with 11 watts. It is definitely not useful for high power applications. So the advantage of leapfrog for efficiency seems good. Thanks for taking a look at it. Best Regards. |
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| analogspiceman |
| quote: | Originally posted by Jaka Racman
I would also be interested in simulations using averaged models. So far I have modified some Ispice buck and boost stage averaged models to classD totem pole stage averaged model. But my model is only useful for constant frequency PWM. Bruno proposed method for devising UcD averaged model, but since it has been some years back when I played with Ispice models, I would have to relearn everything back. |
Hi Jaka,
:angel: Forgive me for retreading ground well known to you (I think it is always worth a revisit).
Bruno's method seems sound in principle although he may have gotten some of the details wrong. The same method is used for analyzing digital gate driven low level, phase shift and crystal oscillators. There, as with UcD, there is a gross over abundance of gain until the output stage is limited by saturation. If everything is symmetrical then the output will become a square wave. Its fundamental Fourier component is in phase with an rms value of 0.9 times the dc supply (for plus and minus supplies). Follow the loop around through the RC phase shift network (or crystal, or UcD's LC filter) back to the input of the gate (or power stage) and sine wave that shows up is always precisely what is required for unity loop gain at the oscillation frequency. Saturation makes it self adjusting.
Ah, but stable oscillation requires more than just unity loop gain. It also require precisely 360 degrees of phase shift around the loop, and that only happens at one frequency determined by the feedback network and the gate or power stage delay. The UcD starts out with 180 degrees of phase shift because due to feeding everything back into the inverting input. Add the nearly 180 degrees from the LC filter and, whoops, we're in trouble because we are very close (but not quite at) the conditions for oscillation. Not good - lots of ringing and who knows what random extra bit of phase shift will put it over the edge and where it will oscillate.
Bruno's bit of genius :wiz: was to throw in a lead network (takes away 90 degrees of phase shift) to set the oscillation point at where the lead network runs out of steam. Of course, there still is the problem of only just barely reaching 360 degrees, but by this point, the delay in the power stage adds enough additional phase shift so that zero phase point (same as 360; it wraps! :hypno2: ) is crossed with a well defined slope. This makes for a reliable and repeatable oscillation frequency. (Not enough delay can be remedied by adding a small RC section into the feedback path, most likely at the input to the power stage.)
So, loop gain at the oscillation frequency is just the transfer function of the LC output filter plus feedback network, but what is it in the audio band? Just as with a typical sawtooth PWM modulator, one need only look at the slope of the wave form appearing at the input (a small sine wave) to the comparator / power stage and calculate how much change it would take along that projected slope to go from zero output to full output.
It turns out that it would take a change of 1/4 the period of oscillation to saturate the power stage along this slope. So if we know the frequency of oscillation and the size of the sine wave appearing at the power stage's input, we can calculate its slope at zero crossing (the point of switching). From this and the voltage of the power supplies and the gain factor of 1/4 the switching period, we can calculate the small signal gain within the audio band.
This is essentially Bruno's method, but I think he calculated a typical UcD design audio loop gain of over 400. When I work through the numbers for the UcD schematic I posted, I get a much lower number, somewhere just under 60. The devil's in the details, eh? :devily:
Regards -- analogspiceman |
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| Bruno Putzeys |
Howdy,
Good analysis.
| quote: | Originally posted by analogspiceman
(...)
although he may have gotten some of the details wrong.
(...)
but I think he calculated a typical UcD design audio loop gain of over 400. When I work through the numbers for the UcD schematic I posted, I get a much lower number, somewhere just under 60. The devil's in the details, eh? :devily:
|
There must have been a slight miscommunication somewhere. I was quite aware that loop gain is not 400. Numbers like that are not the loop gain, but the linearized gain of the comp+power stage alone. The loop gain is that multiplied by the "gain" of the filter and the feedback network. The standard 2nd order circuit from the patent (2nd order = only the output filter) typically clocks in at 25dB loop gain, the 3rd order circuit (1 extra passive pole) such as that used in the hypex modules has about 33dB loop gain (still less than 60). Not that I would mind 400 :)
Cheers,
Bruno
PS: More precise analysis shows that in this sort of phase-controlled circuit, loop gain at the switching frequency always ends at -6dB. The rest of the curve follows. |
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| Jaka Racman |
Hi,
Subwo1, sorry I goofed but I did not have my old HP71B calculator at hand.
Analogspiceman, I was hoping to see more comments from other members. Right now, LF is very appealing to me since it can also work with fixed frequency control. Recently I discovered US patent 4479175 which has now expired. It renewed my interest in ampliverters. Since they work constant frequency, UcD control is out of the question.
I have three questions:
-do you think that for fixed frquency operation, average current mode loop could be used with equally good results as it is possible with hysteretic current mode control?
- what do you think about curent sense method that integrates output inductor voltage instead of using direct sensing? I know that inductor saturation could be problematic, but what else ?
-do you think that LF method could be improved by summing output of voltage error amplifier with differentiated input signal (capacitor current feedforward like in Mueta)
Best regards,
Jaka Racman |
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| subwo1 |
Hi Jaka Racman, it's quite all right. I appreciate that you took a look at it. Thanks, regards.:)
PS. There is a calculator in Windows Accessories. Under the view tab, there is an option for scientific notation. |
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| analogspiceman |
| quote: | Originally posted by Bruno Putzeys
There must have been a slight miscommunication somewhere. I was quite aware that loop gain is not 400. Numbers like that are not the loop gain, but the linearized gain of the comp+power stage alone. The loop gain is that multiplied by the "gain" of the filter and the feedback network. The standard 2nd order circuit from the patent (2nd order = only the output filter) typically clocks in at 25dB loop gain, the 3rd order circuit (1 extra passive pole) such as that used in the hypex modules has about 33dB loop gain (still less than 60). Not that I would mind 400 :)
PS: More precise analysis shows that in this sort of phase-controlled circuit, loop gain at the switching frequency always ends at -6dB. The rest of the curve follows. |
Hi Bruno,
Yes, I probably misread something somewhere, as I am getting my information about the UcD180 design all second hand from back threads, other posters and guesses. By the way, I went through the math regarding the two loop gains, and you are quite right, taken against each other everything drops out except a factor of two (at least at 50 percent duty cycle and as long as the signal appearing at the UcD input is more or less a sine wave).
Delays in the power stage (or right half plane zeros) eat your phase margin without giving back more loop gain, so a responsive power stage with a 3rd order type circuit would be best. Because this is a phase controlled, gain saturating oscillator, it might be difficult to get an even higher order, higher gain, marginally stable system to start up reliably oscillating at the right frequency. Oh, well.
Depending on what's driving it and how the inputs are configured, the UcD might need something (couple of diodes) to keep the input BE junction from Zenering. Also, with mosfets that need it (or to limit EMI), you might find my simple drain-to-gate RC dv/dt limiter useful, since the UcD is already set up perfectly with asymmetrical drive (its got the pull-down PNP that the RC needs so it only affects turn on dv/dt).
I'm very impressed with the UcD's elegant simplicity most of all. I like it (please tell Jan-Peter that if you get too busy with other projects, I'm ready to step in). :angel:
| quote: | Originally posted by Jaka Racman
Analogspiceman, I was hoping to see more comments from other members. Right now, LF is very appealing to me since it can also work with fixed frequency control. Recently I discovered US patent 4479175 which has now expired. It renewed my interest in ampliverters. Since they work constant frequency, UcD control is out of the question.
I have three questions:
-do you think that for fixed frequency operation, average current mode loop could be used with equally good results as it is possible with hysteretic current mode control?
- what do you think about current sense method that integrates output inductor voltage instead of using direct sensing? I know that inductor saturation could be problematic, but what else ?
-do you think that LF method could be improved by summing output of voltage error amplifier with differentiated input signal (capacitor current feedforward like in Mueta) |
Hi Jaka,
A friend of mine actually made a working inverter using that phased carrier concept. It works fine, but can be difficult to snub simply. In the end, he decided it was more costly than traditional approaches.
Three Q's: 1) probably, but comparing theoretical bandwidth (after correcting for hysteresis control's wildly varying frequency) would be very interesting. 2) Risky. Loss of tracking during saturation could be a disaster and thermal resistance shift in the wire would be problematic. 3) ??? Leapfrog already feeds forward the output capacitor's load current. Did you mean something else?
To Subwo1,
Actually you stole a little bit of my thunder. I was going to mention the output damper as a possible addition to the UcD to cure its transient ringing, but Jaka already covered the down side of that. Note that with most loads, it wouldn't be a problem anyway and it might be better just to step around the "problem" by limiting the input signal appropriately (I know, some people don't like such circuits, but it is much easier to do it colorlessly on the low power input than on the high power output). By the way, from the power supply world, the standard recommended Q killing RC damper is 3*C and R = sqrt(L/C).
Regards -- analogspiceman |
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| analogspiceman |
| quote: | Originally posted by analogspiceman
(please tell Jan-Peter that if you get too busy with other projects, I'm ready to step in). :angel: |
I forgot to finish ... step in and design a LeapFrog version. :)
| quote: | | it might be better just to step around the "problem" by limiting the input signal appropriately (I know, some people don't like such circuits, but it is much easier to do it colorlessly on the low power input than on the high power output). |
Forgot to mention ... a clever input limiter can also solve the problem of passing along power supply hum during clipping:
Actively peak track and low pass filter the lowest points of power supply ripple. Further reduce this by a signal proportional to mosfet current (compensates for IR drop). Scaled down just a bit, this then becomes a moving reference for an input limiter that always allows maximum possible output power (with no hum during "clipping"), and without ever having the output stage actually saturate and suffer the ill effects of opening the feedback loop.
Regards -- analogspiceman |
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| subwo1 |
Sorry, analogspiceman, it was not my intention if I even thought it were possible to upstage you. I am considering the simplest but most effective circuit for me in my class D amplifier project, given my design constraints, and I am considering possibilities still. I can most easily both limit input amplitude and frequency, but I am considering throwing in a weaker than standard RC damper for good measure. The formula gives an R value of 6.8 and a C of 2.2uF. That may be one reason why I reduced the capacitor very much from optimal, as the power dissipation in the resistor is already about 10 watts, unless I misread the formula. Thanks, best regards.
| quote: | analogspiceman wrote
Actively peak track and low pass filter the lowest points of power supply ripple. Further reduce this by a signal proportional to mosfet current (compensates for IR drop). Scaled down just a bit, this then becomes a moving reference for an input limiter that always allows maximum possible output power (with no hum during "clipping"), and without ever having the output stage actually saturate and suffer the ill effects of opening the feedback loop.
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This idea sounds a little more thorough than the idea I have simulated which uses two emitter followed voltage dividers from the amplifier power supply to power the input opamp. The values of the outer resistors can be equal to the feedback resistor and the inner resistors slightly more than the gain setting resistor to account for Vbe and opamp output that is less than rail to rail. |
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| subwo1 |
| I wonder if the clipper I tried would track power supply ripple better if filter capacitors were tied from the bases to the power amp supply rails, plus two more from there to ground. It would make a capacitive voltage divider across the resistive one. It might not help, though. |
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| Bruno Putzeys |
Hello analogspiceman.
| quote: | Originally posted by analogspiceman
Hi Bruno,
(at least at 50 percent duty cycle and as long as the signal appearing at the UcD input is more or less a sine wave). |
A-men. Anything that doesn't produce a neat triangle wave at the comparator produces non-linear modulation. That rules out anything except the simplest first-order schemes.:bawling:| quote: | Originally posted by analogspiceman
Delays in the power stage (or right half plane zeros) eat your phase margin without giving back more loop gain, so a responsive power stage with a 3rd order type circuit would be best. |
Indeed, although the peaking produced by the reduced phase margin coincides with the switching frequency, which is why you only see it in the linearised model. Doesn't seem to mean much in practice as the amp is already oscillating at that frequency.:xeye:| quote: | Originally posted by analogspiceman
Depending on what's driving it and how the inputs are configured, the UcD might need something (couple of diodes) to keep the input BE junction from Zenering. |
Not during normal operation. The inputs are only seeing the small oscillation wave form, which is quite a bit less than 5V (a few 10mV or so). However, I've indeed had to add diodes in some cases where even in the shutdown state (tail source off) very large signals like turn-on spikes of the preceding audio circuitry were capable of driving current into the input transistors (through be zenering into the emitter of the other transistor), producing cracking noises in the speaker.| quote: | Originally posted by analogspiceman
Also, with mosfets that need it (or to limit EMI), you might find my simple drain-to-gate RC dv/dt limiter useful, since the UcD is already set up perfectly with asymmetrical drive (its got the pull-down PNP that the RC needs so it only affects turn on dv/dt).
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Pure dv/dt doesn't bother me. Proper layout and correct choice of coil allow very large dv/dt's without causing detectable EMI. It's dI/dt that causes problems.
The crucial point is diode recovery of the outgoing fet. As long as this is still happening, dV/dt is very low so controlling it will have no effect on the speed at which the incoming FET tries to pull the outgoing diode open.
Needless to say I've got another trick that effectively combats this. I use it on all designs 200W and above.| quote: | Originally posted by analogspiceman
(please tell Jan-Peter that if you get too busy with other projects, I'm ready to step in). :angel:
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Noted:)
Cheers,
Bruno |
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| Bruno Putzeys |
| quote: | Originally posted by Jaka Racman
Hi,
Recently I discovered US patent 4479175 which has now expired. It renewed my interest in ampliverters. Since they work constant frequency, UcD control is out of the question.
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Well if you are very patient and have enough power devices to spend on failed amplifier you could just possibly get a UcD based ampliverter working.
Let's say I would not recommend it but just for the heck of it, here's how it could be done (mono amplifiers only):
1. Make a normal UcD loop.
2. Feed the comparator output to a state machine that alternatively switches the primary and secondary sides.
But here's the annoying bit:
3. Add a protection that will override the comparator output if it hasn't switched for the last few microseconds. Otherwise the primary side will blow instantly when the amp is clipped.
I'm not a fan of ampliverters though. The idea is very elegant, but the bilateral switches on the secondary side make things a bit more complicated in reality than in concept.
Cheers,
Bruno |
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| analogspiceman |
Hi all,
The attached gif file is the large signal frequency response analysis output from an LTspice simulation of an UcD180 style class d amplifier.
This simulation uses the recently derived mathematically correct swept sine time domain LTspice B-source in conjunction with a very fast running LTspice A-device to analyze the large signal behavior of a self oscillating class d amplifier under a variety of dc bias levels (approximates high frequencies riding on a large bass signal). The sine source is swept logarithmically from 2.5kHz to 250kHz (25kHz is center screen).
Many weird large signal effects (such as frequency shift, aliasing, pulling and lock) are clearly visible. Note that none of these would be evident in a small signal ac analysis.
When properly set up, the A-device simulates a realistic delay while efficiently allowing maximum step size between switching edges and simultaneously capturing edge timing with great fidelity. This makes successive design iterations possible with almost no waiting.
Time permitting, I will follow up with a post of a similar example based on my leapfrog design method to compare performance under difficult large signal conditions.
I also have a swept sine example of a highly accurate speaker model driven by an amplifier with realistic current and voltage limits modeled. This provocative simulation clearly shows why current limiting (even with perfectly flat and clean clipping) sounds much worse than voltage limiting.
Regards -- analogspiceman |
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| analogspiceman |
Here is the LTspice schematic file (mind the unintended word wrap).
Version 4
SHEET 1 1324 680
WIRE 64 16 64 -64
WIRE 64 128 64 96
WIRE 64 256 64 224
WIRE 64 368 64 336
WIRE 96 -64 64 -64
WIRE 96 224 64 224
WIRE 112 -64 96 -64
WIRE 112 224 96 224
WIRE 224 -64 192 -64
WIRE 224 -64 224 -160
WIRE 240 -160 224 -160
WIRE 256 -64 224 -64
WIRE 256 16 256 -64
WIRE 256 32 256 16
WIRE 256 128 256 96
WIRE 288 -64 256 -64
WIRE 336 -160 320 -160
WIRE 368 16 256 16
WIRE 416 -160 400 -160
WIRE 416 -64 368 -64
WIRE 416 -64 416 -160
WIRE 480 16 432 16
WIRE 544 16 480 16
WIRE 656 16 624 16
WIRE 656 32 656 16
WIRE 656 128 656 96
WIRE 704 16 656 16
WIRE 752 -64 416 -64
WIRE 752 16 704 16
WIRE 752 16 752 -64
WIRE 752 32 752 16
WIRE 752 128 752 112
FLAG 96 -64 i
FLAG 96 224 f
FLAG 64 368 0
FLAG 64 128 0
FLAG 656 128 0
FLAG 752 128 0
FLAG 480 16 x
FLAG 704 16 o
FLAG 256 128 0
SYMBOL bv 64 240 R0
WINDOW 3 -24 168 Left 0
SYMATTR Value V=f1*{f2/f1}**(time/Td)
SYMATTR InstName Bf
SYMBOL bv 64 0 R0
WINDOW 3 -24 168 Left 0
WINDOW 123 -66 214 Left 0
SYMATTR Value V=Vdc+Vp*sin({2*pi*Td/ln(f2/f1)*f1}*{f2/f1}**(time/Td))
SYMATTR InstName Bi
SYMBOL ind 528 32 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName Lo
SYMATTR Value 30µ
SYMATTR SpiceLine Rser=10m Rpar=10k
SYMBOL cap 640 32 R0
SYMATTR InstName Co
SYMATTR Value 680n
SYMBOL res 736 16 R0
SYMATTR InstName Ro
SYMATTR Value 6
SYMBOL res 208 -80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 1k8
SYMBOL res 384 -80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 8k2
SYMBOL res 336 -176 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value 1k0
SYMBOL cap 400 -176 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C1
SYMATTR Value 150p
SYMBOL cap 240 32 R0
SYMATTR InstName C2
SYMATTR Value 33p
SYMBOL Digital\\inv 368 -48 R0
WINDOW 3 0 112 Left 0
WINDOW 123 0 144 Left 0
WINDOW 39 0 176 Left 0
SYMATTR Value tripdt=1n td=200n
SYMATTR Value2 Cout=33n Rout=10m
SYMATTR SpiceLine Vhigh=45 Vlow=-45
SYMATTR InstName A2
TEXT 368 384 Left 0 !.tran 0 {Td} 10u uic
TEXT 248 320 Left 0 !.param Vdc=0 Vp=1 f1=2k5 f2=250k Td=4m
TEXT 472 -224 Left 0 ;To plot frequency on the\nhorizontal axis change\nthe quantity plotted to\n"V(f)*1Hz/1V" and click\n"Logarithmic"
TEXT 704 -32 Center 0 ;35kHz
TEXT 480 -32 Center 0 ;400kHz
TEXT 64 -336 Left 0 ;This circuit demonstrates the use of a swept sine source to test \nthe large signal frequency response of an idealized UcD180 style \nself oscillatiing class D amplifier, as a function of input amplitude,\ninput offset, and output load.
TEXT 256 232 Left 0 ;Sweep Parameters:\nf1 = start freq f2= stop freq Td = sweep duration\nVp = sine peak Vdc = sine offset
TEXT 408 -392 Center 0 ;Swept Sine Analysis - analogspiceman 2005
TEXT 248 352 Left 0 !.step param Vdc list 0 -4 -8
RECTANGLE Normal 672 -368 144 -416 1 |
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| analogspiceman |
| Here is a magnified detail of the output waveform that shows how the oscillation frequency decreases as the output approaches the voltage rail. |
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| classd4sure |
Hi Analogspiceman,
I'll have to take some time later on and have a really good look at that, but just wanted to say, very nice work and thanks for your continued contributions.
Also I like the look of the idealized circuit. No doubt this will have me spending some quality time with LTspice in the near future.
Thanks,
Chris |
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| subwo1 |
| Hi analogspiceman, Indeed, you do a good job of taking the design evaluation process to a higher level. I plan to keep an eye out for further test results comparing leapfrog and UcD.:) |
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| Jaka Racman |
Hi Analogspiceman,
I am sorry I can not answer your question about capacitor current feedforward before I become more profficient in LT spice. I tested it with your schematics and I think that I will finally switch from Intusoft Ispice.
I have another question. On Linear Technology download page there is a program called BodeCAD. From what I can see, it takes LTspice schematic and performs series of transient simulations at different input frequencies thus extracting a Bode plot. Has anyone found this program useful?
Best regards,
Jaka Racman |
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