| Pierre |
Hello all.
This thread is a continuation of "Help with feedback", which I started months ago. It has derived in a interesting question that worths the pain we treat separately.
When testing some of my amplifiers, some of them have failed due to shorted mosfets.
Some of the members point to avalanche phenomena, others to the body diode and excessive dV/dt in unrated devices.
"analogspiceman" proposes that the dV/dt rating in repetitive avalanche mode is not given in all the mosfets, particullarly one of the ones I am using, NTP35N15. However, he said that FQPP46N15 is rated at about 6V/ns, although I can't find this data in the datasheet. However, a pair of them have also failed in the same way. Where did you find that value?
Others propose layout as the main cause: some bouncing can trigger false conduction and hence instant failure of both devices.
Any ideas are welcome.
Thanks.
Pierre |
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| Pierre |
Peter, I can't find info on the mosfet you previously used, the ones you say that worked very bad. What was the problem with them, did they overheat or simply failed in a similar way as mine?
BTW: the mosfets you say you use are TO247, but the photos you posted show TO220 mosfets, what are them?
Best regards |
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| hypnopete |
Pierre,
I had problems with getting a clean gate drive waveform, which resulted in shoot-though etc. They died in a much more spectacular fasion i think, they totally exploded =) .
Yep, very observant of you, they are actually the same mosfet, just in different packages. I opted for the TO-220, as it was a bit smaller, but has a lower peak power disipation rating as expected, in my situation this wasn't a problem.
Regards
Peter. |
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| Pierre |
You had a worse gate waveform with the other mosfet but the same layout? Perhaps that had a bigger Qgate?
Best regards
Pierre |
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| hypnopete |
I don't think they did, it might have been more to do with the Millar charge. I am not sure though, also the output slew rate was quite slow in comparison.
I had a fair bit of trouble keeping the fets cool as well, at frequencies above 30 or so kHz.
Peter |
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| classd4sure |
Hello,
I posted this already but It seems to be the best app note going on this topic, well explained and even providing worked examples to evaluate repetitive avalanche SOA.
Here's the link again:
http://www.semiconductors.philips.c...s/AN10273_1.pdf
I've seen it written by someone who knows alot about how to handle mosfets that the zener drain-gate feedback technique can be troublesome with fets rated at greater than 100V, because the parasitics of the devices in that range lead to oscillation well into the Mhz range, and you wind up with greater than 20V on the gate, causing spurrious turn on.
Ever seen this problem? Of course I'm not sure how relevant that is because of the always advancing technology..
Regards
Chris |
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| Kenshin |
| quote: | Originally posted by analogspiceman
Keep in mind that the reapplied dv/dt limit is never exceeded by too strong of turn off drive (one need only limit the turn on drive). This is best done with a simple dv/dt feedback circuit from drain to the appropriate spot in the gate drive. Simply increasing the gate resistor will serve to limit maximum dv/dt, but it also slows down the already slow enough parts of the transition, thereby unnecessarily increasing switching losses. |
why strong turn off never exceed the dv/dt limit? |
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| analogspiceman |
| quote: | Originally posted by analogspiceman
Keep in mind that the reapplied dv/dt limit is never exceeded by too strong of turn off drive (one need only limit the turn on drive). This is best done with a simple dv/dt feedback circuit from drain to the appropriate spot in the gate drive. Simply increasing the gate resistor will serve to limit maximum dv/dt, but it also slows down the already slow enough parts of the transition, thereby unnecessarily increasing switching losses.
Originally posted by Kenshin
Why would strong turn off never exceed the dv/dt limit? |
One should never say "never", but the mosfet dv/dt problem generally only occurs in a totem pole structure where one of the mosfets' body diodes is first conducting substantial current at the end of dead time and then is immediately (i.e., before it fully recovers) forced, by sudden turn on of the other mosfet, to support too much voltage too quickly, thereby inducing a destructive secondary breakdown in the parasitic bipolar/diode region of the mosfet. Turn off drive speed to the totem pole's "passive" device simply doesn't matter because its voltage is pinned by the current flowing in the reverse direction through its own body diode. |
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| Pierre |
About the power section schematics I posted. Someone asked why I had a shottky diode in parallel with the the low side mosfet and not in the upper side one.
It is there to protect the driver from negative spikes at VS output (referred to COM pin, which is connected to the upper leg of the current sense resistor) If I remember well it is recommended in the IR2110 datasheet or some app.note.
Is it bad placed there?
Have you guys found any other thing worth reviewing or modified? In particular, I think it is ok to connect COM pin to the upper leg of the current sense resistor instead of VSS, as it is there where the source of the LS mosfet is connected, right?
Best regards,
Pierre |
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| dmfraser |
| I'll give you a hint on what the big guys use. They have a PNP transistor between gate and source to discharge the gate source capacitance faser, hence shutting off the FET faster. This makes it run cooler. |
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| Kenshin |
| quote: | Originally posted by analogspiceman
One should never say "never", but the mosfet dv/dt problem generally only occurs in a totem pole structure where one of the mosfets' body diodes is first conducting substantial current at the end of dead time and then is immediately (i.e., before it fully recovers) forced, by sudden turn on of the other mosfet, to support too much voltage too quickly, thereby inducing a destructive secondary breakdown in the parasitic bipolar/diode region of the mosfet. Turn off drive speed to the totem pole's "passive" device simply doesn't matter because its voltage is pinned by the current flowing in the reverse direction through its own body diode. |
when the low side FET is pulling in current to VSS, turn it off suddenly, and the output voltage of switching stage will rise to VDD suddenly due to the output inductor ...does this matter? |
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| phase_accurate |
No it does indeed help switching in some cases. But we have to keep two cases in mind:
1.)
The output current is lower than the idle current (i.e the triangular current flowing in the output coil when an input signal is absent - maybe someone knows a better expression for this ) and then the inductor helps us with switching and even the body diode of the FET that is switching off doesn't fet into conduction. Only the body diode of the FET that is about to turn on gets some foprward voltage and therefor some current flowing. But this is not a problem because this current is taken over by the FET itself and it is therefore harmless.
2.)
The inductor current is exceeding the peak value of the aforementioned "idle current". In this case it can happen that the body diode of the FET that is turned off is getting into conduction, which is causing a reverse-recovery current-spike.
This spike can be minimised (or even completely eliminated in theory) by clever timing of the FET drive-signals.
Regards
Charles |
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| Pierre |
Following the discussion about mosfet selection, I have been surprised that Hypex's Ucd400 amplifiers use the "very advanced power mosfet" (in their own words) FDP42AN15A0.
When I have read its datasheet, I have found that it is the kind of mosfets that look perfect in the datasheet but isn't completely rated for avalanche nor dv/dt. It is rated at 150V, so one could say they have skimped a bit, as the maximum voltage of the module is about +/-65V if I am not wrong.
Yes, it has low gate charge and Rds(on), but its _single pulse_ avalanche energy is 90mJ, compared with the 460mJ rated in the IRFB38N20D, for example.
Surprisingly though, the module seems to be reliable.
So, how can one know "a priori" if one mosfet is going to be suitable and reliable for a Class-D amplifier?
One thing that has been cleared is that one mustn't go to dV/dt higher than the rating for the body diode (that isn't present in a lot of datasheets, on the other hand).
Thanks! |
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| Pierre |
Adding more info on the issue, LCAudio ZAP Pulse 2.0 modules seemed to use IRF640N from IR, right?
They have a higher Rds(on), about 150mohms, but have very low gate charge, etc, _AND_ are avalanche rated and have a 5V/ns dv/dt. They are rated at 200V instead of 150V.
From the reliability point of view, I think they are a good choice, although the Rds is a bit high.
However, perhaps the newer modules have other mosfet, could anyone tell what are they using?
Thanks! |
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| phase_accurate |
| quote: | | They have a higher Rds(on), about 150mohms, but have very low gate charge |
This is still better than the original 640 (without suffix N) that had even 180 milli Ohms. The types with suffix N of the 530, 540 and 640 have all slightly improved Rds(on), trr and dV/dt values compared to the "original" ones.
Regards
Charles
P.S. How is your amp, Pierre ? If you want to try to "fry" some 640s (without suffix N) then I'd have some in my drawer that you can have if you like. |
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| Pierre |
A lot of thanks for the offering, Charles. You are really kind.
They are quite cheap and easy to get here, however, I would like to try another ones with lower Rds(on).
Nevertheless, I suspect that my current mosfets (FQP46N15) are quite good, they have dV/dt=6V/ns, and are avalanche rated (if I am not wrong) with single and repetitive energies of 650 and 21mJ, respectively. They have acceptable gate charge (around 70-100nC) and very low Rds(on). Looking at theif datasheet, they seem very roughed, don't they?
One question that has just come to my mind: When the amp failed, I had two modules running at +/-40V on 4 ohm speakers, and I have 7A fuses in each rail. Is it possible that the failure was caused by _one_ blown fuse that produced a misbehaviour in the circuit, causing a shoot-through current and destroyed both mosfets? Just thinking loud, that shouldn't cause both mosfets to fail and only in one of the modules...
My amp works very well apart from that esporadic and inexplicable failures. :-(
Best regards,
Pierre |
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| subwo1 |
| Pierre, since it sounds like you were driving two speakers independently rather than in parallel or series from a bridge amp, I tend to think that one amp failure should not cause the other to fail. But one possible though unlikely explanation is that if you send the signal through a set of mono amplifiers out of phase to counter power supply pumping, then one amp not operating could cause the other to pump a supply up, leading to the MOSFETs breaking down and passing avalanche current. |
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| Pierre |
No, both amps were operated with independent speakers and with stereo signal, not out of phase.
The supply was +/-45V at idle, and my mosfet were 150V, I haven't experienced problems with pumping so far.
Anyway, I was only thinking loud, I don't think it was due to a failing fuse as one of the amps survived without damage, and I can't find a way in that blowing a fuse can lead to failure of BOTH mosfets. BTW: the one that survived had FQP46N15 mosfets, the other had NTP32N15 from On-Semi.
BUT: the one that failed had previously broken a pair of FQP46N15 in the lab, but as I didn't have more, I put the NTPs. Perhaps the FQPs failed due to an accidental short in the lab... perhaps not! Some more tests are needed!
The thing is: do that mosfets seem rough enough to you?
BTW: The speakers were quite big, a pair of 2x15"+tweeter JBL's TR225. |
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| phase_accurate |
The supply pumping could indeed lead to such a failure if both amps are fed in parallel. This could even happen to a single amp as well if I do a little more thinking. This could only be prevented by having capacitors of significant size AFTER the fuses AND under-/over- voltage lockout.
Regards
Charles |
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| Pierre |
Next time I will monitor the VCC and VSS rails to see if they grow, but I am afraid they don't do too much.
I used 22.000uF per rail (after the fuses, of course) and music (normal LF content, not 20Hz sines or the like :-) Anyway, climbing from 45V to 75V seems too much to me, mainly because I haven't seen that: even in my lab tests with resistive loads, I got 20Hz at 265W while observing that the rails _decreased_ due to transformer losses and 50Hz ripple, instead of having overvoltage.
Besides, the logical thing is that overvoltage should have lead to failure of both modules, right?
Thanks for your help |
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| subwo1 |
| The FQP46N15 MOSFETs are superior to the NTP32N15 ones, I think. What I meant is that if two amps are supplied by a single supply or a +/- dual supply, and the input, stereo or mono, to one them is inverted in respect to the other, the bass reproduction of the two amps will draw power through MOSFETs on both rails simultaneously so long as the inputs have not been independently tone-altered in the bass region of the audio spectrum. The output is put back in phase simply by reversing the speaker connections from one amp. Charles has mentioned this method in the past. |
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| phase_accurate |
| quote: | | Besides, the logical thing is that overvoltage should have lead to failure of both modules, right? |
Not necessarily since one FET might fail at some Volts lower than the other one.
But the fact that your caps come after the fuses rules the supply pumping (for being the cause) out to almost 100 %.
Regards
Charles |
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| Pierre |
Thanks, subwo1. I knew what you meant. But no, there was no pumping compensation at the moment of the failure.
Charles, you are right. Sorry if I insist too much, but I don't think that the supplies have increased more than 45V unless it is too fast that I can't see it with a several ms/div scale. (that's not the nature of pumping, anyway)
Assuming that the rails are +/45V, the mosfets have Vds(br)=150V and that there is no supply pumping, is avalanche still a possibility?
Pierre |
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| subwo1 |
You're welcome, Pierre. It seems not to be from pumping. I think it could be from two MOSFETs in a totem being gate-enhanced at the same time. I see two possible causes of that scenario. One is that the Miller effect is turning one back on because its drain voltage rise has exceeded allowable limits. The way to prevent failure from this problem usually involves slower or delayed turn-on of the opposite MOSFET until the first can get itself off and the voltage flown back by the inductor to the opposite power supply rail.
Another is that your MOSFET drive is being triggered spuriously or randomly a minimum of one time, since once is enough to cause cross-conduction, we know. I wonder what other possible causes of the failure there are. I probably left out something. |
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| Pierre |
Perhaps when connecting inductive loads (i.e. speakers), the PWM waveform has higher spikes at turn off, and it eventually reaches an unallowable Vds value? That could cause one mosfet to fail to shortcircuit due to avalanche, so in the next cycle the other fails too due to overcurrent.
Next time I connect the speakers I will check that waveform and compare it with the resistive load case (where almost no overshoot was found).
If there is another waveform that could be useful to measure, please tell me, I will be doing tests this weekend hopefully.
Pierre |
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| subwo1 |
Hi Pierre, I once seemed to attribute to the inductance of the speaker more villainy than it deserved as far as hardship on the MOSFETs themselves. I think now that, generally, its impedance is too high at the switching frequency to put too much relative strain on them. It may contribute to power supply pumping some, though it doesn't seem to affect even that nearly as much as the filter inductor. But it is good you were able to rule out power supply pumping.
In the vein of the two other ideas I mentioned before, I think there could be a chance that at near maximum duty cycle, one MOSFET could be conducting nearly all the time. But when it switches off, it sends the diode on the opposite rail into freewheel conduction. But before that diode's MOSFET gate enhancement delay times out, the lower MOSFET turns back on again before the diode has time to recover. This explanation reminds me of one analogspiceman gave in the past. The question seems to be then, was the output at or near clipping at the time of failure? |
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| Pierre |
It failed while playing music, but it was not clipping I think.
However, how can that be corrected if it is the cause, adding more dead-time?
Your explanation about speaker inductance seems sensible: although it can make things very bad if the loop is not properly compensated, it shouldn't do harm to the PWM waveform itself.
Thanks! |
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| subwo1 |
You're welcome. Since the top MOSFET gate charging process aborts in this scenario before it gets beyond V(th), if the deadtime were increased more time would be given for the freewheeling diode to start tapering off its conduction. However this option may not be optional since it can increase distortion greatly.
A better alternative may be to limit the input to the amp to keep the duty cycle from getting too close to 100%. If it were simply limited to 98%, there should be enough time for the associated MOSFET to begin conduction and short the voltage across the body diode. Preventing the amp from clipping prevents the filter resonance from making an appearance and adding to distortion, which is related to control loop retaining its effectiveness along the lines of your comment.
Chris mentioned a possibly ideal way which I think is hard to actually implement. It is to prevent the freewheel diodes from conducting by having the timing of MOSFETs precise enough to avoid the body diodes from ever forward biasing. This way would give the minimum distortion too. But this way would seem very hard for the DIYer to implement, but I suspect that the Hypex UcD amps achieve it.
One thing in your favor which should thwart one of the potential appearances of one of the three cross-conduction failure modes, namely the second one, is that the IR2110 has internal logic which prevents both outputs from being driven on simultaneously. That feature is one that I like about the chip. I blew plenty of MOSFETs from that occurrence before I found the IR chip. |
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| phase_accurate |
| quote: | | It is to prevent the freewheel diodes from conducting |
This can also be done using a technique developed by Brian Attwood. He constructed the output coil as an auto-transformer that feeds two fast-recovery diodes so that the body diodes never get into conduction state.
Regards
Charles |
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| phase_accurate |
Below you can see what I am talking of.
Regards
Charles |
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| classd4sure |
Hi Pierre,
I would try increased "dead time" via a bigger gate resistor, if you have ten ohms there now, try it with 20, and maybe even up to 50, in increments.
That should help you rule out the body diode as a possible problem area.
I know it will switch slower but, if you use an old IRF640 it will very likely last the long haul, providing the cooling is there for it. It's harder to drive and will switch alot sloppier all around, as well as the higher Ron.
You may find this interesting, but I've run them in a circuit for days at rather high temps, and they toughed it out for awhile. The circuit had errors which led to serious shoot through. In that same circuit I tried the same mosfets you mentioned that are found in the UCD400. They lasted all of thirty seconds. Seems the more optimal the device is the more optimal everything else has to be as well.
I have the circuit largely fixed now and it has played for a few days with what I think just may be even more optimal devices, the lower mosfet is rather warm but not hot, the upper mosfet is actually cold, I blame a few causes but for the purposes of that particular implementation, it's good enough.
So I feel you're probably better off with a bigger turn on resistor and a more optimal mosfet, than trying to get a dino of a fet to switch fast and efficiently. That's not at all to say not to try the 640 though, go for it.
I think you may have just tried to get the optimal value for THD and in doing so crossed that fine line, and an extra few ohms might be enough to save it.
The other odd thing discussed before is the regenerative effect which causes the upper mosfet to snap on quicker. Does the bottom mosfet run hotter than the top? You could possibly try only increasing the turn on resistor for the upper fet on it's own, and see what smokes. I think trial and error is the way to go because what are the odds you'll catch the very instant on a scope??
You could actually also try a different mosfet in the bottom than on top. I think a slightly slower device on top and a more Cdv/dt immune fet on the bottom. Once you have the problem all narrowed down you might have a tenth look at your layout with that in mind, not to say I know of any problem with it, but maybe you'll spot something you dont' like when you have a better idea of eactly what you're looking for.
Best of luck, I'm looking forward to when you have it all figured out.
Regards,
Chris |
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| Pierre |
Thanks for all your support.
I will try with two identical circuits but different mosfets:
FQP46N15's in one and IRF640N's in the other. Let's see which of them lasts more time in the same conditions. However, at the end, I would like to go for a lower Rds(on) for efficiency. I really don't know why FQP46N15 shouldn't be perfect!
classdforsure: I really didn't notice which of the mosfets was hottest, because they are now placed "back to back" in a common heatsink.
Charles and subwo1: I am sure that techniques are quite optimal, but I am also sure that the circuit can work perfect in terms of reliability while keeping it this simple. For example, IRF ref. design uses a very similar power stage, Crest LT also does, there are plenty of designs using the basic app. note of the IR2110 devices. I think it is "only" a matter of having the right mosfets, the right layout and the right dead-time and turn on/off times.
BTW: Anyone knows what mosfet the current ZAP Pulse modules have?
Best regards,
Pierre |
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| Pierre |
One thing more, to clarify things:
After reading the philips App.note on avalanche SOA:
It seems to me that repetitive avalanche failure should be produced by either exceeded repetitive avalanche energy or by exceded junction temperature over a long time. My mosfets weren't too hot, so _if avalanche was the problem_, the avalanche energy rating must have been exceeded.
To sumarize, the single-pulse avalanche energy is:
Eas=0.5 x L x Ias^2 x (Vbr/Vbr-Vcc)
being Vcc the total rails voltage and Ias the inductor maximum current (Vout_max / RL_min)
Is this correct? That gives about 3mJ, much less than rating.
BUT: How is repetitive avalanche energy calculated?
Thanks! |
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| ekaerin |
Hi,
You can try lets say a 3 to 1 ratio turn on / turn off resistor value.
This way you have a moderate turn on (10-20 Ohm) and a fast turn off (2.2-4.7 Ohm).
Layout is crucial, no load current shall pass the drivepath and the
path (drive-return) shall be as short and low in inductance as possible.
Otherwise the driver can't hold the gate down. Also look at the ratio of the Miller vs gate source cap. If the gs cap is lower than the
miller add a few nF to gs to split the miller charge kicking back.
The IR drivers can output anything and also break if the Vs node
goes south of com by more than a few volts.
/ Mattias |
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| Pierre |
Thanks, Mattias.
Is the Miller cap Coss (output capacitance) or Crss (reverse transfer capacitance)? I suppose it is Crss.
In the FQP46N15, Ciss (input capacitance) is 2500pF typ, while Crss and Coss are 100 and 520pF respectively.
In the NTP35N15 the relationship is very similar.
For the control of turn on/off times, I currently use a 10r resistor in parallel with a schottky, so turn on has the 10r gate resistor while turn off is done as fast as the driver can.
What do you think?
Thanks |
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| Pierre |
Ah, about miller charge (Qgd), it is about double of Qgs charge, but this happens in FQP46N15, NTP35N15 and even in IRF640N, which ZAP pulse amps used. Is that what you were referring to?
My layout is not bat IMHO. The gate signals are only crossed by heavy current tracks in the yellow marked zones of this scheme:
Hope this drawing is clear enough to follow the gate drive routing. Mosfets are mounted "back to back".
Thanks. |
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| classd4sure |
Boy that's a can 'o worms.
The gate charge ratio topic isn't a straight forward one and if you do some searching you'll find many conflicting app notes on the topic.
First the repetitive avalanche question, the two links I gave on the topic explain it and give some examples, I think you have to make use of the thermal impedance curves...
Back to the gate charge ratio:
Even some mosfet manufacturers actually make claims of Cdv/dt
"immune" parts and all they use is the ciss/crss ratio outright, which doesn't seem right because it's alot more complex than that. I'm stunned they make semiconductors and prescribe to that theory.
Here's a fine example:
http://www.semtech.com/pdf/sc420.pdf around page 8. It even recommends adding that gate to source capacitor.
I personally don't feel the gate to source capacitor would be an effective counter measure, It would "split" the miller charge only after it's acted upon the gate by passing through the gate resistance, so it wouldn't help the problem at hand, and also slow turn on. It may however allow the gate to sit lower with respect to the source and by doing so make it a little more immune to gate step, but that's ugly, as a diagnosis measure you wouldn't know if it is helping make it more immune to the gate step by having the gate go lower, of it if helping by slowing Dv/dt. I'd just go with trying a bigger resistor and seeing what happens.
Here's the app note I go by:
http://www.irf.com/technical-info/w...cbuckturnon.pdf
Use a spreadsheet to make a calculator based on Eq:12 and you can compare mosfets with one another alot more quickly. Is it 100% bullet proof method? Apparently not, but it gives you some idea and is alot more accurate than just ciss/crss which is unrealistically simple.
I'm no PCB artist but those current loops don't look all that short? I think you really want all the parts kissing, or as close to that as you possibly can.
Best Regards,
Chris |
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| Pierre |
Wow! That appnote is very good!
I am starting to think that my problem is not mosfet rudgeness but Cdv/dt turn on or spurious turn on due to couplings in the gate drive paths.
Does this problem (Cdv/dt) apply only to the lower mosfet or it does to both of them?
I will look at this appnote more deeply and also at my waveforms on saturday.
Thanks for your help. |
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| Pierre |
I suspect that Qgd or Qgs1 are not directly that especified in the datasheets as "Qgd" and "Qgs", right?
In that case, one must calculate the correct Cgd and Cgs values (not readily available in the datasheets) from the other C's given, right? And that depend on the Vds voltage.
For example, IRF640 datasheet says:
Ciss=Cgs+Cgd, Cds shorted
Crss=Cgd (wow! we have one)
Coss=Cgd+Cds.
So we have Cgd=Crss and Cgs=Ciss-Cgd?
Then, from datasheet's fig.5: for this mosfet at Vds=100V: Cgd=Crss=300pF
Cgs=Ciss-Cgd=1500pF-300pF=1200pF
Thus Cgd/Cgs=0.25 (OK)
For NTP35N15:
Cgd=Crss=nearly 0pF
Cgs=Ciss-Cgd=2200pF aprox
Thus Cgd/Cgs is very low (OK)
Is all this well done? |
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| classd4sure |
Nope, but your close.
You're strictly using capacitance and you need to evaluate it using charges.
I'll quote the app note:
"However, Cdv/dt induced
turn-on at Q2 also depends on Vds and threshold voltage
Vth. It then makes sense to use gate charges instead of
gate capacitances to evaluate the Q2 device.
One intuitive way of interpreting the Cdv/dt induced
turn-on problem is the accumulated miller charge. When
Vds reaches the input voltage, it should be smaller than the
total charge on Cgs at the Vth level so that Q2 will not be
spuriously turned on."
Use equation 12 found on page 5. That's why I mentioned a calculator might make it easier to compare different mosfets quicker. But yeah, you do need to read the capacitances like you had done, and plug those into the equation.
I tried explaining it before as I understood it:
http://www.diyaudio.com/forums/show...3641#post433641
I think you'll find the answers to be less optimistic. |
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| Pierre |
Yes, you are right.
I reviewed the calculations after posting and found that results are not so good: using eq. 12, you have:
For IRF640N:
Qgs/Qgs1=300pF*(100-4)/(1200pF*4)=6 !!!
How can this work reliably in earlier ZAP Pulse modules, then?
Another thing that I don't understand is that this equation doesn't show relationship with dV/dt, so having this high ratio musn't make us discard that mosfet for 100V operation, right? |
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| classd4sure |
Yeah that's disgusting isn't it?
Now that doesn't account for the heating caused by it, the level of current that will flow, or for that matter if it will turn on so hard that it explodes. All that tells is that it isn't an optimal device to use for the synchronous mosfet, because it will no doubt be heating like crazy as the gate step is more than big enough to cause substantial current flow in this case.
When I used them they both ran hot as hell but the circuit wasn't "right" so I can't attest to that really, also it was much lower voltage.
You know what though, you should do that calc with Vth min, that's basically when current flows, which is 2 volts, which doubles your answer to ~12. Ewwwww.
Now try it again with this puppy using Vth min of 2volts:
http://www.fairchildsemi.com/ds/FD%2FFDP42AN15A0.pdf
I wasn't very uptight about selecting the capacitance values,
I used Crss=20pF and Cg~2nF, and it's actually probably higher than 2nF.
I got ~ 0.45! How is that for a leap in technology? |
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| ekaerin |
Hey,
To make things more complex. Look at the graphs showing the caps vs voltage.
You will find that at low voltages the caps are higher, at least some.
And yes, adding Cgs externally can't cure what is going on inside
the transistor case but may still help a bit from the drivepath point
of view. The cap must be as close to the transistor pins as possible.
Also, all drivers and FETs leak current so adding a 10k resistor at gate-source is nice.
/ Mattias |
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| classd4sure |
Hi Mattias,
We actually are reading the cap values off the graph in order to account for the changing capacitance with voltage. Miller capacitance is hugely non linear.
You can't use the given capacitance values found under the max values (?) section for the same reason you just can't use the given charge ratio's ..... even when it seems like they are giving you the relevant charge ratio's, the reason is because those values were taking at what is likely to be different conditions than you're interested in.
An interesting point about this is due to the changing capacitance Vs voltage, you might find a mosfet that gives an OK ratio for one particular voltage but not for another.
As far as selecting mosfets, I think the pro's are privy to some information we may not be as well, like if you're going to be ordering 10 000+ you can talk to sales reps or maybe even designers and perhaps get some recommendations etc.
Fairchild devices seem to be pretty good with their charge ratio's, I have yet to check any of IR's decent mosfets for it.
Note that the IRF640 they were done for here was the old version and not the IRF640N, it maybe interesting to do them both.
You'll still find app notes that show this method isn't accurate but I believe it is OK for a ballpark idea which is all we're really after here anyway.
.....mosfets...... and they said they were easy to drive. :xeye: |
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| phase_accurate |
| quote: | | And yes, adding Cgs externally can't cure what is going on inside...... |
To make matters worse, the lead inductance will give some more uncertainty on what's going on inside and what we see outside.
That's also the thing I'd like to mention regarding Pierre's layout. It is not only the LENGTH of the tracks in the gate-drive circuit that are critical but also the SHAPE. The loop inductance is very important. Have a look at the following drawing. The second loop has less inductance than the first one despite the longer track lengths.
Regards
Charles |
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| Pierre |
Sorry, I made a mistake with IRF640N.
The ratio should be something near 1-1.5 (at Vds=100V)
And for IRF640, it is about the same.
BTW: classd4sure, I think ZAP pulse used IRF640N, not IRF640, look at the photos in their webpage ;-) Anyway, they are similar in this particular aspect.
Curious: my FQP46N15 seems to have a ratio of about 0.5 at 100V. However it failed once (although in the lab, perhaps I did some short-circuit :-(
NTP35N15 is difficult to calculate por 100V, but seems to have a ratio higher than 1. It has failed in my circuit several times.
Best regards |
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| classd4sure |
Pierre I believe I made the same mistake as you, voltage we used to read the cap value was 10V wasn't it, I suppose it would make some difference :)
I cooked two sets of FQP46N15's myself, making the point everything needs to be perfect. You've just taken measures to be less concerned that they could be frying from a Cdv/dt induced spurrious turn on issue, however, that seems to imply an ideal layout and everything.
Let's say you have a "springy" source issue, due to layout, the Cdv/dt immunity might make it a bit more rugged and so it may last longer but it doesn't mean it can't fail from it. Maybe this is what you're experiencing.
Charles,| quote: | | The loop inductance is very important. Have a look at the following drawing. The second loop has less inductance than the first one despite the longer track lengths. |
All I knew about "shapes" was "no sharp turns" and I understand why, in this case I would like to understand more, what is the mechanism at work to cause the second loop to have less inductance?
Thanks |
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| Pierre |
| quote: | | Pierre I believe I made the same mistake as you, voltage we used to read the cap value was 10V wasn't it, I suppose it would make some difference |
Yes, 10^1=10, not 100!!!! :dead:
| quote: | | I cooked two sets of FQP46N15's myself, making the point everything needs to be perfect. You've just taken measures to be less concerned that they could be frying from a Cdv/dt induced spurrious turn on issue, however, that seems to imply an ideal layout and everything. |
Yes. I have also thought on adding a gs resistor (1-10k). And a zener in antiparallel with Vgs to limit the max. Vgs to about 15-18V. Just to protect the gate.
About the "springy" source, I suppose you mean the high side mosfet source, going below -vcc, right? I suppose I have to measure that properly too in the lab.
BTW: IRF ref. design uses IRFB23N15 that has a ratio of about 1.5 at 100V. They also seem to be reliable and they don't use anything sophisticated in the gate drive, just IR2xxx + 9.1R gate resistor + antiparallel schottky. Mmmmm.
Charles, I would also like you to enlighten us a bit more about reduction of inductance in the tracks!
Best regards,
Pierre |
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| phase_accurate |
Simply because the loop is basically an (air cored) inductor with only one turn.
If you now look at the literature you will see that a coil's inductance is proportional to its AREA, the square of its number of turns and the inverse of its length (which is almost zero in our case). The enclosed area of the second loop is clearly smaller than the first one's.
There is a Tripath Appnote that describes these things quite well and you see it also mentioned on some IRF docu. I don't know how reliable Tripath's demo boards are but they seem to get away with quite long tracks between the driver and the output FETs.
We may never forget that it is sometimes only small details that make the difference between a reliable and an unreliable design.
Regards
Charles |
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| classd4sure |
| quote: | | About the "springy" source, I suppose you mean the high side mosfet source, going below -vcc, right? I suppose I have to measure that properly too in the lab. |
I mean say you have too much inductance in the driver current loop, particularly between Vcom and the source pin, you're creating a bigger spring and with enough output current and miller feedback it just may be enough to cause spurrious turn on regardless of it's ratio. (that's just a guestimated theory).
Charles thanks for the explanation and also, a very good point, as always.
Regards |
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| Pierre |
Thanks, Charles. Simple but convincing. You must be a teacher of have some teaching experience, am I wrong?
| quote: | | I mean say you have too much inductance in the driver current loop, particularly between Vcom and the source pin, you're creating a bigger spring and with enough output current and miller feedback it just may be enough to cause spurrious turn on regardless of it's ratio. |
Classdforsure, if you refer to low side mosfet, I get you. >BTW: I have a current sense resistor between source of low side mosfet and -VSS. But I understand that, as long as VCOM of the driver is connected to the mosfet source (not to -VSS), I guess that's ok, right?
What about the zener in Vgs? Can it have any bad influence?
I am also starting to consider a active PNP turnoff to avoid spureous turn-on. Any simple ideas? If I find a simple solution I will keep you posted. |
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| subwo1 |
| Hello Pierre, Some suggestions regarding gate pull-down resistors and zener over-voltage shunts. At the frequencies involved, those resistor values may have negligible effect. The zeners, usually make things worse during high speed gate drive since they cause ringing which can exceed the gate oxide layer dielectric strength. Not to say I haven't tried it though, but it just made things worse. |
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| Pierre |
Thanks, subwo1. It is only that I have seen at least the gs resistors in several designs (Crest LT series, for example). The zener was my idea, perhaps only valid for switching at low frequencies, anyway.
Best regards |
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| classd4sure |
| quote: | Originally posted by Pierre
Thanks, Charles. Simple but convincing. You must be a teacher of have some teaching experience, am I wrong?
Classdforsure, if you refer to low side mosfet, I get you. >BTW: I have a current sense resistor between source of low side mosfet and -VSS. But I understand that, as long as VCOM of the driver is connected to the mosfet source (not to -VSS), I guess that's ok, right?
What about the zener in Vgs? Can it have any bad influence?
I am also starting to consider a active PNP turnoff to avoid spureous turn-on. Any simple ideas? If I find a simple solution I will keep you posted. |
What?!?? Charles?? A teacher?? How can that be, when he actually answered the question informatively, and knows what he's talking about?
About that current sense resistor, yes at first glance it appears having your Vcom right to the source pin takes that out of the equation, but, is it still in the overall current loop?? How is the IC itself grounded for instance, you still have VSS and the drivers VCC drive loop, which you may still find the current sense resistor is actually in. I'm not sure given the nature of the internals of the IC if this would be a problem or not, but it may be worth looking into or experimenting with. Please let me know what you come up with if you do.
I dont' think a PNP turn off could hurt, that's only one loop minimized though.
I've often read alot about what Subwo1 just said, zeners can cause oscillations and it's best to avoid them.
Besides if it is something like a springy source causing spurrious turn on, the destructive mechanism is the spurrious turn on itself and not exceeding the gate voltage limits.
It might be worth just experimenting with a few different layouts or two before you go adding more ingredients into the mix though, one problem at a time sort of thing.
Regards |
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| Pierre |
| quote: | | About that current sense resistor, yes at first glance it appears having your Vcom right to the source pin takes that out of the equation, but, is it still in the overall current loop?? How is the IC itself grounded for instance, you still have VSS and the drivers VCC drive loop, which you may still find the current sense resistor is actually in. I'm not sure given the nature of the internals of the IC if this would be a problem or not, but it may be worth looking into or experimenting with. Please let me know what you come up with if you do. |
IR2110's VCC is conneted to the floating supply, while IR2110's VSS is connected to -VCC, so the sense resistor DOES fall inside that loop. It is NOT included in the gate drive loop, however, as the return for that loop is COM pin, not VSS.
VSS is only the logic input ground. I think this is ok this way, isn't it?
Thanks |
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| classd4sure |
When the topic of that sense resistor came up originally I'd simulated the situation with a discrete driver.
What I found was that yes, in the VCC-->VSS loop the sense resistor of even ultra small values had a disgusting effect.
Said effect totally vanishes if the VCC supply floating on the negative rail were instead grounded to the source pin as well thereby shoring the sense resistor from the driver's loops.
So I think unless the VSS pin and Vcom pins of the driver are internally connected, it is likely to cause some problems. Perhaps an ohmeter and a spare driver chip will answer this question.
Otherwise perhaps VSS is best connected to the source pin as well ?
Sorry I can't tell you more I have never used those IC's. Hey, way to stick with this!
Regards |
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| subwo1 |
| I have used the chips often, but felt leery of separating the supply return paths, though the IR2110 data sheet seems to say that a 5 volt difference is tolerable. With transients and noise around, I try to keep all commons connected to one point and avoid source current sense resistors. With some diodes and high valued resistors, the voltage rise on the lower MOSFET drain can be monitored instead. I have tried it similarly to what this diagram shows. However, for class D audio, triggering needs to be done on a Schmitt trigger external to the IR2110 so that full cycle protection can be engaged. This circuit is more for capacitive coupled transformer drive in an SMPS. |
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| phase_accurate |
| quote: | | You must be a teacher of have some teaching experience, am I wrong? |
I am not a teacher but I have actuallly some limited experience in teaching.
| quote: | | How can that be, when he actually answered the question informatively, and knows what he's talking about? |
Fotunately there are also exceptions to that "rule".
Regarding the IR2110:
The VSS and COM can actually differ by up to +- 5 Volts. This is intentionally so and can be taken advantge of for improving EMC behaviour.
So the precise transmission of the control signals from the input circuitry to the actual driver should still be O.K. with your sense resistor.
But maybe we have to further analyse what happens to the output voltage-swing of the driver. Keep in mind that we "modulate" its negative supply (by the voltage-drop through the sense resistor) while we keep Vcc constant (or dou you keep Vcc to COM constant in your application ? . There could be a reason why IRF senses overcurrent on the upper drain only (within their reference design) !
Regards
Charles |
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| classd4sure |
| quote: | | But maybe we have to further analyse what happens to the output voltage-swing of the driver. Keep in mind that we "modulate" its negative supply (by the voltage-drop through the sense resistor) while we keep Vcc constant (or dou you keep Vcc to COM constant in your application ? . There could be a reason why IRF senses overcurrent on the upper drain only (within their reference design) ! |
This is also along my line of thought.
In my little simulation the gate signals were indeed modulated, and that is even with values for a sense resistor so low as .001R.
They only seem to say that the driver tolerates the difference.. further investigation on that would be nice, but for a quick n simple way, would it be alright to short the Vss and Vcom pins together? If so that might be telling enough.
Regards |
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| Pierre |
Yes, VSS pin can be tied to COM pin, but all the circuitry (level shifters and dead-time) is referred to what -VCC, so shorting VSS to COM would effectively imply shorting the sensing resistor, so all the current would pass by a inapropiate path and also null current limiting.
To do the test it is easier to short both resistor legs. In fact, I have done some of my tests shorting that resistors. I have to check if there is a relationship between failures and the presence/absence of that resistor.
BTW: as opposed to IR ref. design, Crest LT design for example uses low side current sensing and VSS is connected directly to the negative rail.
Best regards,
Pierre |
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| Pierre |
subwo1: excellent, that circuit is simple enough to worth a deeper view.
I suppose that circuit uses Rds(on) to sense current. I understand the need for a latching for this application. Modifying that by using a latch should not be difficult.
However, I see some drawbacks (take them as suggestions only :-)
Rds(on) is dependent on temperature, so sensitivity or overcurrent trip level will also be. That's not bad per-se, as current limit will be lower as temperature rises, so it is very safe.
Best regards |
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| phase_accurate |
| quote: | | They only seem to say that the driver tolerates the difference.. further investigation on that would be nice, but for a quick n simple way, would it be alright to short the Vss and Vcom pins together? If so that might be telling enough. |
Connecting those pins together is the most ordinary way to use this IC but a part of "most ordinary" means also usage without sense resistor.
I have to search again for the info about the negative supply voltage difference. On the IR2110 datasheet you can see that they recommend not to go beyond +- 5 Volts while they can bear quite some more actually (max ratings section).
Regards
Charles |
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| subwo1 |
Thanks, Pierre. Indeed, as the MOSFET heats, a trigger would trip sooner. Since a 74C14 contains 6 gated outputs, the output of the triggered gate could pass to another input whose output is fed back to to the first gate through a diode to latch it.
For 45v rails, the rectifier diode could be traded in for a 1n4148 so that junction capacitance can be minimized, improving performance. In one power supply circuit, I replaced that UF4004 with a series of 1N4148 diodes which did two things. It increased the breakdown voltage and in the other direction the forward voltage drop was the determining factor for when the protection would kick in. |
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| Pierre |
Sorry, but I still don't understand the operation of the circuit.
If I get it right, when LO is 0 it pulls SD pin low through de diode at the right. but isn't that moment where you should sample the VDS voltage of the lower mosfet to sense the current due to Rds(on)? |
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| subwo1 |
| No problem, when the lower MOSFET is on, the LO is high so that a rising ds voltage on that MOSFET lets the resistor connected to the gate pull the shut down pin up to trigger it. The instant LO goes low, the diode connected to it quickly pulls down the sd pin prevent interference with the next half cycle of the waveform output. |
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| subwo1 |
| Pierre, I am glad of your resolve, too, in getting to the bottom of what may be happening in your circuit.:) |
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| Pierre |
Sorry! I made a mistake thinking that LS mosfet on => LOpin=0!!!
I think I get it. Did you get effective short-circuit protection with that? is it fast enough? Does it work with low Rds(on) mosfets?
Thanks and good point!
Pierre |
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| subwo1 |
| It's very much OK, good perception about low Rds-on MOSFETs, too. Let's see. If Rds is .025R, and the current is 20a, we get half a volt to trigger within. I think it is doable. It triggers instantly, but since the speaker is DC coupled to the output, if we just truncate the lower on-time, we could get a heavy DC Bias on the output. I wonder if the feedback circuit of the amp will cut off the upper MOSFET in order to try to re-establish balance. But if we figure that the amp is the problem in the first place, we need to latch a separate external trigger which can use diodes to pull down both inputs to the IR2110 and hold them low. |
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| Pierre |
I assume that you worry about that DC problem with the circuit "as it is". I agree, but as soon as you put a quick reacting latch, it will proctect well.
If I understand well, focusing on the half-cycle where LS mosfet is ON: you have a voltage divider from 12V (LO output) to VSS+IxRdson plus a diode drop. So if there is no loading,
you have 0.7V+ 11.3*30k/(82k+30k)=3.9V aprox.
If you have, say, 20A and a Rds(on) of 60mohms, you have about 1.2V+0.7V+(12-1.2-0.7*30k/(82k+30k))=4.6V aprox.
Am I calculating ok? I suppose that the trimmer way is how one finally does this. |
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| subwo1 |
Doesn't seem quite right. Lets break it up into bits, especially since I am not good with math. The first part is good, the voltage floor is the 1.2v drop across the MOSFET plus the .7v diode drop--1.9v. The LO pin is at 12v, OK. The trigger point is about 1/2Vcc + 1v, or 7v, maybe 7.5v really. 12v-1.9v=10.1v; lets round to 10v. Now we figure the voltage divider. 30k+82k=112k. 112k / 10v = 11.2k per volt, rounded to 10k/v. 30k / 10k/v= 3v. 3v plus the 1.9v floor equals 4.9. Good job! You had it right with the single formula. How, I don't know.:D
So as it is it trips at about 20amps. Trying to get it exact this way can lead to brain damage. Using a trimmer pot is an easier way. Best to place in the lower leg of the divider so that if the wiper contact opens up, the trigger point will drop. However, just using a two resistor divider does eliminate that concern. |
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| Jaka Racman |
Hi,
I can also wholeheartedly reccomend subwo's desaturation protection circuit. I use similar circuit (only instead triggering SD pin i trigger small SCR that discharges driver supply caps and demands manual restart). I did not have a single dead Mosfet in 3kW PFC design over last 5 years.
Charles,
thanks for taking your time and drawing a nice illustration of proper way of minimizing loop inductance. I think that people grossly underestimate importance of tight loops in layout. A most common thing I see is bypassing electrolytics with film caps. Encouraged by Guido Tent's comments (and Bruno's) I recently measured a lot of different electrolytics and other caps on HP impedance meter that can go up to 13 MHz. All wound foil film caps have higher inductance than electrolytics. Stacked foil caps are comparable. The most shocking was smal no name 1uF/50V electrolytic i pulled out of dead ATX power supply. It measured 3nH, the same as 2-3mm diameter loop of wire. For comparison, Oscons have 6 to 9nH of inductance and 1cm square loop of wire has 17nH. So what is the point of bypassing 12nH electrolytic with structure that can easily have 30-40nH of inductance, small C and low ESR. It only makes things prone to ringing.
But there is a little trick that TI uses in their class Damps. They use around 100nH inductor (IIRC) in positive rail and then series RC snubber directly across supply pins of Mosfet totem pole. I think that there is even patent for that, that dates back in Toccata times (before TI bought them). Hopefully I will find it again.
Best regards,
Jaka Racman |
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| IVX |
| quote: | | Rds(on) is dependent on temperature, so sensitivity or overcurrent trip level will also be. That's not bad per-se, as current limit will be lower as temperature rises, so it is very safe. |
Even more! I wondered about the stable threshold when i've studied ir2127.pdf. The diode placing close to the mosfet(for the equal temperature) lend pretty stable current threshold. IRF3205@50A@+1N4148@9mA =.989V100C° and 1.083V20C°. |
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| subwo1 |
| Hi Jaka Racman and Ivan. Thanks for your thoughts!:) |
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| Pierre |
Do any of the diodes need to be schottky or can it be implemented with two 1n4148?
I am thinking on doing an experiment, but using a lower trigger point, say 1V, to excite a transistor that latchs, etc.
BTW: I removed the damaged mosfets from my last amp. They _were_ NTP35N15. One of them has three pins shorted together, the other one doesn't have a short in the gate to the other pins (only between S and D). I suppose this doesn't tell anything about the failure mode...
The failed amp didn't have the sense resistor, either, only a thick tin short. So that doesn't seem to be related either.
Best regards |
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| Jaka Racman |
Hi Pierre,
I use MUR106 for offline applications. I suggest you use a low reverse capacitance diode like 1N4148. Schottkys have large capacitance and even worse: significant leakage current.
I think that for Mosfet protection triplevel is not very important. Something else is if you want exact current limiting. I think that with desaturation protection you can forget about exact current limiting and use thermal protection instead.
Best regards,
Jaka Racman |
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| subwo1 |
| I think 1N4148 diodes should work the best. Since you are just latching your protection on, the transistor way sounds good. |
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| Pierre |
After reviewing a bit more the Cdv/dt issue, some of the app notes talk about watching at the gate waveform to see the spikes that can cause spurious turn-on if they reach Vth.
I have a question here: this problem doesn't seem to have nothing to do with drain currents, so it should manifest even at light loads. I mean, if that's the problem, a spike should be seen when the Vgs voltage is low and the other mosfets is turning on, right?
I checked my gate waveforms with both 6 ohm and 10 ohm gate resistors, with load but no input signal, and they looked this way. I attach the 6 ohms one, the other is almost identical, a bit slower. Can I stop worrying about Cdv/dt then?
The little spike at turn on should be due to the miller charge, but there are no spikes when the mosfet is turn off... |
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| classd4sure |
Hi,
It looks like there's a bit of a step on the lower one. What's that at 5V/div? ~.5V gate step with no substantial output current, why not give it a try with output current and compare them, it just may get worse.
Hey, are those on the same scale? How do they measure pk-pk it almost looks like they aren't the same. |
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| subwo1 |
Hi, I think the bigger problem may actually occur when the lower gate is being pulled low, but the Miller effect occurring when the upper MOSFET is pulling its drain high is trying to turn it back on. It may be showing up in the thickened portion of the falling edge of the gate waveform and appears to happen within a very short time interval.
Hi Jaka, we practically crossed in our postings, but I am glad that we said practically the same thing concering the 1N4148 diodes. |
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| Pierre |
Thanks for the soon response to both of you. I love this forum and how helpful people is in it.
The lower one is actually HS mosfet. Yes, the scales are the same. It seems that the HS has a little less amplitude. I will check the other figure (with 10 ohms) to see if it happens the same.
Have in mind that both waveforms are not taken at the same time, so time is not aligned.
I will check with heavier load (I will need to trigger with a digital storage oscilloscope, as the signal moves its duty cycle when a large signal is present).
Best regards,
Pierre |
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| Pierre |
Yes, I have checked with the 10r waveform and there is a little difference in amplitude, 11Vpp in the high side instead of 12vpp in the low side. Don't think that's a problem. Can be due to the diode drop in the bootstrap circuit, right?
Please have a look at this: it is the 10r waveform. It shows a little more garbage in the turn-off phase, perhaps.
I will check with heavy load, however.
Best regards,
Pierrre |
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| classd4sure |
Hi,
Yeah I believe that would be the cause of the difference, and I agree it isn't a big deal, I spotted a difference but couldnt' tell if it was 2 volts or....? No cause for concern there.
That gate step looks more pronounced in this screen, it's funny though I would expect to see that in the bottom driver. Let's see what happens with higher current :) |
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| Pierre |
| quote: | | That gate step looks more pronounced in this screen, it's funny though I would expect to see that in the bottom driver. |
Sorry, don't understand you. What do you mean with "gate step", the little glitch that is attributed to the miller charge, or you mean the rise/fall times?. Why did you expect to see it in the bottom driver? (remember that the lower trace is HS driver in both screens).
Pierre |
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| subwo1 |
| I have been thinking that since it is an IR2110 driver, the Miller effect should be about the same for the upper and lower MOSFET. That symmetry should be a good thing. |
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| classd4sure |
Well, yeah, the little glitch associated with miller.
I expected to see it on the bottom because it's the synchronous mosfet that's most susceptible to Cdv/dt induced turn on (it causes a "gate step").
I actually believe it can happen on the high side as well, but with good rail decoupling there it should be less of a concern.
Dead time and output current may play a roll here too. I'm curious to see what happens with more current flowing. Maybe you can check it at different output levels, low medium high? I suppose results will differ depending when you trigger it. |
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| Pierre |
Don't rely on that captures more than necessary, perhaps the little gate step is there but the resolution of the oscilloscope has missed it in some of the drawings.
| quote: | | I expected to see it on the bottom because it's the synchronous mosfet that's most susceptible to Cdv/dt induced turn on (it causes a "gate step"). |
The "synchronous" mosfets is the lower one, right? That corresponds to the upper waveform in my captures. I think now I get you: in my waveforms the worse turn-off phase appears in the HS mosfet, that's not very logical.
Perhaps that's due to ringing instead of Cdv/dt, or simple parasitics in the oscilloscope lead (although I used 10x probe with a little tip with the grounding just by the tip to minimize the loop inductance that may pick up unwanted signals)
Yes, it will be hard to trigger. I think I will take a lot of captures for each power level to catch several duty-cycles and look for the unwanted spureous trials-to-turn-on.
I will also measure the PWM waveform looking for ringing or overshoot that could lead to avalanche.
Best regards |
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| Pierre |
One thing more, about the coils, only to make sure they are not having influence on the failures.
I have tested the coil with a impedance analyzer. The results are:
-Inductance from about 500Hz to about 5MHz: 20uH.
-Resistance: about 30mOhm at DC, 180 mOhm at Fsw (270KHz)
-Capacitance: -16nF at Fsw.
saturation current must be quite high following micrometals inductance calculator (more than 20A).
The self-resonance is located at 10.6MHz. From there, the inductance is negative and the capacitance, positive.
What do you think of this?
Best regards,
Pierre. |
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| Pierre |
I have done some measurements this morning.
About gates, they seem the same as what I have shown before, but it appears a nasty spike just before going up in both sides. This spike goes to about -5V. I don't know if it is a probe pickup, although I have measured it the same way as before. I am currently using FQP46N15's.
About the PWM waveform, it shows some undershoot of more than 20V amplitude in the negative side, and only with high power (tested with resistive load). I don't know if that's another noise pickup, but that makes Vds of the upper mosfet be about 120V. Perhaps more with another kinds of loads.
About VS pin with respect to COM pin, it doesn't show any apreciable undershoot, measure just at the IC pins.
What do you think about the coil measurements I have put in my previous post? |
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| Pierre |
Seems that I am the only mad that works on weekend! ;-)
If you see my previous posts, you'll read that I have found some overshoot in the negative portion of the PWM signal increasing with higher power levels. That worries me and I was wondering whether reducing dead-time would help, as it would reduce the time that the signal is freewheeling...
Any opinions?
Best regards |
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| subwo1 |
| Hi Pierre, na, just not sure what to suggest right now. 5v undershoot does not seem too bad. It is actually a little bit like adaptive dead time, so it may not be bad to lessen the dead time some to lower distortion a little, if nothing else. |
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| Pierre |
Thanks, subwo1.
There are two undershoot problems, actually: the one in the gates (5V aprox), and in the PWM signal (more than 20V with high power output).
I don't know where the gates undershoot come from, perhaps it is only probe pickup.
But the other one makes me think that Vds(br) can be exceeded at some moment and cause mosfet failure. I also wonder why is it present only in the negative portion of the PWM and not in the positive.
Best regards |
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| phase_accurate |
When you talk about a spike on the negative-part of the PWM - I assume that you mean a spike on the output signal when going low. This could be caused by the parasitic inductance of the FET (or any other circuit parasitic inductance as well of course), preventing the body-diode from turning on fast. I don't have an explanation why it doesn't happen on the positive-going side apart from differences in timing or maybe that it is indeed caused ba parasitics of the layout rather than the inductance intrinsic to the FET.
How does it behave whan you add a snubber ?
Regards
Charles |
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| subwo1 |
| You're welcome. The gate voltage drop is caused by the Miller effect. It is not a problem at -5 volts. But the source undershoot could cause breakdown and avalanche and then smoke. Maybe try adding 1000pF from the totem pole outputs to ground to slow the transition some. The Miller effect will also be reduced, but hopefully enough will still remain to provide a little dead time. |
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| Pierre |
Thanks, Charles.
I haven't still tried with a snubber. What do you suggest, a snubber from PWM to -Vss and another (if required) from PWM to VCC?
I suppose that the way to go is to put a R in series with C, the R being low valued (about 22ohm?) and C of about 1nF. |
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| subwo1 |
| I think try the 1000pF without the resistor, maybe, first, from the MOSFET side of the filter choke to one rail, or two 470pF, one to each rail. |
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| Pierre |
Thanks, I will try.
Best regards,
Pierre |
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| subwo1 |
| Sounds good and you're welcome. In fact, go straight from the drain to the source of each MOSFET, I think, with a 470pF on each. If you can get away with 1000pF on each, it should be even better so long as there is still enough dead time. My experimentations with zero voltage switching leads me to believe this way. |
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| Pierre |
| quote: | | If you can get away with 1000pF on each, it should be even better so long as there is still enough dead time |
But how can the simple addition of the 470-1000pF between drain and source affect dead-time?
Zero voltage switching? I want to know, I want to know! :smash: |
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| subwo1 |
It should slow down the rate at which the voltage on the drains can flyback to the sources because of the output inductor. The result is improved switching too, so long as the inductor has enough stored energy to charge/discharge the capacitors during the transitions. By slowing down the transition, the Miller charging of the gate-source capacitance is kept from building as much because the series gate resistor shunts the charge as it is added. If the gate resistor is too small, and the d-s capacitors too large, the Miller effect will not be able to keep the gate unenhanced before the output finishes its transition. Then, the switching efficiency goes from the gain category to the loss side. It is a delicate balancing act to get it optimized.
The above mechanism is a type of adaptive dead time and is one element I am incorporating into my latest updated ZVS power supply. My ZVS power supply also needs phase feedback from the MOSFETs to the oscillator so that once the feedback shuts off each output switch, the opposite MOSFET turns on as soon as the voltage flies to its peak, which is ideally at the opposite power supply rail.
In classD, the phase feedback should not be necessary since the dead time is never capable of getting so high as it can in the ZVS power supply. In class D, when one MOSFET shuts off, the easiest thing is to let the output go straight to the other rail with no chance for extra dead time. |
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| phase_accurate |
Adding "pure" capacitors can lead to increased overshoot. The snubber is actually representing a lossy cap which is 1.) reducing the Q of parasitic resonances and 2.) lowering the f0 of said resonances.
The 1nF cap with 1 to 100 Ohms (or your proposed 22 Ohms) in series is not a bad value to start with.
I would place it accross the Mosfet, since this is the component you want to protect with this measure.
Some may complain about the losses introduced by snubbers. These are not that severe however if you take enough care about a good layout with the subsequent need for very small snubbers only.
As long as the snubber's timeconstant is small enough that the capacitor is fully uncharged during each half-cycle the loss in the series resistor is calculated by (approx):
Ploss = C * 4 * Vpeak^2 * f
That means an amp running at 250 kHz and being capable of supplying 100 volts peak would actually produce 10 Watts of snubber loss when a snubber with 1 nF is being used. This might at first sound like being very much, but keep in mind that this very amp would drive a 4 Ohm load at 2500 Watts !
Regards
Charles |
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