| cathode_leak |
I am messing around with the Crystal CS8412 digital reciever chip, trying to build a decent SPDIF input stage for it and realizes this task is not as trivial as it first appeared to me...
After reading through an informative thread on the subject, I could not help myself from stopping again and again reading through WMS's post at http://www.diyaudio.com/forums/show...27860#post27860. This definitly looks like the way to go, and the 6111 triode idea melted me....:blush: My bet will, I think, be to use the 74HC86 (or VHC) wired as a phase splitter for the digital signal, using a 6111 dual triode pencil tube to amplify both phases into an Aes-EBU transformer...
Now, when using the 6111 tube in place of transistors as WMS suggests, I would have to set it up as cathode follower with coupling capacitors wouldn't I?
Also, Partsconnexion has a Aes-EBU-tranny that might be a good alternate to the Lundahl LL1566 I have, since it appears (judging by it's picture, i have to check this) to have centertap on its primary, wich might be beneficial to connect to ground reference in a balanced scheme?
Could anyone help me get somewhere with this? Any thoughts or ideas? Here is a copy of the circuit MWP suggests, but using transistors...: |
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| Jocko Homo |
Why do you think that you need to amplify it? The output is supposed to be 0.5 V p-p, not 50 V p-p.
Jocko |
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| cathode_leak |
| quote: | Originally posted by Jocko Homo
Why do you think that you need to amplify it? The output is supposed to be 0.5 V p-p, not 50 V p-p.
Jocko |
True, but the output of the 74HC86 OR-gate is hardly 0.5V p-p is it? I'm not an expert on this digital stuff but I had the impression it was much lower.. Are you saying a 74xx86 chip can drive the tranny on it's own? and wouldn't the signal benefit from a buffer (with regards to reflections, etc) even if the buffer provides only minimal gain?
Edit: Also, the CS8412 chip will have no problems handling a higher, say 3V p-p signal (example out of the blue), with it's self-biasing feature? |
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| cathode_leak |
Apparently, Harry have had good experiences using the '86, so I thought it was a somewhat safe and way easier approach than reclocked flipflop or other suggestions i've seen.. Here's what he says;
| quote: | Originally posted by HarryHaller
I have used the 74HC86 as a phase inverter for driving balanced digital out for AES/EBU interfaces. It works real well. Jocko said this circuit was too good to give away for free! |
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| Jocko Homo |
Uh..........the output is CMOS level..............5 V p-p. You need to reduce it, not amplify it.
As for reclocking F-F..........put it in front of the '86, and only use one ouput. Yeah, too good to give away for free, but what the hey............
Don't use the Lundahl. They make good audio transformers, but SPDIF onrs are totally different. I would not use them. Or any designed for AES-SPDIF conversion. Or 2:1 ones, either.
Jocko |
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| cathode_leak |
Thanks for your reply, Jocko.
| quote: | Originally posted by Jocko Homo
Uh..........the output is CMOS level..............5 V p-p. You need to reduce it, not amplify it.
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Aah... I see... Then why would WMS use transistors in his example schem? Reducing voltage can be done purely resistive...?! He uses them to battle impedance transients of the '86 rise fall? could I use a no-gain OPA627 buffer for this purpose? (627s are probably overkill but I have spare chips laying around)
| quote: | As for reclocking F-F..........put it in front of the '86, and only use one ouput. Yeah, too good to give away for free, but what the hey............
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Is there any obvious advantages of reclocking in the input stage instead of say, between the digital reciever and the DAC? pros & cons?
| quote: | | Don't use the Lundahl. They make good audio transformers, but SPDIF onrs are totally different. I would not use them. Or any designed for AES-SPDIF conversion. Or 2:1 ones, either. |
Are you suggesting to use no transformer at all? I do in fact have a pair of very small chip trannys that, AFAIK, are not the "scientific aes/EBU".., 1:1, chinese production marked "PE-65612", "0203-C".. IIRC they were designed for digital signal transmission, would they be the better choice than "standard" Aes/EBU?
Edit: PE-65612 pdf @ http://www.elfa.se/pdf/56/05655055.pdf
edit: edit: BTW they are pulse trannys... |
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| cathode_leak |
| quote: | Originally posted by myself
could I use a no-gain OPA627 buffer for this purpose? |
I just realized it would be a very stupid thing to waste OPA627s in a buffer with no gain..:bigeyes: I'll rather ask wether OPA2134 could be a suitable buffer... got spares of these too... |
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| Jocko Homo |
Yes, he wants to keep the impedance constant, but I bet that he does not have a TDR. I do...........
I never tried adding a follower, but then I have other ways of isolating the driver from the line.
Those cheap Chinese transformers are ok. A cheap version of a Schott, that was good. Lundahl............stick with his audio transformers.
I would not waste a good part of the SPDIF output. It has to work at 2.8 MHz, and pass at least the fifth harmonic.
Still want to use a good audio part there??????
Yes, reclock on the TX side. On the RX side, you need to come up with a seconadary PLL, and use that to get the recovered clock.
(I have a buddy that sells one, but it is not cheap. I use one, but I need a good reference system.)
Jocko |
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| cathode_leak |
| quote: | Originally posted by Jocko Homo
Yes, he wants to keep the impedance constant, but I bet that he does not have a TDR. I do...........
I never tried adding a follower, but then I have other ways of isolating the driver from the line.
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The logic question would be "how", now wouldn't it? And one other thing... I don't have a TDR either I believe.. but I could not be sure because I have no clue what it is. What does it tell you? Measurements are better for your line isolation tricks than for op-buffer? :scratch1:
| quote: |
Those cheap Chinese transformers are ok. A cheap version of a Schott, that was good.
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Good. Then I will work with the chinese trannys for now, and concider upgrading them at a later point.. Thanks for the tips :)
| quote: |
Yes, reclock on the TX side. On the RX side, you need to come up with a seconadary PLL, and use that to get the recovered clock.
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Whow, I'm getting an overdose of digital language ;) Let's assume for a second that my setup will be the reclocked 74 flipflop, into the 86 as digital phase splitter, resistive network, opamp buffer, then the tranny...
Would I feed the 74 on the TX side 2.8MHz, and then 44.1KHz for CS8412 FS output on the RX side? If so, could this be done as simple as using one clock, say 11.289MHz, and use a binary counter or other suitable logic to divide by 4 and 256?
Sorry if I ask very dumb questions here.. New*cough*bee ;) |
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| Cobra2 |
| quote: | Originally posted by cathode_leak
Good. Then I will work with the chinese trannys for now, and concider upgrading them at a later point.. Thanks for the tips :)
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Unless the world has a "back-spin", you will probably not find any better trafo, just as with transports/lasers and dinosaurs...
Arne K |
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| Jocko Homo |
Get rid of the buffer..........
You will use 11.2896 MHz as the clock for the F-F. No dividers/counters needed. Worry about getting the TX side working first. Your guesses on the RX side still need work, so forget about them for now.
TDR= Time Domain Reflectometer.
You can make a crude one with a 'scope............Harry Haller did.
Jocko |
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| cathode_leak |
| quote: | | Worry about getting the TX side working first. Your guesses on the RX side still need work, so forget about them for now. |
Good idea.:up:
| quote: | Get rid of the buffer
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mmkay... but the issues addressed by the buffer.. how will I address them now? Is this a part of your "I have other ways of isolating the driver from the line"-strategy? I'm listening!! :scratch2:
away goes the buffer...
| quote: | | You will use 11.2896 MHz as the clock for the F-F. No dividers/counters needed. |
OK. My stuff is battery powered, so I shouldn't have any jitter problems using a low-jitter XO-1 (to keep things simple)?
Now what..? Will i use a '86 for phase splitting, or should I get rid of it and make the '74 flop take care of this..?
:bfold: |
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| Jocko Homo |
You can not use a F-F to make balanced outputs.
I don't want to have to 'splain this again. Keep the XOR gate.
All the parts are already there. The order may be wrong.
Yes, use a good, clean low-jitter clock.
Jocko |
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| cathode_leak |
| XOR gate as input splitter and flop on each phase? thus the flop also acts as buffer? Or am I talking nonsense? |
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| rfbrw |
| As I understand it, this is the input to a DAC. That being so, what signal do you intend to clock the FF with? |
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| cathode_leak |
Regarding the SPDIF antijitter measures, I've been reading som datasheets and tried to understand the glue logics involved here, and what I've come up with is drawn in the attached schematic. The SPDIF input uses a 86 xor gate wich splits the digital signal into inverted and non-inverted logic signal. These signals are then reclocked in a 74 flipflop, before being tuned down to 0.5Vp-p SPDIF standard for the pulse transformer driven in a balanced setup.. Will it work? any comments? I guess the suggested 11.2896MHz frequency was based on regular 44.1KHz sampling frequency (256Fs)..
Should the flipflop be clocked to 256Fs if switching to 48KHz or 92KHz sampling frequency?
Regarding reclocking of the CS8412, I've set up options for FSYNC clocking at 44.1KHz, 48KHz, and 92KHz. I got the impression that SCK should be clocked at 64Fs, so that is what i've drawn in the scematic.. Sampling frequencies will be jumper programmable I guess...
CS8412 provides three outputs, the DATA, FSYNC, and SCK... PCM1792 recieves I2S on LRCK (pin 4), BCK (pin 6), and DATA (pin 5)....
wich goes where? and should clock the PCM1792 SCK?
| quote: | quote from PCM1792 datasheet
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio
interface. Serial data is clocked into the PCM1792 on the rising edge of BCK. LRCK is the serial audio left/right word
clock.
The PCM1792 requires the synchronization of LRCK and system clock, but does not need a specific phase relation
between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±6 BCK, internal operation is initialized within
1/fS and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock
is completed.
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| quote: | quote from PCM1792 datasheet
PCM Audio Data Formats and Timing
The PCM1792 supports industry-standard audio data formats, including standard right-justified, I2S, and
left-justified. The data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0],
in control register 18. The default data format is 24-bit I2S. All formats require binary 2s complement, MSB-first audio
data. Figure 27 shows a detailed timing diagram for the serial audio interface.
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I would like to be able to switch between 16 and 24 bit operation of the PCM1792, just as I'll be able to select sampling frequencies.. that means as far as I've understood switching the FMT[2:0] bits in control register 18 of the PCM1792, between 100 (16bit I2S) and 101 (24bit I2S)... Ehm.. do I need an MCU here? or can I get away with glue logic?
| quote: | Originally posted by rfbrw
As I understand it, this is the input to a DAC. That being so, what signal do you intend to clock the FF with? |
it will be clocked by the 11.2896MHz clock as far as I've understood.. But as you can read in this post I am not quite sure.. |
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| Jocko Homo |
What good does it do to reclock the incoming data, when it will go out with almost 1 n Sec of jitter, from the PLL????????
Why stick all those XOR gates in there to get differential, then put a transformer after it?
At least you have something between the '8412 and the line. Just the wrong stuff, in the wrong order.
Jocko |
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| cathode_leak |
I realize the '86 was messed up in the 1st schem... I've got to xor signal with +5V to invert, and xor signal with ground for non-inverting...? I'm thinking 1100 xor 1111 = 0011, 1100 xor 0000 = 1100....... right? but Jocko.. can you give me a clear hint on how to do this? will I reclock first, then split, then step down voltage (resistor network), then transformer?
I realize I ask alot of really stupid questions, but this digital stuff is all new to me... I'm really trying to learn.. :( |
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| Jocko Homo |
NO!
Put the reclocker on the TX side, where you already have (or should have), a good, clean clock.
On the RX side, you add a secondary PLL. Some guy who sometimes posts here sells one. (I know from personal experience that it works. Drawback: cost.)
Those chips may not like driving a resistive load................
The simple RX circuits that you can find on the web work ok. The TX ones do not.
Jocko |
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| cathode_leak |
This time the attachment looks more sensible doesn't it? :blush:
| quote: | Originally posted by Jocko Homo
On the RX side, you add a secondary PLL. Some guy who sometimes posts here sells one. (I know from personal experience that it works. Drawback: cost.)
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PLL=Phase-locked loop?
You mean I will use a PLL to reclock the I2S signal lines?? |
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| Jocko Homo |
You are going backwards, bub........
You need 5V to drive those flip-flops.........isn't going to happen with 0.5 V p-p.
Your schematic looks like an output stage, only backwards. It doesn't work that way.
Yes, once you figure out the input, and save up $$$$$, you would stick a secondary PLL on the output of the RX chip. As far away s you are........forget it for now. Just too much stuff to confuse you.
Go look at the cheap SPDIF inputs. They work, the outputs don't.
Jocko |
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| Calimero |
Cathode leak,
I have been reading this thread from the start with a lot of interest, however due to misunderstandings it is on the wrong track and getting humorous.
Your question is about balance SPDIF.
SPDIF is used between a transport, the TX-side, and a DAC the RX-side.
Jocko's advice is:| quote: | | Put the reclocker on the TX side, where you already have (or should have), a good, clean clock. |
The sbalanced SPDIF signal at the TX-side requires XOR-ing. The normal, and XORED-signal are together with GND send to the DAC (That is a balanced connection). You can use pulse-trafo's for isolation and adjusting the 5V to that of the AES/EBU standard
At tha DAC side the balanced signal can be input (via pulse trafo) into the ASRC (a CS8412, 8414), The ASRC used a PLL to split clock and data signals, however the PLL of the poular ASRC (8412, 14) are not good enough for sereous audio purposes, and therefore, Jocko's advice is:| quote: | | On the RX side, you add a secondary PLL. Some guy who sometimes posts here sells one. (I know from personal experience that it works. Drawback: cost.) |
The pulse-trafó's at the TX and RX side help in reducing problems due to impedance mismatches, which are the cause of reflections and thus sound degradation.
I Hope this clears up some mis understandings.
I have a question for the SPDIF-experts and that is:
when you decide to use a 2nd PLL, how much effort do you still have to put in the first PLL (in other words): how good must the signal be that is input in the second PLL, to let it pay of the extra costs).
Henk |
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| cathode_leak |
Jocko,
Just an observation.. It looks like the AD8561 comparator ("ultrafast", 7ns propagation delay) could be utilized to produce CMOS logic signal from SPDIF.. According to Elso Kwak it needs only a few mV above zero to give a high output state..
'cause I would have to step up the signal to 5Vp-p in order to utilize CMOS logic like 74 or 86 if I understand you correctly?
And I will have to step down signal to SPDIF standard (0.5Vp-p) before feeding the pulse tranny...? Resistors is the only way I can think of doing this... |
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| cathode_leak |
Thanks for your feedback, Henk.
| quote: | Originally posted by Calimero
The sbalanced SPDIF signal at the TX-side requires XOR-ing. The normal, and XORED-signal are together with GND send to the DAC (That is a balanced connection).
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Can you tell me wether the '86 attached is correctly setup for this purpose?
| quote: | Originally posted by Calimero
You can use pulse-trafo's for isolation and adjusting the 5V to that of the AES/EBU standard |
Adjusting the CMOS 5V to the CS8412 inpust using the pulse-tranny will require adding a resistor network, right? |
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| Jocko Homo |
Transformers do not reduce jitter due to reflections. In most cases, they increase reflections. There is that little matter of leakage inductance to take into account.
Leave the comedy to the experts.
I do not like comparators, Elso does. Elso claims that it needs diodes to keep from frying the inputs. Adding diodes increases reflections.
You can get balanced with just with a transformer. Isolate the '841x from the transformer. Think buffer/inverter.
Jocko |
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| cathode_leak |
| quote: | Originally posted by Jocko Homo
You can get balanced with just with a transformer. Isolate the '841x from the transformer. Think buffer/inverter.
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With gain in the buffer then, to get CMOS voltage for the inverter? |
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| cathode_leak |
| One possible implementation of TX reclocking? |
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| Jocko Homo |
Why 2 flip-flops????
On the RX side................if you use an unbuffered one, it can do both functions.
Jocko |
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| cathode_leak |
| quote: | Originally posted by Jocko Homo
Why 2 flip-flops????
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That is a d**n good question. I'm not yet on wavelength with the basics of flipflops.. I've seen them wired like that in I2S reclock circuits so I figured it was the way to go.. It should be a single flop then, like attached?
| quote: | Originally posted by Jocko Homo
On the RX side................if you use an unbuffered one, it can do both functions.
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A unbuffered 74? That would mean... 74HCU74? both functions? reclocking and... ...... ?
In the attached schematic I added the transformer to the 86 outputs directly, and an resistor across secondary windings.. Am I on the right track? |
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| Jocko Homo |
Get rid of the reclocker on the input.
Put the transformer on the input.
Jocko |
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| cathode_leak |
| Thanx for your helpfulness, Jocko, but I'll leave clocking out of the TX side and run balanced without reclocking, but i'll figure out somethin' for reclocking of the I2S lines on the RX side.. I'll start a new DAC thread shortly, but no TX reclocking for me yet... Maybe in the future though.. But thanx again for keeping up with my stupid nonsense.. I need to learn more about this stuff before I attempt to put this thread into a working shematic :( |
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| cathode_leak |
| Just one last suggestion that suddenly seemed obvious... could this possibly be closer to your secret, Jocko? |
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| Elso Kwak |
| quote: | Originally posted by Jocko Homo
Transformers do not reduce jitter due to reflections. In most cases, they increase reflections. There is that little matter of leakage inductance to take into account.
Leave the comedy to the experts.
I do not like comparators, Elso does. Elso claims that it needs diodes to keep from frying the inputs. Adding diodes increases reflections.
You can get balanced with just with a transformer. Isolate the '841x from the transformer. Think buffer/inverter.
Jocko |
Hi Jocko,
I feel sad the SPDIF is so badly understood even by maufacturers. I am not going to point again at that chapter of Horowitz explaining the tranmission line as it should be....
No doubt you have built the best Interface. Too bad I can't have it......But put me on your list.
Oh yes, comparators like I use blow up with more than 3V on the input. SPDIF is a 0.5 V p-p so the signal will do no harm. Must be static........
Attached a picture of my most wanted item!:cool: |
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| Elso Kwak |
| And the flipside: |
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| Eric_R |
| quote: | Originally posted by cathode_leak
In the attached schematic I added the transformer to the 86 outputs directly, and an resistor across secondary windings.. Am I on the right track? |
At the output of the flipflop you have your balanced outputs so the XOR gates are not needed. But the transformer does the balancing anyway so you could drive the trafo with ground on one pin. The only difference from balanced drive of the transformer is that you have half the signal level on the output. |
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| Jocko Homo |
And it still is backwards.
I don't want to have to 'splain it again.
No, Elso, you can not have one. Only 3 were made. I don't even have one.
One is in Norway already. Maybe someone should drive over to where ever and copy it.
Jocko |
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| Elso Kwak |
| quote: | Originally posted by Jocko Homo
And it still is backwards.
I don't want to have to 'splain it again.
No, Elso, you can not have one. Only 3 were made. I don't even have one.
One is in Norway already. Maybe someone should drive over to where ever and copy it.
Jocko |
Jocko,
How can I seduce you to make some more????
I am not the kind of guy copying someones intellectual property......
:confused: |
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| Jocko Homo |
"All You Need Is Cash".
Actually, I need it more than they do. Find a bunch of guys who want one.......start a thread on a forum that I read more often, and bribe me.
Jocko |
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| Elso Kwak |
| quote: | Originally posted by Jocko Homo
"All You Need Is Cash".
Actually, I need it more than they do. Find a bunch of guys who want one.......start a thread on a forum that I read more often, and bribe me.
Jocko |
Jocko, You did not say the magic word on this forum. Can you say groupbuy?
:clown: |
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| cathode_leak |
| quote: | Originally posted by Elso Kwak
Can you say groupbuy?
:clown: |
I'm definitly in on that one :nod:
would also love to see a closeup of those 5-pin SOT23 packaged chips on the picture :D |
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| Cobra2 |
Rx board (this is as close as you get!)
Arne K |
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| Cobra2 |
Magic DAC !
Jocko's creation...in new clothes.
Arne K |
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| cathode_leak |
| quote: | Originally posted by Cobra2
Rx board (this is as close as you get!)
Arne K |
CLOSER!!! :D
I know people in Stavanger.. If you thought NOKAS was well thought out, wait till you see those camouflage-colored drwafs hanging from the roof with big-lens nightvision thermal x-ray spy-cameras!! They will bring me your secret!! :D |
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| cathode_leak |
| quote: | Originally posted by Cobra2
Magic DAC !
Jocko's creation...in new clothes.
Arne K |
Brrr.. What are these for ;) |
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| Cobra2 |
Just balanced out conversion, by special order, for a friend.
Arne K |
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| Jocko Homo |
Jocko's creation..........circa 1992, with balanced outputs added, a secondary PLL, and something that adds 24-bits. Only because the original 20-bit DACs are no longer around, and I did not want someone halfway around the world to be stuck with something that could not be fixed if lightning got hold of it.
Yes.......it has the infamous I/V circuit.
Jocko |
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| Jocko Homo |
Allegedly run as a non-profit enterprise. Nope, I am only in it for the money, so $$$$$$. Don't expect any quantity discounts, either.
Don't make me post the cover of that Mothers of Invention album cover.
Again.
Jocko |
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| Elso Kwak |
| quote: | Originally posted by Jocko Homo
Allegedly run as a non-profit enterprise. Nope, I am only in it for the money, so $$$$$$. Don't expect any quantity discounts, either.
Don't make me post the cover of that Mothers of Invention album cover.
Again.
Jocko |
Jocko, You should have emphasis on allegedly......
Love to see that cover of MOI.
:clown: |
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| Jocko Homo |
But I could no find the thread that I posted it in. (Actually, I probably have done it more than once.) So for all the newbies..........when you want to know what ticks inside of my head................and why my memory is kaput-ski........it comes form listening to this **** when I am designing electronics:
(Don't tell my customers!)
Jocko |
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| vuki |
| Jocko's rx circuit looks like xformer (+compensation) > bjt diff pair > 2x unbuffered inverters , PS is LED referenced emitter follower :scratch2: |
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| moamps |
| Now, who's a full-time reverse engineer around here, you or I? :D |
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| Jocko Homo |
I guess that no one needs me around here.
I'll let you 'splain all this **** to the newbies next time.
Just wait until someone askes you about that compensation...............
Jocko |
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| moamps |
| quote: | | Just wait until someone askes you about that compensation............... |
I'll tell you right now, that boy learns real quick... :D |
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| vuki |
| quote: | Originally posted by moamps
Now, who's a full-time reverse engineer around here, you or I? :D |
My humble apologies, Mr. RE master! :angel:
| quote: | Originally posted by Jocko Homo
Just wait until someone askes you about that compensation...............
Jocko |
What compensation? :clown: |
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