| PatPet |
Hello,
After getting a few of these DAC chips in hand, now I decide to start the work.
Firstly, I'm going to use stripboard for the whole DAC. The reason is I lack experience in designing a pcb for this. I heard from somewhere that the cables/tracks carrying digital signals shall be kept short and thin, preventing noise pickups. I shall be eager to know if this is the case.
And right here is the draft of the structure of the DAC
1) signal selection, between AES/EBU XLR and SPDIF RCA
2) CS8414, DIP packaged
3) PLL reclocking, with Kwak clock
4) AD1865N-K, parallel or not to be tested and decided by my ears, balanced current output
5) Pass D1 I/V stage
flames or comments are welcomed |
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| Peter Daniel |
| quote: | Originally posted by PatPet
1) signal selection, between AES/EBU XLR and SPDIF RCA
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I don't know how you plan on that, but I would suggest using Scientific Conversion input transformer with separate primaries that were specifically made for both inputs. This allows you the implementation without any additional switching circuitry (you might ground unused input maybe).
I just got those yesterday and they sound pretty good too.
http://www.scientificonversion.com/dualZo.html |
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| erozsolt |
Kwak:
I don't really know the digital part of the DAC-s, but from my knowladge, the best NON-OS DAC-s use no jitter correction and reclocking, using a very simple receiver -> DAC signalpath.
I asked sometime at head-fi that how could I build myself a good NON-OS DAC designed for computer-as-a-source listening. The special about computer's soundcards is that they can use external sync signal - unlike CD transports, where they have to "lock-on" to the drive's continous dataflow.
Here is a quote from Glassman repleying to my question:
| quote: | | if you're building your own DAC, the best thing you can do is to use some low jitter oscillator like Tent Clock or Kwak Clock inside your DAC and running S/PDIF output from your DAC to the card's digital input and letting the card synchronise to the incomming clock, that way you end up with absolutely jitter-free transmission and you can use any card with s/pdif in and out which has the capability to lock on external clock (pretty much every serious card).. |
So, does it meen reclocking? I think it is just a precise clock inside the DAC, and a clean signalpath between the receiver and the DAC chip. |
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| PatPet |
| quote: | | I don't know how you plan on that, but I would suggest using Scientific Conversion input transformer with separate primaries that were specifically made for both inputs. This allows you the implementation without any additional switching circuitry (you might ground unused input maybe). |
How much do they cost?
I have some low-signal Omron relays in my box. If they are too expensive, I think I shall pick the relays. |
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| PatPet |
| quote: | http://www.ptsoundlab.com/secnumeri...dac1865/dac.jpg
It is the digital part of an Autio Note DAC (the digital part is same for all of them).
The whole DIY guide can be found here (page is sometimes buggy).
http://www.ptsoundlab.com/secnumeri...zeroad1865n.htm |
Why do I see no sentences or words describing the circuit?:D
Any, the schematics are very useful. Thank you. |
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| PatPet |
And one more thing is that, for the digital signal cables connecting the board and the RCA/XLR connectors, is it absolutely to ensure they are short, or even thin?
What are the tolerences, if anyone has experience on this. |
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| Peter Daniel |
| quote: | Originally posted by PatPet
How much do they cost?
I have some low-signal Omron relays in my box. If they are too expensive, I think I shall pick the relays. |
They are $15/pc. The advantage here is not only source selecting, but also improved interface, whith improved sonics. |
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| philbyx |
Hello
I'm planing too on a dac based on ad1865k-n (I have two of them), receiver cs8414 (I have two also, thank you Panda99).
I 'm thinking about digital part for the moment :
Transformer : why not a ethernet 10base5 transceiver transformer ?
Reclocking : all the reclocking I saw for the moment are reclocking bclk. In the case of the 1865, the important signal is the Latch on each chanel : LR, LL.
18 last bits of sdata, shifted by bclk in the register, go on the output and give the current when latch LR or LL goes low.
We can connect directly fsync on LR and fsync inverted on LL if the receiver cs8414 is in 18 bits mode lsb justified (mode 6). Realignement with shift registers in not necessary (it is necessary if I2S or msb justified).
Sdata goes directly on data left and data right (perhaps I will make balanced with two dac by chanel, sdata on one, sdata inverted on the other, 2's complement permits it...), bclk go to clk.
This is without reclocking.
If we want to reclock (anti jitter), we have to do it on LL and LE.
We have to make a super clock (in my case, a 33.8 Mhz, to send to my asus520 (the drive, for me) which have a poor ceramic oscillator on the MT1199 chip).
From this super stable clock, I will make a 2.88 Mhz Bclk which will clock D flip flop with fsync from the cs8414 on D to have a super LL and LR latches signal on Q and Qbar.
This is my project, and I wait for your advices...;)
Philippe |
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| PatPet |
Hello Philbyx,
Okay, maybe I shall briefly explain the details of the digital part in my project.
Balanced mode is done as shown in the schematic below
The logic is done on the DATA line if I did not make a mistake.
And the PLL filter is done on CLK, or SCK
And for your reclocking plans, I'm afraid I encounter problems understanding. Maybe could I have some pictures or schematics of them, to make it clear?
:bawling: |
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| Wodgy |
| quote: | Originally posted by Peter Daniel
They are $15/pc. The advantage here is not only source selecting, but also improved interface, whith improved sonics. |
Where did you buy them? I thought the Scientific Conversion parts were in the neighborhood of $40/pc. At $15/pc they're pretty much a must. |
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| Peter Daniel |
| A forum member (Algar_emi) bought them for me (I believe directly from them) and that's how much I paid. The model I'm using is SC939-06 . |
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| Jocko Homo |
HA! HA! HA! HA!
So they say. Snicker.
What is wrong with this picture?
(I'll let you guys argue about it for a while.........can anyone say reflections?)
Jocko |
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| Elso Kwak |
| quote: | Originally posted by Jocko Homo
HA! HA! HA! HA!
So they say. Snicker.
What is wrong with this picture?
(I'll let you guys argue about it for a while.........can anyone say reflections?)
Jocko |
Jocko, After some reflection I decided not to use them........(funny picture BTW). Is everybody funny here?
:clown: |
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| Peter Daniel |
| quote: | | What is wrong with this picture? |
XLR pin 1 is in a wrong spot. Beside the lack of coupling cap, this picture is pretty much consistant with CS8414 datasheet.
Another thing that supposedly should be an improvement is not connecting the shield to the outer connector (XLR) and tying it only to the ground pin. Leaving the shield floating around the pins creates noise, that's why many balance connectors have the outer connector shell removed for best sound. |
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| Peter Daniel |
| quote: | Originally posted by Jocko Homo
Stick with the Schott ones. Even the morons at Crystal/Cypress recommend them.
But for the wrong reason. Idiots.
Jocko |
I tried Schott available from Digi-Key couple years ago. To my ears, the Scientific Conversion transformer sounds better. But only the recent one, the ones made 8 years ago or so (and sold by Parts Connection at a time) sounded indeed like ****. |
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| Tuliman |
PatPet, can you please "share" the hole project, schematics, details....
Thank you
mosfet#myx.net |
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| philbyx |
Hello
I will also share all the project if you want.
A little more about it :
I have a cdrom drive (asus520d quiettrack). Its clock is 33.8 mhz .
I have a cdrom controller card from Rockna-line.
I want to make a super clock for the drive and for a dac I will build, based on ad1865 and cs8414.
This clock will generate 33.8 mhz obviously, but also Bclk (64*44.1k) to reclock fsync, before the ad1865. (I will post a scheme later)
I made some photos this afternoon :
This is the 33.8 mhz clock of the cd-drive (poor low range ceramic oscillator) and the bit clock after the cs 8412 of the dac in the box that I use for the moment to experiment...
Philippe |
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| PatPet |
Hello Tuliman,
I'm pleased to do so. Expect it in a week. I'm having the exam.:D |
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| PatPet |
The schematic is right here. I'm still looking for bugs. Maybe there are some I can't find. But I have checked this for several times. Wrong connection should be eliminated. But other problems I dont know still exists.
I got a guy to help me with PCB laying out. So if the PCB is made successfully. Boards will be available too. (He would make an order of great quantity, thus making it possible to reduce price of each board. |
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