| wimms |
Hello. For quite some time I've been tossing around idea of analog linear interpolation during the DAC IV stage. So I hope to get your comments to this very idea. Note that I haven't built any such thing. I have only simulated results. But they look interesting.
Linear analog interpolation - putting slew rate limiting to good use.
Normal DAC outputs step current that is then feeded into IV conversion circuit that produces step Voltage proportional to PCM sample values. This step voltage is then filtered to remove garbage inherent to the steps. The steps themselves offer very difficult signal for linear circuits.
What is proposed here is method of implementing DAC with linear interpolation in analog domain which effectively completely limits the slew rate of the signal to easily manageable levels.
To grasp the approach consider how linearily interpolated samples are calculated - interpolated sample is average of two subsequent real samples, exactly halfway on the time axis. If you continue adding interpolated values between newly calculated values, you get straight line between real sample values.
That straight line can be represented as slew rate (Volts/sec) required to reach next real sample value after finite sampling interval expires. In essence, stream of PCM data can be easily converted into list of slew rate values that alternate in sign and value at each sampling interval.
Now, constant current source feeding into capacitor will produce monotonously increasing voltage on the capacitor, and basically slew rate of that voltage is proportional to applied current. Given any capacitor value, stream of slew rate values converted into proportional current when applied to capacitor will produce signal that exactly corresponds to PCM sample values with infinite number of linearily interpolated intermediate values. see dac77.gif
To produce suitable stream of current values to be applied to IV capacitor, it is required during each sampling interval to produce current that is proportional to difference between recent sample and previous sample. Then, such delta current is proportional to the required slew rate and signal on capacitor linearily approaches analog value of the next PCM sample at time instant of next sampling interval.
The easiest way to generate suitable delta current stream is to use 2 channels of a stereo DAC with current outputs, and delay input PCM data for 1 sample interval before feeding second channel of this DAC. Then, difference of outputs of the 2 channels will be delta current and our slew rate stream. The 2 outputs can be substracted, (e.g. by connecting out- with out+ of other channel), and the resultant delta current fed into IV capacitor.
Voltage on the IV capactitor will be precisely proportional to PCM data at infinitesimal instants between consecutive samples, but instead of steps there would be linear voltage increase between sample values. Amplitude of the resultant output voltage will be dependant on capacitor absolute value, larger capacitor will produce lower amplitude output, by means of limiting maximum possible slew rate between sampling intervals. see dac6.gif
Benefits of such DAC IV conversion.
1 - maximum possible slew rate of the IV output is best controlled, no matter what PCM input.
2 - there is effectively infinite number of interpolated intermediate samples - like infinite OS.
3 - output of such IV is easy signal to filtering and amplification.
4 - step signal is replaced by triangular signal which contains less harmonics than rectangular signal, these harmonics have less energy and roll off faster.
5 - for PCM signals approaching lower frequency limit triangular signal is increasingly approaching exact representation of the analog sinewave with very little upper harmonics. For e.g. sinewave with frequency FS/20 has inband harmonics below -130db and aliases -60db before any filtering.
6 - aliasing harmonics are more than 20db below what step signal produces - ie. simpler filter.
7 - impulse response is as ideal as it can get.
8 - IV converter settling time is a moot - there is NO settling time of IV as such, its a linear system.
9 - settling time errors of DAC do not cause voltage spikes - they are limited by max slew rate on IV capacitor.
10 - Coupled with DSP sinc interpolation and oversampling, could allow DAC without antialiasing filter at all.
11 - most nonlinearity is located at sinewave peaks. Region of zero transit is most linear.
Downsides.
1 - there is inherent roll off of about 4-6db at highest inband frequencies due to output signal approaching pure triangular wave and that contains less area (energy) than step signal has.
2 - linear interpolation is academically unable to precisely reconstruct original sinewave if compared to hypothetical ideal brickwall filter applied to step signal. There is unavoidable error signal present, and it increases in magnitude with increasing inband frequency. This manifests as roll off in higher band and as harmonics beyond signal band. Basically difference between linear and sinc interpolation. But sonics of this is unknown. I personally think linearity of lower band is more important.
3 - output voltage is floating. As this is basically delta modulation, output signal zero is not strictly fixed, but depends on previous PCM data. This can be a problem, as asymetrically clipped PCM signal can cause DC output buildup. DC can be filtered out, main issue is with IV capacitor which drifts towards power rails. Some sort of soft DC servo seems unavoidable here.
4 - very sensitive to jitter.
what else? |
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| wimms |
| dac6.gif referenced above. Notice how difficult it is to distinguish original sinewave from interpolated signal. |
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| wimms |
Spectrum of simulated DAC with comparison to normal step output.
dac1 is step signal, IV-out is triangular output. |
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| ojg |
This is one of the most innovative ideas I've seen on this forum in a long time! Lot's of outside-the-box thinking here!
I think downsides 1 and 2 are not as bad as it seems. They only apply if you use non-os dac's, and even then it is not worse than regular non-os dac.
Downside 4 needs some explanation, why is this worse than normal dac wrt. jitter?
Additionally it has the same downside as using a resistor for I/V in that you will not have a virtual ground at the dac output.
The delay can be implemented with a fifo-chip like TI 74ALC2226, a cpld or a bunch of 8-bit registers.
Did you have a specific dac-chip in mind? Also a conceptual schematic would be informative :)
Keep up the good work! |
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| Jocko Homo |
| quote: | What is proposed here is method of implementing DAC with linear interpolation in analog domain which effectively completely limits the slew rate of the signal to easily manageable levels.
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Hate to be a PITA, but..........
I haven't seen where slew rate is anything but manageable levels. The problems with op-amps as an I/V is most likely not from slew rate limitations.
Jocko |
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| Circlotron |
| quote: | Originally posted by wimms
The easiest way to generate suitable delta current stream is to use 2 channels of a stereo DAC with current outputs, and delay input PCM data for 1 sample interval before feeding second channel of this DAC. Then, difference of outputs of the 2 channels will be delta current and our slew rate stream. The 2 outputs can be substracted, (e.g. by connecting out- with out+ of other channel), and the resultant delta current fed into IV capacitor. |
How about if you just shove the stepped samples from a single DAC into an opamp integrator? If the DAC is a current output type the opamp can function as the I to V stage as well. :angel:
Edit -> Just had a think about this; my idea is not the same thing at all but I understand *exactly* what you are aiming for. Gotta think some more about this... |
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| wimms |
| quote: | Originally posted by ojg
Downside 4 needs some explanation, why is this worse than normal dac wrt. jitter?
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When step DAC instantaneous jitter causes full sample-time error (just imagine one extreme), then max error is not directly amplitude error, but appears only after filtering. When delta current misses full sample, amplitude can swing fully peak-to-peak. Thats notable difference. Thats how I understand it.
Amplitude errors of step DAC are constrained by absolute levels of DAC output, while in delta mode these errors can cumulate without limits.
Virtual ground can be maintained if low input impedance current amp is used.| quote: | Originally posted by Jocko Homo
I haven't seen where slew rate is anything but manageable levels. The problems with op-amps as an I/V is most likely not from slew rate limitations. |
Jocko, op-amps or their abilities was not my concern, especially not as an I/V. Central idea is linear interpolation. Mainly because its doable. Now my only concern is if its useful. And, in relative terms, its easier signal to anything after IV.
Circlotron, one of points in doing it so is the relative simplicity of current summing, its almost passive nature. Integrator on normal DAC will not get you there. But you could generate delta current PCM data in DSP (e.g. PC) and then feed integrator. Well, it would be pretty much multibit DSD then. |
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| alvaius |
You stated a potential implementation as two DACS slightly out of step in time (1 sample). Would not gain differences and other non-linearities between the DACS make this impossible from an implementation standpoint. With sigma-delta DACs you will at least get good low level linearity, however, if you use a linear PCM DAC, the bit - bit differences between the two DACS would negate the advantages I would expect. What I foresee is a loss of low level linearity and resolution.
I have to give some thought to that 4-6db roll off. When I was thinking of what you were saying, it sounded like you would essentially be implementing a first order filter (mathematically speaking).
Interesting though.. would be interesting to see how the implementation comes.
Alvaius |
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| Circlotron |
Righto then, here we go! This will enable anyone to relatively easily try out the idea.
1/ Get a *mono* wav file of whatever you want to listen to.
2/ Open it with CoolEdit and save it as an ASCII txt file.
3/ Process this txt file with the attached "difrence.exe" file
4/ Load the resulting txt file with CoolEdit and save as a wav file.
5/ Use this wav file to burn a normal audio CD.
6/ The voltage samples from your DAC are now the *difference* values of adjacent samples - Use these samples to drive a plain old op-amp integrator. The integrator output will be "join-the-dots" provided a suitable R&C value is chosen.
The DC gain of the integrator will have to be rolled off though otherwise it's output will eventually drift over to one rail or the other.
Example of CoolEdit txt audio file below:
SAMPLES: 455346
BITSPERSAMPLE: 16
CHANNELS: 1
SAMPLERATE: 22050
NORMALIZED: FALSE
954
-164
-681
-111
1147
2295
2542
2540
2892
3544
3990
etc etc
Have fun!
P.S. the difrence.exe file has to do a lot of work so it is a little slow; start with a small file first! |
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| Bernhard |
| quote: | Originally posted by alvaius
however, if you use a linear PCM DAC, the bit - bit differences between the two DACS would negate the advantages I would expect. What I foresee is a loss of low level linearity and resolution.
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Because nonlinearities are random, hopefully things get better.
I will try 4 x TDA1541 and 2 x 10 x PCM56 soon. |
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| rfbrw |
| quote: | Originally posted by Bernhard
Because nonlinearities are random, hopefully things get better.
I will try 4 x TDA1541 and 2 x 10 x PCM56 soon. |
In what configuration? |
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| Bernhard |
| quote: | Originally posted by rfbrw
In what configuration? |
with CS8412 and SM5813 just parallel. |
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| rfbrw |
| quote: | Originally posted by Bernhard
with CS8412 and SM5813 just parallel. |
SM5813 to TDA1541. ummmmmmmmmmmmm |
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| Bernhard |
Ok, ok, SAA7220 and TDA1541.
Can I connect both SAA7220 and SM5813 to CS8412 at the same time or better use dip switches ? Or resistors to each chip ? Or buffer with 74HCmos ? |
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| rfbrw |
| It is possible with some logic. If I was doing the same thing I would use programmable logic. That way I could run the SAA7220P and the SM5813 simultaneously and switch between the two. |
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| Bernhard |
| I mean electrically, is it a problem for the CS8412 that each output drives two inputs ? Not run both chips at the same time. |
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| rfbrw |
| The '8412 will drive two inputs but as the two filters require different data formats one filter will be producing rubbish while the other is working properly. |
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| Bernhard |
| Thats what I need :D |
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| guido |
Back to the post:
thought of this long ago too. Why? because i read a folder about the harman/kardon RLS players:
Quote:
RLS process: injecting a preview of the dig audio signal ahead of the main signal. A blending device called an integrating comparator superimposes the first advanced signal over the second one, resulting in a smoothing of the stepped dig signal.
In effect RLS connects the stairs represented by the data points of each bit of dig music... Technally speaking, RLS is making a lin interpolation between two consecutive samples....
end Quote
They use a onepole low pass with -3dB @ 88kHz, discrete analog outputs with low neg feedback. Convertors are PCM61P, four of them, 8x oversampling. HD7725,7625,7527 are the types, from 1993. Remember the mags found them a bit 'soft'.
Now how to 'translate' the above into a schematic? The above text implies the use of an integrator, but then why 2 dacs/channel?
Interesting to continue here, happen to have a dac with two current dacs with one dac 1 sample after the other (45xx 64bit shift register). Now using i/v resistors and a transformer to add them up (~2xOS). Would not mind experimenting a bit. |
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| rfbrw |
wimms,
If you are proposing linear interpolation,then for a stream of samples A,B,C,D, you produce an output stream such that the output is A, (A+B)/2, B, (B+C)/2, C, (C+D)/2, D and you end up with twice the number of samples you started with. You can either sum these digitally, in which case the dac needs to work twice as fast and needs a greater wordlength or you can use two dacs working alternately with the outputs summed. Nothing unusual here and this has been done before all the way up to 64 dacs in parallel but there is no easing of the slew rate requirements.
However the gist of your post suggests something more akin to a one-bit dac but you refer to a difference between a sample and a delayed version of its self and in that case there can be no difference.
So what exactly are you proposing? |
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| wimms |
rfbrw,
Think in terms of currents here. Your list of ABCD inherently assumes absolute voltage levels, which is not what its all about.
There is output A(x) on DAC1 and A(x-1) on DAC2, concurrently, always. Only 2 samples at a time. Currents are easy to substract. Result is single current that is proportional to difference between two last samples. In your example, that would be A-B, B-C, C-D, etc.
If such delta current is applied to IV Cap, exactly the waveform results that connects instants of DAC output change as if infinite linear interpolation has been done.
http://www.diyaudio.com/forums/atta...tamp=1097849833
Its a difference between blue DAC output and green delta-current output (IV-out plot). To generate such linear signal, not a single filtering stage is needed or digital filtering, only 2 DACs with delayed data on one.
The IV Cap is slew rate limiter. It must be dimensioned so that to get say 1V AC output from the DAC, slew rate on the Cap must not exceed 1V/sample for change from 0 to 64K of 16-bit sample. In essence, thats slew rate limit of 1V/22us for 44.1K audio. Thats pretty hard, but its nothing compared to 200ns settling time of DACs. And thats absolute extreme case, for lower freqeuency or lower amplitude content, slew rate on the Cap will be lower, naturally, as a result of DAC delta-current charging the Cap.
Thus, anything beyond that IV Cap is seeing slew rate limited signal to deal with.
Guido, thanks for quote. So its not new idea. I have also seen some hints on similar approach from Onkyo, but not any DIY. Why I wonder. |
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| janneman |
Wimms,
I like your idea, but I don't understand why the second delayed signal is necessary. One the one hand, once you know how to do the integrating, a 'normal' DAC output step into an integrator will give exactly the result you want. On the other hand, using the delayed signal, IIUC, you take the difference of two steps, which in itself is again a step. It's the integrating action that is the core of your idea IMHO.
Jan Didden |
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| rfbrw |
| quote: | Originally posted by wimms
<snip>
There is output A(x) on DAC1 and A(x-1) on DAC2, concurrently, always. Only 2 samples at a time. Currents are easy to substract. Result is single current that is proportional to difference between two last samples. In your example, that would be A-B, B-C, C-D, etc.
<snip>
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I see absolutely no point to this. |
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| Circlotron |
| quote: | Originally posted by janneman
One the one hand, once you know how to do the integrating, a 'normal' DAC output step into an integrator will give exactly the result you want. |
Hi Jan.
I thought this way at first too. Consider what happens though when your DAC outputs a whole line of more-or-less equal samples such as the flat top of a low frequency square wave. Feed this straight into an integrator and it will ramp up *continually* for the duration of that flat top at a rate depending on the voltage coming out of the DAC at that moment.
With the difference-of-2-DACs setup, the difference (i.e. the variation) between subsequent samples of the flat-top waveform is basically zero so the integrator gets fed zero volts and therefore holds it's output at a constant voltage, a.k.a. flat-top waveform.
Try my software in an earlier post and see! |
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| janneman |
Isn't this the same as a single-bit DAC where the bit only toggles if there is a change to the previous value? Anyway, the idea doesn't improve on the regular I/V integrator with regards to filtering the steps, IMHO.
Jan Didden |
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| OliFilth |
Two points that concern me with the original idea:
1. You are basically differentiating (in the discrete domain) and then re-integrating (in the continuous domain) the signal. As the original poster's Point 3 suggested, this will inevitably lead to D.C. drift.
2. What advantage could this have over oversampling with a low-pass digital filter acting as an interpolator? Whereas the "traditional" oversampling filter method leads to a flat frequency/phase-response, this linear interpolation idea does not, and in fact introduces non-linearities from a transfer-function/s-domain point of view (i.e. the transfer function will depend on the values of your consecutive samples). In this respect, it behaves worse than a non-oversampling "stair-case" DAC, which will at least have a linear transfer-function. |
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| wimms |
janneman,
If you integrate output of normal DAC, you won't get the same thing. You could achieve almost the same result IF before feeding normal DAC you translated PCM into delta stream computationally. It is important to integrate delta-current, not absolute currents. Then you would need to change your normal DAC IV stage to integrator. Normal alias filter would fit then beyond that.
Linear interpolation occurs only if you integrate between steady states for the whole duration of sampling interval. There are only few ways to do that, all involve "memory" of the previous sample for the duration of integration.
The remaining considerations, perhaps arguable, are related to other things, not fundamental to the idea. Of course imo.
Because outputs of both DACs change simultaneously, some nonlinearities are canceled. It's utilizing similarity of channels as a matched pair. DAC transients are heavily damped. DC drift due to nonlinearity of DACs is canceled.
Integrator is purely passive device - Capacitor. No feedback. No opamp is needed at this stage. Thus linearity of IV stage is defined purely by DAC output linearity and Capacitor properties. Nothing else.
It's the linear interpolation with only passive devices that is the core of the idea.
I don't think second DAC channel is _necessary_, single DAC would be even easier for testing with PC, but I thought that it would be pain to construct delta-PCM computationally in a standalone DAC expecting normal PCM data input. The use of 2 channels is simply a straight forward method of getting delta-current.
Settling time of normal DAC can cause voltage oscillations. In delta mode, it is converted into slew-rate variations, basically damping high frequency transients very efficiently without upsetting circuitry beyond. When going to higher DAC sampling rates, settling can take quite a large proportion of whole sample interval, thus digital interpolation has some limit in its usefulness.
WRT essentially implementing first order filter, raised by Alvaius - any type of interpolation is essentially some kind of filter. Yes, this DAC would have property of lowpass filter, but its not as simple as ordinary lowpass with some fixed cutoff frequency. I'm in trouble classifying it. Its behaviour is different with discrete-time input vs linear input signal it seems. It allows instantaneous change of slew rate (and thus signal, implying infinite bandwidth) yet strictly limits the slew rate itself. With linear input it looks like first order filter with cutoff frequency of 0. Its the interaction of fixed sampling interval (Fs) and the integrator that makes the difference. If you take output peak swing for output magnitude, then such discrete interpolation has cutoff at Fs/2. Reason why sinusoidal output has lower cutoff is caused purely by signal shape approaching triangle when approaching Fs/2. That is best avoided by digital filtering and OS.
Of course, all these are just my thoughts, not necessarily correct.
I have played with this idea simulating in LTSpice. Since posting graphs in my first message I tried to tidy up DAC emulation, but can't get it perfect. At least you can get a rough view how it is simulated, in attach. DAC part isn't precise there, so be careful when making conclusions.
| quote: | | I see absolutely no point to this. - rfbrw |
rfbrw, how can I help you? If you integrate normal step signal, you would not get linear interpolation. What is done is done to achieve _linear_ interpolation. |
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| wimms |
| quote: | Originally posted by OliFilth
Two points that concern me with the original idea:
1. You are basically differentiating (in the discrete domain) and then re-integrating (in the continuous domain) the signal. As the original poster's Point 3 suggested, this will inevitably lead to D.C. drift.
2. What advantage could this have over oversampling with a low-pass digital filter acting as an interpolator? Whereas the "traditional" oversampling filter method leads to a flat frequency/phase-response, this linear interpolation idea does not, and in fact introduces non-linearities from a transfer-function/s-domain point of view (i.e. the transfer function will depend on the values of your consecutive samples). In this respect, it behaves worse than a non-oversampling "stair-case" DAC, which will at least have a linear transfer-function. |
OliFilth, thanks for your comments.
1. This is one reason for using 2 matched DAC channels. DC drift due to DAC nonlinearities cancels out largely. Static DC offset can be biased out. The remaining signal modulated DC drift is quite similar to that with normal DAC. But yes, this is valid concern and would need more attention, or just different thinking.
2. This is not meant as substitute for digital filtering. The main advantage, in its core, is that this way interpolated signal has less spectral content than step DAC before any analog filtering. It works best when sampling rate is at least 4 times highest band frequency, which asks for digital oversampling.
WRT to your comments to transfer function, I'm not sure you are correct in frequency-phase response, and I would love to hear you elaborate your thoughts on non-linearities in transfer function/s-domain. This is area I could use some help.
janneman,
This is not exactly the same as a single-bit DAC, which is 1-bit DSD. But it has strong similarities. It is multibit DSD that allows lower bitrate at the expense of higher DAC resolution. |
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| OliFilth |
Wimms, I assumed you were proposing your method as an alternative to digital oversampling/interpolation. Now I understand that you intend to implement it in addition to oversampling, in which case my point regarding flat frequency/phase-response is no longer valid.
However, with regards to transfer-function, from the maths I've worked out, I still believe that this will give a non-linear transfer-function (I apologise in advance for the amount of maths below, but I can't think of any other way of demonstrating this):
If you consider each sample in isolation as a weighted impulse function (see Fig. 1):
f(t) = A0δ(t)
with a Laplace transform (s-domain representation):
F(s) = A0.
Fig. 1: Individual sample
Using a stair-case DAC, this impulse is reproduced in the analogue world as a pulse (see Fig. 2), which can be represented as:
g(t) = A0[u(t) - u(t - T)]
where T is the sampling period, and u(t) is the unit-step function.
This has a Laplace transform of:
G(s) = A0[1 - exp(-sT)]/s.
Fig. 2: Staircase DAC pulse
The transfer function of this arrangement H(s) is given by:
H(s) = G(s)/F(s)
Substituting:
H(s) = ( A0[1 - exp(-sT)]/s ) / ( A0 )
Here, the amplitude cancels, leaving a transfer-function dependent only on s (think of this as frequency):
H(s) = [1 - exp(-sT)]/s
This implies that a basic "staircase" DAC has a linear transfer-function.
Considering your proposed method:
Fig. 3: Linear interpolation waveform
The individual pulse has a waveform (see Fig. 3) given as:
g(t) = [(A1 - A0)t/T + A0][u(t) - u(t - T)]
with a Laplace transform of:
G(s) = [(A1 - A0)/(T . s^2) + A0/s][1 - exp(-sT)]
When the transfer function is considered now, we get:
H(s) = ([(A1 - A0)/(T . s^2) + A0/s][1 - exp(-sT)] ) / ( A0 )
This cannot be cancelled down to a function in s only, because we have both A0 and A1 in the expression. This shows that the transfer-function is now dependent on the input values.
Please bear in mind this is something I worked out without checking anywhere to see whether this is right, so please don't take this as gospel. |
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| rfbrw |
| quote: | Originally posted by wimms
rfbrw, how can I help you? If you integrate normal step signal, you would not get linear interpolation. What is done is done to achieve _linear_ interpolation. |
Either I don't what you are trying to achieve or I do and don't see the point. From the simulation the net effect looks like linear interpolation and one can achieve that without all the brouhaha that seems to attend your method. If that is the case I see no point. If you are trying to do something else, I simply don't see it. |
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| janneman |
| quote: | Originally posted by wimms
janneman,
If you integrate output of normal DAC, you won't get the same thing. You could achieve almost the same result IF before feeding normal DAC you translated PCM into delta stream computationally. It is important to integrate delta-current, not absolute currents. Then you would need to change your normal DAC IV stage to integrator. [snip] |
But a 'normal' I/V IS an integrator, so I don't see how you can improve on that with what is essentially a scaling change. I thing rfbrw's comments is along the same lines, IIUC.
Jan Didden |
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| guido |
dont wanna mingle into the discussion if this works or not (although HK seems to have sold something like this in the past):D
suppose it does;
The easiest way to get two matched dacs seems to me to take a stereo dac and feed it with left and left delayed and another one and feed it with right and right delayed.
... just like the one i got, however the tda1541 has an offset current which needs to be compensated. dunno if i can compensate completely, think not. Guess that would be a problem (?) |
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| wimms |
| quote: | Originally posted by rfbrw
From the simulation the net effect looks like linear interpolation and one can achieve that without all the brouhaha that seems to attend your method. |
Brouhaha? rfbrw, this is a discussion forum, so if you have constructive input, give it. I had an idea that I presented with my personal thoughts. If that is brouhaha in your book, then I suspect you're into personalities here.
As there have been noted that this is not a new idea, I don't claim its mine. So free yourself from urge to attach it to me and analyze it like idea first implemented by names like HK.
I'm genuinely interested in discussing merits or problems with that idea, and OliFilth is at least trying to make his point.
| quote: | Originally posted by janneman
But a 'normal' I/V IS an integrator, so I don't see how you can improve on that with what is essentially a scaling change. I thing rfbrw's comments is along the same lines, IIUC. |
Perhaps this picture below illustrates it better. There you see DAC output that corresponds to 1KHz sine sampled at 50KHz, simple RC integration of the DAC output, and delta dac output.
RC output is what the output integration of a normal DAC gives. This picture is of course exagerated, as its just simple RC, more sophisticated brickwall filters will increasingly achieve sinusoidal output, but there will always remain the character of this RC integration, which is result of memoryless integration.
Notice that the positive and negative slopes are not symmetric with RC integration. Notice larger difference (error) between original waveform and RC integration vs linear interpolation. This is manifesting as higher spectral composition of DAC output that is subsequently harder to filter, meaning higher order filter is required, is facing more difficult transients.
So, what this linear interpolation gives, is lower spectral density, higher symmetry, simpler filtering. Whether thats good thing to the sound, I don't really know, but I'm inclined to think so. |
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| wimms |
| quote: | Originally posted by OliFilth
Considering your proposed method:
Fig. 3: Linear interpolation waveform
The individual pulse has a waveform (see Fig. 3) given as:
g(t) = [(A1 - A0)t/T + A0][u(t) - u(t - T)]
with a Laplace transform of:
G(s) = [(A1 - A0)/(T . s^2) + A0/s][1 - exp(-sT)]
When the transfer function is considered now, we get:
H(s) = ([(A1 - A0)/(T . s^2) + A0/s][1 - exp(-sT)] ) / ( A0 )
This cannot be cancelled down to a function in s only, because we have both A0 and A1 in the expression. This shows that the transfer-function is now dependent on the input values.
Please bear in mind this is something I worked out without checking anywhere to see whether this is right, so please don't take this as gospel. |
OliFilth,
Thanks for your input. I'd need some more time to chew your math, but here are few thoughts I had immediately.
In essence, you take chunk of signal with linear increase between time points and show that it cannot have linear transfer function. I have problem with that, because the signal could have been part of sinusoid. In effect it appears that you try to proove that analog circuit cannot have linear transfer function, because you'd have both A0 and A1 that do not cancel out and that transfer function depends on previous signal.
Also you do not compare equal things. For delta function, you take 2 samples for analysis, but for step dac only single sample.
Note that transfer function (impulse response) of delta dac is triangle around time=0, timeshifted wrt to the input. And its worth noting that ideal step is inherently nonlinear.
I suspect that you might apply wrong math to the problem. Let me try put it that way: any continuous signal can be decomposed into continuous delta function dA/dt where delta-t (dt) is approaching zero. Thats the essence of continuous signals, and with delta dac we are dealing with continuous signal, thus we should apply math of continuous signal processing. The special case here is that our dt is fixed to a discrete constant, leaving us with the only issue that dA has linear relationship through the system.
Yes, of course next output depends on previous input, but that does not necessarily mean that the transfer function is nonlinear, or that the function itself depends on previous data.
I'm not sure how to express that, I'm not too good with math, but you might want to take a look at this: http://www.spectrumsdi.com/ch13.pdf which explains the convolution integral. That is what the delta dac with integrator is basically doing.
Or here: http://cnx.rice.edu/content/m10085/latest/
But all that goes too deep into the math. I think its much simpler to grasp intuitively. Samples in PCM data describe only infinitesimal instants in time. It describes nothing that happens between the samples. The step output of a normal DAC is also form of interpolation, that is taken to be "hold" for the sake of simplicity and gain considerations. If taken from the view of continuous signal, the only correct way to reconstruct the PCM data into analog IS linear interpolation. Its just not what we assume the original waveform was. We have that strong assumption that PCM data has strictly bandwidth limited sinusoidal signal in it, that gives us the very freedom to apply filtering to reconstruct the original.
So, the comparison problem comes down to finding which DAC output after alias filtering would represent signal closest to original waveform. It can be shown that step DAC with perfect filter can reconstruct original (assuming strict bandwidth limits) exactly, but that has little practical benefit, as ideal analog brickwall filters are impossible to make. To deal with that digital filtering and OS is efficient way, but that pushes DACs to their linearity limits.
The linear analog interpolation, together with moderate OS and digital filtering, can have potential to combine best from both approaches. In addition to theoretical considerations, I'm really also looking at the practical issues, like DAC performance limitations, opamp overloads or just generally nonlinearities triggered by the step output.
guido, I don't see why you couldn't compensate the offset current. |
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| Elso Kwak |
| quote: | Originally posted by wimms
Brouhaha? rfbrw, this is a discussion forum, so if you have constructive input, give it. I had an idea that I presented with my personal thoughts. If that is brouhaha in your book, then I suspect you're into personalities here.
As there have been noted that this is not a new idea, I don't claim its mine. So free yourself from urge to attach it to me and analyze it like idea first implemented by names like HK.
I'm genuinely interested in discussing merits or problems with that idea, and OliFilth is at least trying to make his point.
Perhaps this picture below illustrates it better. There you see DAC output that corresponds to 1KHz sine sampled at 50KHz, simple RC integration of the DAC output, and delta dac output.
RC output is what the output integration of a normal DAC gives. This picture is of course exagerated, as its just simple RC, more sophisticated brickwall filters will increasingly achieve sinusoidal output, but there will always remain the character of this RC integration, which is result of memoryless integration.
Notice that the positive and negative slopes are not symmetric with RC integration. Notice larger difference (error) between original waveform and RC integration vs linear interpolation. This is manifesting as higher spectral composition of DAC output that is subsequently harder to filter, meaning higher order filter is required, is facing more difficult transients.
So, what this linear interpolation gives, is lower spectral density, higher symmetry, simpler filtering. Whether thats good thing to the sound, I don't really know, but I'm inclined to think so. |
Hi wimms,
Interesting picture as the signal in my DAC after the IV looks exactly like the green curve. To get a smooth signal additional filtering is required.:cool: |
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| wimms |
Hi Elso,
Can I see your schematics? |
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| Elso Kwak |
| quote: | Originally posted by wimms
Hi Elso,
Can I see your schematics? |
Yes, With the TDA1543 NON-OS I am currently using 3k65 as the IV-resistor (R3) and a 3n3 cap (C2) across it. Please note "??"= ground.
The scope picture I am referring to is that of a 3150 Hz sine wave. |
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| rfbrw |
| quote: | Originally posted by wimms
Brouhaha? rfbrw, this is a discussion forum, so if you have constructive input, give it. I had an idea that I presented with my personal thoughts. If that is brouhaha in your book, then I suspect you're into personalities here.
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Suspect what what you want but it is now pretty clear me that you have a solution in search of a problem and if that upsets you boo hoo. Whatever it is you have thought up it is not linear interpolation as I, my text books and a number of digital audio companies know it. |
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| wimms |
| quote: | Originally posted by rfbrw
Whatever it is you have thought up it is not linear interpolation as I, my text books and a number of digital audio companies know it. |
I would suggest you to restrict your assertion to yourself alone. Anyway, it is clear that there is no hope to get any useful input from you. Sad you've wasted time in vain. |
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| Circlotron |
Wimms, please continue; I'm sure many are listening. :grouphug:
rfbrw, shoosh! :shhh: |
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| peranders |
:cop:
Time out, wimms and rfbrw! Show each other respect, please :nod:
:cop: |
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| wimms |
rfbrw, my respect.
| quote: | Originally posted by Elso Kwak
Yes, With the TDA1543 NON-OS I am currently using 3k65 as the IV-resistor (R3) and a 3n3 cap (C2) across it. Please note "??"= ground.
The scope picture I am referring to is that of a 3150 Hz sine wave. |
Elso, I'm confused here. Your schematic is pure good-old opamp integrator, subject to same RC signal shape as in my picture.
I thought you'd show something along the lines of http://users.verat.net/~pedjarogic/.../disdia_i-v.htm which is constant current loaded cap integrator whose source current is modulated by DAC output.
Attached is expected signal shape from your schematic. |
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| wimms |
| And LTSpice simulation with Elso's IV stage included. |
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| Circlotron |
Did anyone listen to any results using my software in post #9 along with an integrator on the existing single DAC?
/Circlotron - hopes no-one asks him the same question. :cannotbe: |
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| wimms |
Circlotron, there's not much use to try out on existing DAC. DAC would need to be modified to operate properly in delta mode. DAC itself becomes part of current-source integrator, thus IV Capacitor is needed instead of IV-stage. Normal IV and RC voltage integrator would misbehave there.
Elso's IV stage would work though if R3 was removed and C2 increased to limit the output swing. |
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| Elso Kwak |
| quote: | Originally posted by Elso Kwak
Hi wimms,
Interesting picture as the signal in my DAC after the IV looks exactly like the green curve. To get a smooth signal additional filtering is required.:cool: |
Hi Wimms. I am sorry I must have been totally colour-deaf at the moment of my posting. Of course I meant my DAC is similar to the purple curve in your first picture on myscope.(post# 34) The funny thing is if you lower the frequency of the sine wave the steps get lost. Well your output curve shows that a lot of smoothing has taken place. On my scope it is slightly better but that may be due to additional filtering by the capacity of the cable and non-ideal opamp. What is the frequency of your sine wave in the pictures? (too lazy to calculate from the µs)
As a side note I am one of the few males who is not colour blind as the Moron for the military selection found out. Whe did the whole book of colour dot pages faster and faster.... I guess he thought I learned the book by head.
Again wimms I apologize for the confusion.
I have been thinking a long time about something you posted making the steps smaller in length by two staggered DACs or something like digital antidote by Taddeo. I gave up as even two balanced DACs did not sound better but worse especially in the highs.
Some top of the line Sony converter had two staggered DACs (TDA1541AS1) in the past.
I do not see a fundamental difference with Pedja's IV that I will build some time as the current to voltage converion takes place across the 1k resistors??
:angel: |
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| wimms |
| quote: | Originally posted by Elso Kwak
Hi Wimms. I am sorry I must have been totally colour-deaf at the moment of my posting. Of course I meant my DAC is similar to the purple curve in your first picture on myscope.(post# 34) The funny thing is if you lower the frequency of the sine wave the steps get lost. Well your output curve shows that a lot of smoothing has taken place. On my scope it is slightly better but that may be due to additional filtering by the capacity of the cable and non-ideal opamp. What is the frequency of your sine wave in the pictures? (too lazy to calculate from the µs) |
Hi Elso. I see now. The original gif with purple curve I posted was created by simulating 1KHz sine, and then zoomed into the upper peak of the signal. The RC constant of the purple curve was 2.2usec iirc. The last gif simulating your IV was made with 3KHz signal iirc.
You know, your IV stage can be easily modded to allow testing of the idea discussed here. I think it would be possible to write a simple DSP plugin to foobar2000 that would generate required delta PCM on the fly, thus you could actually audition with real music and measure the results.
You'd need to remove R3 and set C2 to dac-current*TS to get 1V output swing. (TS is sampling time, 1/44.1K). If the DAC is outputting delta-current, then output of your integrator will have same signal shape as in my simulated interpolation. |
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| janneman |
Wimms,
In your graph you are comparing apples with pigtails. The exponential RC time constant curve is for an RC integrator, the straight line approximation is for a constant current integrator like Elso's. What your idea does is changing the steps of the staircase, but the results will be the same as the unmodified stair case: straight line with a constant current integrator, exponential with an RC integrator. I am pretty sure you are fully aware of this, and I can only guess why you chose to use two different integration methods in this 'comparison'!
Your idea may change the step size, but so would oversampling. It does nothing on the basic operation of the way of integrating. If you stay with the same sampling rate, and you lower the step size, you will get a lower recovered analog level, with a lower 'noise' level, but still with the same signal-to-noise-ratio. This is a no-win situation.
It's your decision to follow your idea, but don't expect a large reward for your efforts.
Jan Didden |
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| Jocko Homo |
If this was a way of making a good DAC- I/V setup.....and cheaply, just like MASH/Bitstream/one-bit/etc...........wouldn't those clever Japanese companies that develop all this mass market **** tried it already????
Seems that maybe they would have. I tend to agree with rfbrw. I don't seem to get it either.
Jocko........getting a sunburn on the roof of his mouth. |
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| Elso Kwak |
| quote: | Originally posted by janneman
Wimms,
In your graph you are comparing apples with pigtails. The exponential RC time constant curve is for an RC integrator, the straight line approximation is for a constant current integrator like Elso's.
Jan Didden |
Hi Jan,
Now I am the one to be confused.:confused:
In my DAC I see exponential discharge curves of a capacitor and wimms is proposing a straight line between steps. Right?
As I wrote earlier on this forum the whole problem originates from a far too low chosen sampling frequency for Redbook CD.
At first the industry came with a brickwall filter, then they invented 4 or 8 times oversampling.
And now I am among those guys favouring NON-Oversampling....... |
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| rfbrw |
| quote: | Originally posted by wimms
I would suggest you to restrict your assertion to yourself alone. Anyway, it is clear that there is no hope to get any useful input from you. Sad you've wasted time in vain. |
Wimms, you cannot come to an open forum, try and sell me a lemon when I know it is a lime and get upset when I contradict you.
There are two issues here. One is the value of your proposal, something best left to the likes of circlotron et al.The other is what your proposal actually IS and that is the issue that concerns me. All the maths and insults in the world will not alter the fact that it is NOT linear interpolation, analogue or otherwise. Linear interpolation as a mathematical concept is as simple as it gets and its hardware implementation is just as simple as shown by Beard, Cambridge, Wadia and numerous diy implementations. |
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| wimms |
| quote: | Originally posted by janneman
Wimms,
In your graph you are comparing apples with pigtails. The exponential RC time constant curve is for an RC integrator, the straight line approximation is for a constant current integrator like Elso's. What your idea does is changing the steps of the staircase, but the results will be the same as the unmodified stair case: straight line with a constant current integrator, exponential with an RC integrator. I am pretty sure you are fully aware of this, and I can only guess why you chose to use two different integration methods in this 'comparison'!
Your idea may change the step size, but so would oversampling. It does nothing on the basic operation of the way of integrating. If you stay with the same sampling rate, and you lower the step size, you will get a lower recovered analog level, with a lower 'noise' level, but still with the same signal-to-noise-ratio. This is a no-win situation. |
janneman,
You are attacking me for no reason.
May I suggest you to make few simulations at least? Elso's integrator is no more but RC integrator and IV resistor, with all its RC exponential issues. You can not apply pure current integrator directly onto staircase current - you would get garbage out. Simulate! And not just with single sinewave, but complex signal.
I was making no 'competition' with graphs, but only used them to convey my point, noting exagerations. Why do you accuse me? Elso's integrator can not output straight line approximation, as cannot anything else that is not based on memory of previous sample. Obviously, oversampling is. Many are preferring as little OS as possible. Not because of digital processing btw. As low order filtering as possible.
And I don't understand what you say about step size or basic integration operations. This has no relation to what I'm saying.
I'm suggesting a way to use pure current integrator in place of RC integrator with IV resistor. If you think that you already use pure current integrator, then you are confused. |
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| wimms |
| quote: | Originally posted by rfbrw
Wimms, you cannot come to an open forum, try and sell me a lemon when I know it is a lime and get upset when I contradict you.
There are two issues here. One is the value of your proposal, something best left to the likes of circlotron et al.The other is what your proposal actually IS and that is the issue that concerns me. All the maths and insults in the world will not alter the fact that it is NOT linear interpolation, analogue or otherwise. Linear interpolation as a mathematical concept is as simple as it gets and its hardware implementation is just as simple as shown by Beard, Cambridge, Wadia and numerous diy implementations. |
You still have provided NO constructive input to this discussion. I still don't see the point of your participation.
Its not your contradicting that bothers me, but fact that you have offered exactly ZERO reasoning to your denial. |
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| janneman |
| quote: | Originally posted by wimms
janneman,
You are attacking me for no reason.
May I suggest you to make few simulations at least? Elso's integrator is no more but RC integrator and IV resistor, with all its RC exponential issues. You can not apply pure current integrator directly onto staircase current - you would get garbage out. Simulate! And not just with single sinewave, but complex signal.
I was making no 'competition' with graphs, but only used them to convey my point, noting exagerations. Why do you accuse me? Elso's integrator can not output straight line approximation, as cannot anything else that is not based on memory of previous sample. Obviously, oversampling is. Many are preferring as little OS as possible. Not because of digital processing btw. As low order filtering as possible.
And I don't understand what you say about step size or basic integration operations. This has no relation to what I'm saying.
I'm suggesting a way to use pure current integrator in place of RC integrator with IV resistor. If you think that you already use pure current integrator, then you are confused. |
Wimms, I am not attacking you or accusing you. I addressed the merits, if any, of your idea. I think if you read my post less emotionally, you will agree. I apologise if I gave the impression to accuse you of something less then honesty. But it is well known that people - unconsciensly - often present data in a favourable way.
You could be right that I misread Elso's I/V converter. I'll look at it again.
But that doesn't change the basic fact, and please let me know if I am right, that your idea changes the step size, but NOT the 'shape' of the step. So, whatever the integration method, it can only differ in level or amplitude, NOT in basic shape. I think that part of rfbrw's frustration came from the fact that this obvious fact is being glossed over.
So, I think you have received advise from different people looking at your idea from different angles but with the same conclusion. Does that count for something?
Jan Didden |
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| rfbrw |
| quote: | Originally posted by wimms
You still have provided NO constructive input to this discussion. I still don't see the point of your participation.
Its not your contradicting that bothers me, but fact that you have offered exactly ZERO reasoning to your denial. |
There is so much information out there defining linear interpolation that it beggars belief that you cannot find it. One can only conclude you are not looking for it.
So once more.
For a series of samples A, B, C, D you have an output of A, (A+B)/2, B, (B+C)/2, C, (C+D)/2, D. That is linear interpolation. It assumes the points are joined by a straight line. |
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| steve |
RFBRW's post explaining linear interpolation is correct... at least as far as he goes with it, a series A,B,C,D does indeed lead to a series A, (A+B)/2, B, (B+C)/2... but what is the point? it also leads to a series A, (A+((A+B)/2)/2, (A+B)/2... and so on... looks like 'upsampling' to me... but WIMMS is suggesting a method of 'integrating' the difference.... essentially 'upsampling' to a 'infinite' level of samples... Seems like a pretty neat idea to me.
Steve |
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| rfbrw |
| quote: | Originally posted by steve
RFBRW's post explaining linear interpolation is correct... at least as far as he goes with it, a series A,B,C,D does indeed lead to a series A, (A+B)/2, B, (B+C)/2... but what is the point? it also leads to a series A, (A+((A+B)/2)/2, (A+B)/2... and so on... looks like 'upsampling' to me... but WIMMS is suggesting a method of 'integrating' the difference.... essentially 'upsampling' to a 'infinite' level of samples... Seems like a pretty neat idea to me.
Steve |
It is indeed a crude form of oversampling, and is found in bitstream dacs operating in conjunction with a FIR based oversampler. You'll find a 4x variant in Wadia dacs. It is, in theory at any rate, infinitely expandable though in practice it is limited by the serial clock rate.
BTW steve, the next step practical step in terms of ease of implentation would be 4x,though there is, I think, a dac with 3x linear interpolation. 4x would yield [4A],[3A+B],[2A+2B],[A+3B],[4B].I have a schematic from the Japanese magazine MJ that follows the SAA7220 with 64x linear interpolation. |
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| alvaius |
I have read this topic with some interest. Can someone answer me un-emotionally:
1) How are you going to accurately, in the analog domain, represent both n, and n-1 samples to 16+ bits precision? There is a difference between paralleling DACS and running them completely independantly (you don't get the averaging effect).
2) I know have this current source integrator. My current source would need to output a current that is exactly correct for the step size that will change for every sample. How will this be implemented? Will this not be prone to errors as well?
3) The comments was made that this would be like "infinite oversampling". Mathematically, that does not seem true to me at all. Going back into the depths of the brain, this just seems like a trapezoidal approximation which is just a second order approximation of the analog domain. That is far from infinite. In fact, I don't think mathematically it will be a whole lot more accurate than a 2* oversample with a first order anti-alias filter. As opposed to square waves, now you have triangular waves. Same harmonics, they just roll off faster at higher frequencies. |
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| steve |
Just a quick 'clarification' I used the term 'infinite upsampling' as an analogy. Perhaps it was a poor one, but the previous poster explained the idea of 'linear interpolation' by describing a series ... and showing the calculation for the 'mid-point' of that series... I was trying to point out that the technique in question provides an 'analog function' that does not occur in the 'digital domain', hense the only 'digital analogy' would be to 'upsample'.. meaning that you would need to make more than just that 'midpoint' calculation to approximate that 'analog function' but would infact have to break the sample into ever smaller 'time units' .... same 'analogy' used in Calc 101 to explain the integral...
I don't think anyone here has any illusions about somehow 'creating' new data out of thin air... just looking to find the most logical interpretation of the data that is present.
Steve |
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| steve |
| Oh... by the way... an analog 'function' is just that, something that happens in 'real time' while a digital signal is simply a sequence of 'samples', there is no way to 'perfectly' describe an analog function in the 'digital domain' without 'infinite' sampling... Assuming of course that the analog function changes over time. |
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| Pedja |
| quote: | Originally posted by alvaius
As opposed to square waves, now you have triangular waves. Same harmonics, they just roll off faster at higher frequencies. |
That is right, but it is not that small. The effect is, let’ say, that instead of -30dB the image will fall to -60dB. Instead of -50dB it will be at -100dB.
Wimms, nice thread, I’ll read it carefully later today.
Pedja |
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| wimms |
| quote: | Originally posted by janneman
But that doesn't change the basic fact, and please let me know if I am right, that your idea changes the step size, but NOT the 'shape' of the step. So, whatever the integration method, it can only differ in level or amplitude, NOT in basic shape. I think that part of rfbrw's frustration came from the fact that this obvious fact is being glossed over.
So, I think you have received advise from different people looking at your idea from different angles but with the same conclusion. Does that count for something? |
Jan, you are wrong. What we are talking about, is exactly changing the shape of the integration. What you assume, as well as perhaps others, is RC voltage integrator with exponential decay on the capacitor. That is THE only way you can integrate with any normal DAC. Its not much use and could aswell go directly with Nth order filtering.
What I propose, is direct current integrator, without RC exponential decay - thus linear shape as constant current feeding cap would do.
Now - to be able to use direct current integrator, you NEED delta-PCM. Its a derivative of the source PCM signal, and after integration becomes back PCM signal. The linear interpolation on the way is just a pleasant byproduct.
What I've met so far is frustratingly large amount of misunderstanding.
| quote: | Originally posted by rfbrw
There is so much information out there defining linear interpolation that it beggars belief that you cannot find it. One can only conclude you are not looking for it.
So once more.
For a series of samples A, B, C, D you have an output of A, (A+B)/2, B, (B+C)/2, C, (C+D)/2, D. That is linear interpolation. It assumes the points are joined by a straight line. |
Thats EXACTLY what proposed idea is about and implements - straight line between sample points.
Now what? |
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| wimms |
| quote: | Originally posted by alvaius
1) How are you going to accurately, in the analog domain, represent both n, and n-1 samples to 16+ bits precision? There is a difference between paralleling DACS and running them completely independantly (you don't get the averaging effect). |
You shift PCM data by 1 sample in time (delay), and output n and n-1 samples through 2 DACs concurrently. If you then connect +I output of one dac and -I output of other dac, the resultant current will be delta-PCM.
| quote: | | 2) I know have this current source integrator. My current source would need to output a current that is exactly correct for the step size that will change for every sample. How will this be implemented? Will this not be prone to errors as well? |
by summing + and - output of current-output DACs and getting output current that is precisely proportional to the step size.
Everything is prone for errors. I don't know all real-life difficulties it might face. The theory is there and simulations do WORK. Whether it is any benefit sonically, I have not a faintest idea.
| quote: | | 3) The comments was made that this would be like "infinite oversampling". Mathematically, that does not seem true to me at all. Going back into the depths of the brain, this just seems like a trapezoidal approximation which is just a second order approximation of the analog domain. That is far from infinite. In fact, I don't think mathematically it will be a whole lot more accurate than a 2* oversample with a first order anti-alias filter. As opposed to square waves, now you have triangular waves. Same harmonics, they just roll off faster at higher frequencies. |
For a series of samples A, B, C, D you have an output of A, (A+B)/2, B, (B+C)/2, C, (C+D)/2, D. Thats computational linear interpolation. What I achieve, is straight line between any pair of points: A-B, B-C, C-D, which corresponds exactly to math of linear interpolation. Because this is done with analog integrator of constant current, this creates infinite number of intermediate analog samples between each pair of samples. To create equivalent signal digitally and with staircase, you would need infinite oversampling. Thus, its a point of analogy.
And yes, triangular shapes contain a LOT less spectral garbage. |
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| rfbrw |
| quote: | Originally posted by wimms
You shift PCM data by 1 sample in time (delay), and output n and n-1 samples through 2 DACs concurrently. If you then connect +I output of one dac and -I output of other dac, the resultant current will be delta-PCM.
by summing + and - output of current-output DACs and getting output current that is precisely proportional to the step size.
Everything is prone for errors. I don't know all real-life difficulties it might face. The theory is there and simulations do WORK. Whether it is any benefit sonically, I have not a faintest idea.
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Samples are processed such that
original sample dac1 <= A B C D E
delayed sample dac2 <= - A B C D E
As described I now convert each sample train, invert the output of one dac and then sum both outputs. If I have described the process correctly, the sample rate has stayed the same but I have now scaled the data. What have I gained? |
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| wimms |
| quote: | Originally posted by rfbrw
Samples are processed such that
original sample dac1 <= A B C D E
delayed sample dac2 <= - A B C D E
As described I now convert each sample train, invert the output of one dac and then sum both outputs. If I have described the process correctly, the sample rate has stayed the same but I have now scaled the data. What have I gained? |
You gain delta-PCM, or differential PCM: (A-0) (B-A) (C-B) (D-C) ..
If that is in a form of constant current proportional to the difference, then you can feed this into direct current integrator. Output of the latter will be voltage signal that connects PCM samples with straight line, ie. effectively linear interpolation. You eliminated RC integrator's property of RC time constant and exponential decay on the cap. Integrator is formed from DAC current output and simple capacitor. Alternatively opa integrator without resistor feedback.
If you feed original PCM into current integrator, you'd get garbage out. If you feed into RC integrator, you'd get exponential decay property. Do you understand that?
If you want to question merits of linear interpolation as such, then its separate question, isn't it.
edit: re scaled data. Maybe its not clear that the voltage on the current integrator capacitor will track PCM data precisely. Positive delta-PCM will cause voltage to go up, negative delta to go down (from its last voltage), at a rate that is proportional to the delta-PCM. Thus do not view this delta stream as PCM that gets smoothed and filtered - changes to capacitor voltage are incremental. |
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| rfbrw |
| We will have to agree to disagree on the definition of linear interpolation but that aside I would have thought you would be better served with uniform steps. |
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| Jaka Racman |
Hi,
while I have no doubts that the circuit works as advertised with simulation, I wold like to know how do you intend to solve practical problems. Let's say you put continous value into your real DAC. While there should be no current at the output, some fraction of the LSB current will surely be there. This current will slowly charge your IV cap to the limit of the voltage compliance of the DAC's output. Input current of the following amplifier stage was not even taken into consideration. I think it is impossible to compensate for offset in proposed passive IV conversion. The only solution I see is active integrator at the output and DC servo loop for the integrator.
Best regards,
Jaka Racman |
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| wimms |
| quote: | Originally posted by rfbrw
We will have to agree to disagree on the definition of linear interpolation but that aside I would have thought you would be better served with uniform steps. |
There is no disagreement on the definition of linear interpolation. I have no idea what you agree to disagree with.
Why would uniform steps be better? Are you going to say something with a content or not? |
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| guido |
| quote: | Originally posted by wimms
Perhaps this picture below illustrates it better. There you see DAC output that corresponds to 1KHz sine sampled at 50KHz, simple RC integration of the DAC output, and delta dac output.
RC output is what the output integration of a normal DAC gives. This picture is of course exagerated, as its just simple RC, more sophisticated brickwall filters will increasingly achieve sinusoidal output, but there will always remain the character of this RC integration, which is result of memoryless integration.
|
Eh,
Think the green line is wrong. should it not go to the right corner of the blue sample in the middle ? Did a simulation in vis-sim long ago and it looks like the blue and green line, except for the above.
From a piece of paper i kept with the RLS brochure i see i got to the same thing as you're proposing now. But back then i did not know how to build it.
Those were the days i could follow that laplace stuff :xeye:
As for compensating the current, i'm afraid a little drift of the dacs or the compensating element would give offset current easily.
With i/v resistor this is just dc, but here it would influence the integrating process and therefore the signal (not?).
Pedja might know this from his dac, he's compensating too.
Edit: put better into words two posts up.
...
HK talks about 'connects the stairs represented by the data points of each bit of digital music' and 'technically speaking RLS is making a linear interpolation between two consecutive samples'
Looks like the thing you are proposing.
The above leads to 'one pole low pass filter (-3dB @ 88kHz) which, thanks to the extremely smooth signal, is now more than sufficient to deal with any remaining trace of high freq noise'.
That's the gain you get from this: less analog filtering required.
Mind you they r using 8x dig filter before all this.
But nowadays (some) people are already happy with 1x OS without much/any filtering and tons of high freq noise on the output of a dac. So if it's worth the effort ?
integrating comperator:confused: |
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| wimms |
| quote: | Originally posted by Jaka Racman
I wold like to know how do you intend to solve practical problems. Let's say you put continous value into your real DAC. While there should be no current at the output, some fraction of the LSB current will surely be there. This current will slowly charge your IV cap to the limit of the voltage compliance of the DAC's output. Input current of the following amplifier stage was not even taken into consideration. I think it is impossible to compensate for offset in proposed passive IV conversion. The only solution I see is active integrator at the output and DC servo loop for the integrator.
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Hi Jaka. I think the only valid continuous value we accept to listen to is zero, meaning we need to deal only with removing DC on the IV cap. That can be done with DC servo too. That basically also removes static offset of the dacs at any PCM output, and the rest is dynamic errors appearing as noise I guess. |
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| wimms |
| quote: | Originally posted by guido
Think the green line is wrong. should it not go to the right corner of the blue sample in the middle ? Did a simulation in vis-sim long ago and it looks like the blue and green line, except for the above.
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No, there are 2 samples in the middle with very small PCM difference. Thus green curve is flat at the top, obscured by the purple RC curve. |
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| rfbrw |
| quote: | Originally posted by wimms
There is no disagreement on the definition of linear interpolation. I have no idea what you agree to disagree with.
Why would uniform steps be better? Are you going to say something with a content or not? |
Dude, the floor is yours. You are far too touchy for me. |
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| guido |
| quote: | Originally posted by wimms
No, there are 2 samples in the middle with very small PCM difference. Thus green curve is flat at the top, obscured by the purple RC curve. |
ah yes, getting late here... |
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| guido |
very late.... From the net somewhere, buyers guide for second hand stuff:
Harman/Kardon HD7725 £800 Jan 94 Construction is price-correct, but not the excessively relaxed sound.
excessively relaxed due to what, the RLS stuff or ???? |
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| alvaius |
quido, Jaka, thanks for wading in and voicing my concerns and mathematical thoughts....
-- Would someone like to wade in and tell me how they are going to match two DACS to a tremendously high resolution? I realize this is a "delta" signal, but the worst delta is at low signal levels, so I see losing resolution, well actual SNR. You will at least 1/2 the SNR.
-- you also need to make a current source that is exactly proportional to the step size...
- quido, thank you for confirming my thought that this is a low pass filter essentially (in a mathematical sense)
- I agree that a triangle wave decays much quicker. However, it will not be -30 or -50db smaller until high frequencies, not for the first few critical harmonics. A square wave decays at 1/n (where n is the harmonic number). A triangle decays at 1/n^2.
- I am actually interested in how this will sound once implemented, however, in terms of pure implementation, oversampling is much simpler and provides similar results does it not? Of course, you can mix the two...if you can implement in the analog domain.
Good Luck.. not raining on anyones parade.. I just don't see how practically it is going to come about and what the real benefits will be compared to other implementations. |
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| wimms |
| quote: | Originally posted by alvaius
-- Would someone like to wade in and tell me how they are going to match two DACS to a tremendously high resolution? I realize this is a "delta" signal, but the worst delta is at low signal levels, so I see losing resolution, well actual SNR. You will at least 1/2 the SNR. |
The easiest way to match DACs is to take stereo DAC chip I believe.
Why do you think low level signal is worst? Or any worse than with normal DAC? Step size of delta signal is smaller than with normal DAC. No resolution is lost, though I can't say about SNR.
| quote: | | -- you also need to make a current source that is exactly proportional to the step size... |
Output of DAC chip is the current source. So is difference of 2 DAC outputs. It is exactly proportional to step size.
| quote: | | - I am actually interested in how this will sound once implemented, however, in terms of pure implementation, oversampling is much simpler and provides similar results does it not? Of course, you can mix the two...if you can implement in the analog domain. |
Indeed. I'm curious too. Digital oversampling is very well complementing this. |
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| guido |
| quote: | Originally posted by alvaius
- quido, thank you for confirming my thought that this is a low pass filter essentially (in a mathematical sense)
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Bad phrasing from my side, it should be:
HK used only (quote) 'one pole low pass filter (-3dB @ 88kHz) which, thanks to the extremely smooth signal, is now more than sufficient to deal with any remaining trace of high freq noise'. So this is the analog filter stage.
According to the brochure this is much better than cd player x which can use up to 6 pole filters at the analog filter stage. |
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| ojg |
Interesting thread so far!
| quote: | Originally posted by alvaius
-- Would someone like to wade in and tell me how they are going to match two DACS to a tremendously high resolution? I realize this is a "delta" signal, but the worst delta is at low signal levels, so I see losing resolution, well actual SNR. You will at least 1/2 the SNR. |
The worst delta may happen at all signal levels! You may have two consecutive samples of 1 and 2 which gives a delta of 1, or you may have two consecutive samples of 32766 and 32767 which also gives a delta of 1. However alvaius is right that low-level sinewaves will have greater number of small deltas then loud sinewaves per period.
Another issue:
High deltas will be most likely for high frequencies so the DAC will have best performance at frequencies close to Nyquist. Since low deltas will be most likely at low frequency signals, SNR will decrease with falling frequency. By how much I don't know, I'll have to think about this one a bit.
Also the cut-off frequency of the servo would need to be higher the more non-linear the DAC is, right? So maybe you will find in practice that it has to be unreasonably high and will roll off the bass-response?
wimms: I don't know if LTSpice supports it, but it would be interesting if you add some random noise to the DAC currents and see how it behaves then for various signals. |
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| alvaius |
A thank you to Wimms for posting an interesting topic that has got us thinking on diyAudio again.... sometimes agreeing, sometimes not, but always moving in a somewhat forward direction and learning. I was beginning to think diyAudio was getting stale.
Alvaius |
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| wimms |
| quote: | Originally posted by ojg
The worst delta may happen at all signal levels! You may have two consecutive samples of 1 and 2 which gives a delta of 1, or you may have two consecutive samples of 32766 and 32767 which also gives a delta of 1. However alvaius is right that low-level sinewaves will have greater number of small deltas then loud sinewaves per period. |
Thanks for your comments, ojg.
I'm abit confused though. Do I understand you right that you and alvaius consider small delta as being worse than large delta? Indeed low-level sines will have smaller delta, as also lower freqeuncy sines. But I see that its not the size of step or delta that matters, but its precision. With normal LPCM dac, distortion depends on LSB precision as much as with dPCM - LSB errors translate into error voltage.
It is not right to think that because dPCM uses on average smaller deltas it would increase significance of these errors. Its because dPCM deals with deltas only, absolute signal levels accumulated on the integration Cap, while LPCM deals with absolute levels comparable to full swing of the signal. Full swing of the signal with dPCM is recreated on the IV capacitor, and it is of same magnitude as with LPCM. Thus delta errors with dPCM are equivalent to LSB errors in LPCM, no more, no less. IIUC.
There is one bit that might make dPCM even benefit from small deltas. Its distortion depends on monotonicity of the dac, and by utilizing smaller dynamic range of the DAC the amplitude of monotonicity errors is reduced too. That of course only if single DAC is operated with dPCM input.
| quote: | Another issue:
High deltas will be most likely for high frequencies so the DAC will have best performance at frequencies close to Nyquist. Since low deltas will be most likely at low frequency signals, SNR will decrease with falling frequency. By how much I don't know, I'll have to think about this one a bit. |
I do not agree that best performance is near Nyquist, but much lower. First because at Nyquist delta dac approaches triangular wave having larger error than square wave, causing frequency rolloff. And second with large delta maximum slew rate is needed that elevates timing jitter importance considerably. Voltage error equals signal slew rate multiplied by jitter timing error.
Fortunately general spectral distribution of music is rolling off towards high frequencies, thus maximal deltas are rarely required.
Re SNR I don't know, I don't quite understand the mechanism of reduced SNR at lower frequencies. Although simulations suggest that, I'm suspecting its either simulation imprecision or some other reasons. Perhaps IV capacitor discharge induced errors. If so then it must be signal dependant noise addition, masked by the signal. I wonder how bad this might be to the sound.
| quote: | | Also the cut-off frequency of the servo would need to be higher the more non-linear the DAC is, right? So maybe you will find in practice that it has to be unreasonably high and will roll off the bass-response? |
Interesting concern. And there is also quite interesting peculiarity with delta dac. In general, we don't care about DC offset, it | | | |
