| nar |
Hi to everyone here . The project here , me and my friend dreamt of it . Finally we got to something that should work ? and sonically very good ! That's all what we want ...
First , the design is not tested - we are just finalizing schematics .
Basically as you can see nothing very new here - but the DAC works WITHOUT oversampling . That for a better sound , and we let the ear do its own low pass filter ;)
Second , the design should be as simple as possible without compromising sound quality . It should be easy to build by anyone , and that's why you can see no CMS part , every circuitry is at human scale , for better layout reproduction and adaptability .
We decided to use a CS8412 as input receiver , and to trust the SPDIF clock . The signal is then routed to some 74HCXXX to adapt digital data to input compatible words for the 2*PCM1702 , with a current out . The I/V conversion is made by the amazing analog stage found in Mr PASS's D1 . And that's all . No opamp filtering at the output
Objectively , with good measurements on the bench there should be HF garbage , but no oversampling is certainly better for the sound . We wait a lot of this design .
Feedback welcome !
Regards
Anael
I'll post the parts here as they get finalized :devilr: |
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| nar |
| And here is the schematic of the I:V stage ( unbalanced ) |
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| nar |
| And let me take this schematic from an old thread , if the I/V stage is not sophisticated enough for you ;) |
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| nar |
| The layout in. pdf so that it can come out of your printer at the exact scale ;) |
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| nar |
| Note that the 2*IV resistors are for passive conversion only . For the ones who prefer it this way . In the Borsanar the Iout is directly wired to the source of IRF610 on the I/V stage ! |
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| nar |
I had a check of the circuit board vs. schematic , and it seems we have a bug here :hot:
The connections of the V+/GND pins of the 74HC164s are inverted , i.e. pin 7 goes to GND instead of V+ and pin 14 goes to V+ instead of GND
We will correct the PCB
Best regards
Anael
PS traces modifications are perhaps important - especially GND planes and voltages distribution . Thanks :angel: |
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| nar |
The .pdf PCB is correct , the numbers 7 and 14 were just interverted on the schematic
Here is the correction
Apologies :smash:
Regards |
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| Guido Tent |
| quote: | Originally posted by nar
We decided to use a CS8412 as input receiver , and to trust the SPDIF clock . Feedback welcome !
Regards
Anael
I'll post the parts here as they get finalized :devilr: |
Hi
I like simple schematics, though it is nt a goal as such
The jitter at pin 12 (8412) is too high, lower it, your ears will like it
To start, seperate the supply at pin 7 and pin 22, at least by using a ferrite bead in pin 22, and a resistor (say 22 ohm) at pin 7. Better, build a low noise supply for pin 7
Then attack the 8412 loopfilter, by rducing the resistor to 500 ohm, and quadruppling the cap to 220 nF. You may take that even a step further, if you like
Then add a cap (10nF) at pin 20, it is next to pin 19 which puts out 11.2896 MHz. The silicon layout guy at Crystal must have been drunk when he did this.
Why do you use 10k in series from pin 12 ? I like series resistors, but they are missing in the rest of your circuit.
You may want to add ferrite beads in the supply lies rom the other logic as well
succes |
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| nar |
What do you mean by ferrite beads ? Precisely ?
Regards
Sorry english isn't my first langage :D |
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| Guido Tent |
| quote: | Originally posted by nar
What do you mean by ferrite beads ? Precisely ?
Regards
Sorry english isn't my first langage :D |
Hello Nar,
Ferrite is a material that shows high impedance at high frequencies. A bead is like a drop of that material around a wire. You may read the backgrounds here:
http://www.tentlabs.com/Info/Articl..._decoupling.pdf
cheers |
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| rfbrw |
Two things.You might consider replacing the inverters with pairs of XORs, equalizing the propagation delay between the dacs.
The other is the interchannel delay. I'd find that unacceptable.
ray. |
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| nar |
OK . with my friend we had a long discussion to decide if we would change the design.We decided not to do it because we trust the original design . However we had to make some corrections...
To rfbrw:
I understand nothing is perfect and remember it is just some diyers first attempt in DACs.Be indulgent. There is of course interchannel delay.
According to Borsa, there is a delay between 2 outputs of...11µS.
I wonder if you can hear it ... or you have supersonic ears !
Second , it would give an offset virtual vertical distance of 3,6mm between the speakers( in the horizontal plane).Tell me if you listen to music attached in a chair millimetrically fixed vs speaker distance , and if you have a metal hat like Alex in Orange Mécanique , just to avoid moving your head of about 1mm ...:devilr:
(I'm joking of course :) )
To Guido Tent :
Many thanks for the link , we read the PDF with a great interest and we tried to applicate some of it to the design . It is very nice surprise to be helped by so precise and brillant tech. The option we retained basically is to use 22R resistors 0,1% welwyn metal in all supply lines,and why not to pass some specially adapted ferrite beads around the resistor body ... well ... we like it ...
So now we should get closer ;)
Things become hot as we approch May :hot: :hot: :hot: |
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| jean-paul |
| quote: | According to Borsa, there is a delay between 2 outputs of...11µS.
I wonder if you can hear it ... or you have supersonic ears !
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I think the point is that it is technically not optimal and it is not really necessary. You could reread the advice Ray gave.
I won't be surprised if the delay does affect sonical results in a negative way ... The human ear is very sensitive for errors in the time domain.
Don't trust the SPDIF clock just like that ... |
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| nar |
Jean Paul :
So which is a simple way to avoid it ? Tell us , we don't work only for ourselves ;)
Maybe I should ask Nelson if really disturbing .:eek:
Regards
Anael |
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| nar |
| The One and Only ... after all we use one of his modules :cool: |
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| dddac |
Site is not available??? :confused:
Nar, do NOT trust the spdiff from the 8412. Re-clocking with a Tent-XO will improve the sound stage largely.... more air, more focus and pin point.
Have you build a prototype already? Any listening-experience to share?
I will not comment your I/V, as this seems to be a 2-camp thing here on the forum :rolleyes: and as I still have not tried the active one, I cannot comment. I do know, that the best DAC's I have heard so far used passive I/V... But that might be coincidence ;)
take care,
doede |
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| till |
| hi, for those ferrite beads and inductors for DAC decoupling: what should be inductance values for this purpose? As i understand with the LC decoupling we get something like a second order LP instead of first order with only C. As a DAC can easily need some ten mA or so, it would be a R of 100 or so Ohms. A ferrite bead with few copper windings would be very few uH, what would be a some 100khz LP at best? |
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| Ulas |
I find this thread very amusing. Here we have all the diyAudio digital “experts” picking nits and no one sees the big problem with Nar’s design.
Nar, before you make any PCBs I suggest you do a thorough timing analysis of your design. |
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| Guido Tent |
| quote: | Originally posted by nar
So now we should get closer ;)
Things become hot as we approch May :hot: :hot: :hot: |
Hi Nar,
I do not want to upset your schedule, but lookin at he PCB design, I am somewhat worried
You have not applied decoupling at each IC, let alone that you have placed the caps sometimes close to the + pins
The fact that I can easilly see through the PCB (i.e. lack of black area = ground) means that the impedances are too high
You may consider choosing a somewhat more "logic" way to place the chips, to shorten the critical wiring (clocks, data).
An alternative sollution may be a double layer PCB
just some thoughts, my experience tells me that the results very much depend on he layout as well
succes |
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| nar |
i am intended on this project . Note I didn't really make the design , I trust my friend Borsa for it as I am not familiar with digital flows :bawling:
Yes we could surely do a better ground plane and have decoupling caps closest to components , and basically replace all straps on V lines by resistors with a ferrite bead :cannotbe:
For the layout maybe a little complicated to work on 2 sides PCB , but as I understood we should get the CS8412 away from the others , and get shortest connexions between 74s , and a good ground plane and proper decouplings !!!
No one gave us a way to reclock L and R datas so that they can arrive together on the DACs :confused:
A little help would be nice , gentelmen ;)
Regards
Anael |
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| Guido Tent |
| quote: | Originally posted by nar
i am intended on this project . Note I didn't really make the design , I trust my friend Borsa for it as I am not familiar with digital flows :bawling:
Yes we could surely do a better ground plane and have decoupling caps closest to components , and basically replace all straps on V lines by resistors with a ferrite bead :cannotbe:
For the layout maybe a little complicated to work on 2 sides PCB , but as I understood we should get the CS8412 away from the others , and get shortest connexions between 74s , and a good ground plane and proper decouplings !!!
No one gave us a way to reclock L and R datas so that they can arrive together on the DACs :confused:
A little help would be nice , gentelmen ;)
Regards
Anael |
Hi
If you are not willig to invest in signal integrity, you will not be able to retrieve the last information from what CD offers you
For inspiration (also on reclocking) look at the DAC I designed 8 years ago with some friends
http://httpd.chello.nl/%7em.heijlig...html/dactop.htm
Why do you have to get the 8412 away from others ?
cheers |
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| nar |
Thanks Guido the link is very extensive and rich in observations , you are professional and we are musicians so we don't have all that knowledge :xeye:
The schematic is very nice and clear . I guess all components are needed to obtain good sound .
The problem is we wanted t obuild something SIMPLEST . With less parts . With both a more direct path for the digital and analog signals .:(
The 2 schools of I/V conversion are interesting/ passive vs active .
My friend is very tempted by the transformer after I/V resistor .
I would rather use the D1 stage . What we will do is make 2 prototypes with different I/V manners , so we could compare !!!
WE WOULD LIKE TO STAY AS CLOSE AS THE SIMPLEST WAY IN THE DIGITAL DOMAIN . With current design there is re-looking to do ... what should we start with ... the channel interdelay problem ?
Regards
Anael |
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| Guido Tent |
| quote: | Originally posted by nar
Thanks Guido the link is very extensive and rich in observations , you are professional and we are musicians so we don't have all that knowledge :xeye:
The schematic is very nice and clear . I guess all components are needed to obtain good sound .
The problem is we wanted t obuild something SIMPLEST . With less parts . With both a more direct path for the digital and analog signals .:(
The 2 schools of I/V conversion are interesting/ passive vs active .
My friend is very tempted by the transformer after I/V resistor .
I would rather use the D1 stage . What we will do is make 2 prototypes with different I/V manners , so we could compare !!!
WE WOULD LIKE TO STAY AS CLOSE AS THE SIMPLEST WAY IN THE DIGITAL DOMAIN . With current design there is re-looking to do ... what should we start with ... the channel interdelay problem ?
Regards
Anael |
bonjour Anael,
OK, keep it simple, but at least use one decoupling cap at each IC. Place it as close as possible to the gnd pin, and use 10 to 47 ohm series resistors (cheap and simple), value slightly depends on the current consumption.
Then, look at the floorplan. Most crictical are the RF signals clock (pin 12 of 8412) and data, and the local decoupling caps. Now place the 8412 and the other logic "in a column" , in parallel to the existing column of the 2 converter chips.
At present, the 3 logic IC's are inbetween, forcing long wires.
Place all other component outside the area, as it is " low frequencies'" running there.
forget about compensating inter channel delay, this is nonsense
salut |
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| stefanobilliani |
Hallo , I take the chance to ask something to Guido Tent :
I am using the XOR's gates (SN74HC86N) closely after the SAA7310 and pretend they act as buffers for all the digital lines and inverters for the DATA line since my interest was a balanced dac . I am using also an USB cable (35cm or more) that carries the 4 signals (BCK WS DATA+ DATA-) outside the cd player ,but I think I will go with 4 shielded cables for each line. Previously there was the reclocker + your XO + dacs and the clock was feeding the flip-flops(synchronous) and the SAA7310. I admit to prefere, from a musically point of view the today solution :
Inside the player: saa7310 + XOR gates
Outside the player : Tent XO and DACS (1543 or 1541A) .
I do not why , but I feel as the recloker is not essential .I point out also that the XOR gates as buffers works good to my ears .
I ask you what you think about the differences between the choice of recloker and XOR gates and if your clock is still in better place outside the player since the reclock is not used anymore.
For the 1543 lovers : the D1 stage is applied with succes to the dac , I will post the schematic soon , I just need a thread to jump in. |
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| nar |
I had an idea , analogic one ... to compensate delay between channels , to use the equivalent length in wire to slow down the channel in advance , basing on speed of electrics in a cable ...
That would have done about ...50...100 meters ! As a wirewrap wire could do it ( 5cm*3cm cylinder of wire)...!!!!
Silly , yes , but it would have given some inductance too ,providing HF filtering...and put a normal (9mm self) on the other channel ... to have same filtering without delay ...
But would be worse than before...yes?
The delay between channels would have been of one sample ... do you think we could hear it or if not heard , feel it to be disturbed?
Best regards :)
I will take the layout on hand , try to do something logic for HF...! |
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| nar |
Stephanobilliani:
Could you adapt the D1 stage to the 1545? The problem isDC at dac output :(
Regards
Anael |
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| Guido Tent |
| quote: | Originally posted by stefanobilliani
Hallo , I take the chance to ask something to Guido Tent :
I am using the XOR's gates (SN74HC86N) closely after the SAA7310 and pretend they act as buffers and inverters for the DATA line since my interest was a balanced dac . I am using also an USB cable (35cm or more) that carries the 4 signals (BCK WS DATA+ DATA-) outside the cd player ,but I think I will go with 4 shielded cables for each line. Previously there was the reclocker + your XO + dacs and the clock was feeding the flip-flops(synchronous) and the SAA7310. I admit to prefere, from a musically point of view the today solution :
Inside the player: saa7310 + XOR gates
Outside the player : Tent XO and DACS (1543 or 1541A) .
I do not why , but I feel as the recloker is not essential .I point out also that the XOR gates as buffers works good to my ears .
I ask you what you think about the differences between the choice of recloker and XOR gates and if your clock is still in better place outside the plyer since the reclock is not used anymore.
For the 1543 lovers : the D1 stage is applied with succes to the dac , I will post the schematic soon , I just need a thread to jump in. |
Hi
With respect to jitter:
- The conversion clock of the DAC is most important
- Reducing jitter at the data line is of second importance
Place the clock close to the DAC, feed back that clock to the drive, eventually clocking the EXOR gates there.
Eventually reclock the data just before it enters the DAC chip
lower jitter = better
cheers |
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| Andypairo |
| quote: | Originally posted by stefanobilliani
For the 1543 lovers : the D1 stage is applied with succes to the dac , I will post the schematic soon , I just need a thread to jump in. |
C'mon Stefano,
don't be shy!
This topic deserves a thread of his own, so.. just post it ;)
Cheers
Andrea |
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| stefanobilliani |
| quote: | Originally posted by Guido Tent
Hi
With respect to jitter:
- The conversion clock of the DAC is most important
- Reducing jitter at the data line is of second importance
Place the clock close to the DAC, feed back that clock to the drive, eventually clocking the EXOR gates there.
Eventually reclock the data just before it enters the DAC chip
lower jitter = better
cheers |
Is there a way to clocking the EXOR gates ? How?
:confused:
I edited my previous post , sorry.
In my set up ALL the signals enter a XOR just after the saa7310 , and then via cable they reach the dacs .For me this plays better than the recloker just before the dacs(outside the players) and without the buffers.
Thanks , BTW your XO is VERY FINE.
Anael , there is not a problem with the 1545/D1 . I have a Philips CDP with 1545 inside and will see what voltage it works at the output . I'll tell you soon. |
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| nar |
You know I already tried ... I fried a resistor 10ohms on the IV stage . Problem seemed to be the DC existing at the current out of the 1545, pputting it on the source of the mosfet seemed to cause problem...how would you do ?
regards
anael |
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| stefanobilliani |
| quote: | Originally posted by Andypairo
C'mon Stefano,
don't be shy!
This topic deserves a thread of his own, so.. just post it ;)
Cheers
Andrea |
Oh my....:rolleyes: |
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| stefanobilliani |
| quote: | Originally posted by nar
You know I already tried ... I fried a resistor 10ohms on the IV stage . Problem seemed to be the DC existing at the current out of the 1545, pputting it on the source of the mosfet seemed to cause problem...how would you do ?
regards
anael |
Philips set the 1545(A) at 3.27 volts in its CDplayers.
The DC voltage is not a problem .Also 0 volts is a voltage , isn'it?
It is just that the D1 has to be modified so that you can trim the SOURCE voltage to the required level , in this case is 3.27 volts;
for example 1543 works good at 2 volts or so. |
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| nar |
Thanks :)
Will try it :devilr:
R |
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| stefanobilliani |
| quote: | Originally posted by stefanobilliani
Philips set the 1545(A) at 3.27 volts in its CDplayers.
The DC voltage is not a problem .Also 0 volts is a voltage , isn'it?
It is just that the D1 has to be modified so that you can trim the SOURCE voltage to the required level , in this case is 3.27 volts;
for example 1543 works good at 2 volts or so. |
edit: with cascode output stage you can leave the Vref pin disconnected.
:) |
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| stefanobilliani |
Becouse it is Cascode that set the voltage itself , and IT DOES NOT care what is the current at Vref . It is not theory BTW but observation.
:cool: |
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| nar |
I've tried to start a better layout
Takes time :smash:
Guido what do you think ? is it better ? |
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| Bricolo |
| Guido, what's best in series with the power supply, a resistor or a ferrite bead? |
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| rfbrw |
| quote: | Originally posted by nar
The One and Only ... after all we use one of his modules :cool: |
The Pass D1 dac uses a digital filter so it has no delay but still Nelson Pass is a good a person to ask as any. BTW If the delay did not matter the large manufacurers would probably still using a single dac switched between the channels.
As for getting rid of the delay there are two possiblities. The simplest and most acceptable to the clock fetishists is the large shift register. Alternatively, you can take advantage of the fact that it is possible to stop the clock on the PCM1702 and have the data remain in situ. There is circuit in the forum somewhere by rah that can be modified to do this.
| quote: | Originally posted by Ulas
I find this thread very amusing. Here we have all the diyAudio digital “experts” picking nits and no one sees the big problem with Nar’s design.
ray
Nar, before you make any PCBs I suggest you do a thorough timing analysis of your design. |
Come on Ulas, put us all out of our misery. |
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| jean-paul |
| quote: | | BTW If the delay did not matter the large manufacurers would probably still using a single dac switched between the channels. |
Ah, the days of sample-and-hold circuits and HEF4053 come to mind ;) |
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| Ulas |
| quote: | Originally posted by rfbrw
Come on Ulas, put us all out of our misery. |
Where’s the fun in that? Ordinarily I wouldn’t comment but, because Nar is a fellow musician and newbie DAC designer, I thought I would give him a heads up. It probably wouldn’t hurt you to learn how to do a simple timing analysis. |
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| rfbrw |
| quote: | Originally posted by Ulas
Where’s the fun in that? Ordinarily I wouldn’t comment but, because Nar is a fellow musician and newbie DAC designer, I thought I would give him a heads up. It probably wouldn’t hurt you to learn how to do a simple timing analysis. |
If you feel the need for a timing analysis, go a head but I have never needed more than a functional simulation at these speeds.
I have no idea of what you think you see but at these glacial speeds LS logic would probably suffice and anyone one who needs a timing analysis for something as simple as this ought to hang their head in shame. |
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| nar |
Come on guys , I don't see why it should bother for another reason than PRINCIPLES
But yes I would like someone to learn me how to do a timing analysis :clown:
I WOULD think that nobody is able to hear or feel disturbed by a interchannel delay of one echantillon ... 11µS is short isn't it :D
I am triying to apply Guido's headlines to the PCB
I go now in doublesided PCB and things are horrible but I try to make everything shortest :xeye:
Not evident for the beginner :headshot:
Could you comment the try ? Thanks
And to Ulas : you would say that all experts don't see the BIG problem that you see in the design ? Appart delay , what would it be ? The fact I trust the SPDIF clock ??:confused: |
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| Ulas |
| quote: | Originally posted by nar
But yes I would like someone to learn me how to do a timing analysis :clown: |
It’s very simple: The big problem I see comes from using the falling edge of SCLK to clock the HC164 and the PCM1702. The falling edge of SCLK is what the CS8412 uses to clock its internal shift register and the state of SDATA is unstable for up to 20ns after that edge.
The HC164 wants its data input stable from 20ns before the clock and continuing 5 ns after the clock. Those conditions cannot be met. The active edge of the HC164 clock latches the new input data and shifts the internal bits to the next stage. As a result, the data outputs are unstable for up to 35ns after that edge.
The PCM1702 wants its data stable for 20ns before and after the active clock edge. Those conditions cannot be met. The PCM1702 also doesn’t want to see the falling edge of LE within 15ns of the rising edge of its clock. That condition cannot be met because the CS8412 guarantees FSYNC to be coincident with the falling edge of SCLK +/- 20ns.
Everything above comes directly from the chip data sheets. While it’s true the published setup and hold times are very conservative, it never hurts to follow the specs, especially if this is your first design effort. It also wouldn’t hurt if you used the chips as they were intended to be used. The CS8412 in mode 2 is intended to be directly connected to an I2S DAC; clock to clock and data to data. The PCM1702 is not I2S.
A better choice would be to use the CS8412 in mode 6 and connect clock to clock, data to data, and delay FSYNC two clock periods while preserving its phase relative to SCLK. That way the data is transferred on the rising edge of the clock, which is what the chip designers intended. It also reduces the chip count and simplifies the PCB layout. Don’t worry about the picayune suggestions of the “experts” until you learn more and are ready for your next project. |
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| nar |
Very impressive . Your explanations are clear like mountain spring water....:)
I think we are going to have a discussion about it , and we 'll see what we can do with it :xeye:
It seems to be more simpler to do it like this :devilr:
Anyway I hope we won't have to re-clock everything
I spent hours on the PCB layout and it is not:headshot:finished !
What do you think about the CS8412 and its associated components layout ?
Best regards
Anael |
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| stefanobilliani |
| quote: | Originally posted by Guido Tent
Hi
With respect to jitter:
- The conversion clock of the DAC is most important
- Reducing jitter at the data line is of second importance
Place the clock close to the DAC, feed back that clock to the drive, eventually clocking the EXOR gates there.
Eventually reclock the data just before it enters the DAC chip
lower jitter = better
cheers |
Guido Tent ,
if I use 4 flip flops for reclocking the 4 lines (BCK WS DATA+ DATA-) may the Tent clock have problems feeding the 4 FF gates + the saa7310?If yes , then it should be simple reclocking just the BCK and WS . |
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| Guido Tent |
| quote: | Originally posted by stefanobilliani
Guido Tent ,
if I use 4 flip flops for reclocking the 4 lines (BCK WS DATA+ DATA-) may the Tent clock have problems feeding the 4 FF gates + the saa7310?If yes , then it should be simple reclocking just the BCK and WS . |
Yes, correct observation
Clock the DACs directly from TentLabs clock, and feed 1 inverter as well (that's 3 gates in total), using series resistances in all lines.
The output of the inverter in turn feeds 4 others, these feeding the reclocking.
Use as much as possible single packages, preferably picogates
cheers |
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| Bricolo |
| what value for the series resistance? |
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| stefanobilliani |
| quote: | Originally posted by Guido Tent
Yes, correct observation
Clock the DACs directly from TentLabs clock, and feed 1 inverter as well (that's 3 gates in total), using series resistances in all lines.
The output of the inverter in turn feeds 4 others, these feeding the reclocking.
Use as much as possible single packages, preferably picogates
cheers |
Bricolo, 47ohm colse to the XOto each line - max 3 lines/gates.
Guido Tent,
I will , if understand well, clock the saa7310(line1) and an inverter(line2) . Since the dac is NONos there will not be 3rd line.
But then the 4 FF gates will take the clock from the inverter? |
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| Bricolo |
| quote: | Originally posted by stefanobilliani
Bricolo, 47ohm colse to the XOto each line - max 3 lines/gates.
Guido Tent,
I will , if understand well, clock the saa7310(line1) and an inverter(line2) . Since the dac is NONos there will not be 3rd line.
But then the 4 FF gates will take the clock from the inverter? |
that's how I understand Guido Tent's post
the clock will drive (with a resistance for each (47R ?))
-the 2 dacs
-an inverter
This inverter feeds 4 other inverters, and those drive the FF |
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| stefanobilliani |
I think the point is that the 74HC74 FF contains 2 FF par chip and they are 2 clock gates par FF. I will go finally for the 74VHC374N that has 1 gate for clock and 7(?) FF in one chip.
For example see the great thread http://www.diyaudio.com/forums/show...&threadid=23044 by rbroer .
I have lingered upon the 74HC74 just becouse they have the inverted output, but I am convinced that the inverter is better implemented outside and before the FF. |
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| Bricolo |
| quote: | Originally posted by stefanobilliani
I think the point is that the 74HC74 FF contains 2 FF par chip and they are 2 clock gates par FF. I will go finally for the 74VHC374N that has 1 gate for clock and 7(?) FF in one chip.
For example see the great thread http://www.diyaudio.com/forums/show...&threadid=23044 by rbroer .
I have lingered upon the 74HC74 just becouse they have the inverted output, but I am convinced that the inverter is better implemented outside and before the FF. |
I only see 1 clock input per FF, so 2 per chip
You're right, the 374 will simplify the layout. But I'm not sure about the performance (Guido Tent advices to use only 1 FF per chip) |
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| stefanobilliani |
| quote: | Originally posted by Bricolo
I only see 1 clock input per FF, so 2 per chip |
Oh yeah!I meant 2 clock par chip ,
:devilr: | quote: | Originally posted by Bricolo
You're right, the 374 will simplify the layout. But I'm not sure about the performance (Guido Tent advices to use only 1 FF per chip) |
Bah... in a previous post Guido Tent said| quote: | | Originally posted by Guido Tent Use as much as possible single packages, preferably picogates |
and I believe to have 4 chips that runs at 11Mhz is not that simple too (at least for a diy)... ... ... |
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| guido |
Had a look at the 7310 datasheet. No info on timing between 11MHz clock input and I2S output. Guess you need a fast dual scope to see if the I2S data changes on rising or falling edge of 11MHz. To repeat myself, you don't want to have the 7310 changing the I2S lines at the time the FF clocks the lines.
gr |
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| Elso Kwak |
| quote: | Originally posted by Guido Tent
Yes, correct observation
Clock the DACs directly from TentLabs clock, and feed 1 inverter as well (that's 3 gates in total), using series resistances in all lines.
The output of the inverter in turn feeds 4 others, these feeding the reclocking.
Use as much as possible single packages, preferably picogates
cheers |
Guido, What's so special about these picogates? I did not see them in your XO-3.
:confused: |
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| Zodiac |
| quote: | | You're right, the 374 will simplify the layout. But I'm not sure about the performance (Guido Tent advices to use only 1 FF per chip) |
| quote: | | Bah... in a previous post Guido Tent said Use as much as possible single packages, preferably picogates |
Guido is talking about inverters. You should try not to use more than one inverter in a package because supply rejection is very poor, like 6db. Hence, picogates can be used, if you can solder the bl**dy things... |
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| Bricolo |
| So, the supply rejection of other logic (FF, XOR, counters...) is far better than the pssr from an inverter? |
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| Elso Kwak |
| quote: | Originally posted by Zodiac
Guido is talking about inverters. You should try not to use more than one inverter in a package because supply rejection is very poor, like 6db. Hence, picogates can be used, if you can solder the bl**dy things... |
Supply rejection of Picogates is better then???
The smallest thingy I can solder is SOT23.
:confused: |
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| Bricolo |
Don't know if theyr PSSR is better, but theyr advantage is clear: if you need only one gate, you don't have to use a DIL14 package with 7 unused ones.
But they are smd :( |
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| stefanobilliani |
| quote: | Originally posted by guido
Had a look at the 7310 datasheet. No info on timing between 11MHz clock input and I2S output. Guess you need a fast dual scope to see if the I2S data changes on rising or falling edge of 11MHz. To repeat myself, you don't want to have the 7310 changing the I2S lines at the time the FF clocks the lines.
gr |
More than one time I had the feeling 7310 prefear an phase inverted clock in combination with a FF sinchronous mode.Earlier , using the Kwak clock I was feeding the 7310 in the "right" line and the FF with the "inverted" one. In that respect I still think thingswas going in a different way.
Now , the idea (of yours)is to use an inverter after the Tentlabs clock to feed the 7310 and use the right one for the FF, with respect to jitter. I have the XOR at the moment and I will try with it and report later.
Thanks. |
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| Guido Tent |
| quote: | Originally posted by Bricolo
Don't know if theyr PSSR is better, but theyr advantage is clear: if you need only one gate, you don't have to use a DIL14 package with 7 unused ones.
But they are smd :( |
Hi
PSRR is equal, but picogates have less inductances so less groundbounce induced jitter
In addition, they contain one inverter only, so interaction to others is fully in your control, whereas 6 inverters in one package are a drama in that aspect
regards |
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| Elso Kwak |
| quote: | Originally posted by Guido Tent
Hi
I like simple schematics, though it is nt a goal as such
The jitter at pin 12 (8412) is too high, lower it, your ears will like it
To start, seperate the supply at pin 7 and pin 22, at least by using a ferrite bead in pin 22, and a resistor (say 22 ohm) at pin 7. Better, build a low noise supply for pin 7
Then attack the 8412 loopfilter, by rducing the resistor to 500 ohm, and quadruppling the cap to 220 nF. You may take that even a step further, if you like
Then add a cap (10nF) at pin 20, it is next to pin 19 which puts out 11.2896 MHz. The silicon layout guy at Crystal must have been drunk when he did this.
Why do you use 10k in series from pin 12 ? I like series resistors, but they are missing in the rest of your circuit.
You may want to add ferrite beads in the supply lies rom the other logic as well
succes |
Guido, So in fact you are proposing a modification of the Wildmonkeysects loopfilter by going from 3n3 to 10nF.....
http://db.audioasylum.com/cgi/m.mpl...412&r=&session=
:eek: |
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| Zodiac |
| quote: | Originally posted by Guido Tent
Hi
PSRR is equal, but picogates have less inductances so less groundbounce induced jitter
In addition, they contain one inverter only, so interaction to others is fully in your control, whereas 6 inverters in one package are a drama in that aspect
regards |
PSRR equal between standard DIL inverters and picogates.
What do you mean by "interaction to others". Isn't this related to power supply issues, i.e. ground spikes due to switching CMOS logic? Obviously you can better control this in separate picogates... |
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| stefanobilliani |
| quote: | Originally posted by guido
Had a look at the 7310 datasheet. No info on timing between 11MHz clock input and I2S output. Guess you need a fast dual scope to see if the I2S data changes on rising or falling edge of 11MHz. To repeat myself, you don't want to have the 7310 changing the I2S lines at the time the FF clocks the lines.
gr |
OK Done! The saa7310 -if its clock is inverted with respect to the sinchronous flip flop-works better or play music better.The differences are more than audible , you can almost touch they!
This is out of question.There is more differentiations in the mixing plans, and the bass...not...the entire specrum of frequencies losts that sense of compression previously experienced.This come down to better dinamics.
This change is quite resolutive, now I have to search for suggestions about the choice of gates,packages, flip- flop etc.
Thanks! |
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| guido |
| quote: | Originally posted by stefanobilliani
OK Done! The saa7310 -if its clock is inverted with respect to the sinchronous flip flop-works better or play music better.The differences are more than audible , you can almost touch they!
This is out of question.There is more differentiations in the mixing plans, and the bass...not...the entire specrum of frequencies losts that sense of compression previously experienced.This come down to better dinamics.
This change is quite resolutive, now I have to search for suggestions about the choice of gates,packages, flip- flop etc.
Thanks! |
No, the 7310 does exactly the same if you feed it with equal or inverted clock. The problem is what happens at the flipflop:
Suppose the I2S signals change on clock going 0 to 5 at the 7310 and the same happens at the FF: it reads the I2S on the inputs on clock going 0 to 5. So the inputs are not stable when the FF is reading them because the 7310 is changing them.
With clock inverted to 7310 you change the moment that the data changes at the input of the FF: it changes when clock goes 5 to 0 and the FF still reads at 0 to 5. Then you have 44nanoSec between those moments.
The above is based upon your experience, not on measurements!
(i have a scope, but it is single channel, sixties tube stuff with 1MHz bandwith :D :D )
mvg, |
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| stefanobilliani |
| quote: | Originally posted by guido
No, the 7310 does exactly the same if you feed it with equal or inverted clock. The problem is what happens at the flipflop:
Suppose the I2S signals change on clock going 0 to 5 at the 7310 and the same happens at the FF: it reads the I2S on the inputs on clock going 0 to 5. So the inputs are not stable when the FF is reading them because the 7310 is changing them.
With clock inverted to 7310 you change the moment that the data changes at the input of the FF: it changes when clock goes 5 to 0 and the FF still reads at 0 to 5. Then you have 44nanoSec between those moments.
The above is based upon your experience, not on measurements!
(i have a scope, but it is single channel, sixties tube stuff with 1MHz bandwith :D :D )
mvg, |
Thanks , say... lets change the subject :D of the phrase :D
Of course I agree that the 7310 does the same work ... is the combination that counts...but...
:confused: what do you think is the best one?:confused:
:devilr: |
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| nar |
Sorry gentlemen :smash:
We have changed a little the DAC design ( originally what this thread was open for ) ;)
Of course feedback IS welcome
We would like to thank : Guido and Ulas for their great help :) making us understand our errors
The PCB is under last preparation phase . We design a good PSU for that , and the IVs are ready :angel:
Best regards
Anael |
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| f.k.l.chan |
| Thanks Nar, i found somewhere to use my PCM1702...finally:D |
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| nar |
f.k.l chan :
Thanks for subscribing to the thread . Alas if you construct the DAC as it is posted in the last state , it probably will work but not optimally .
We are beginners so we sometimes don't understand things untill bottom is reached . We are preparing another schematic , and I hope to post it tonight .
But the power supply is ready
:)
We made it strong and healthy , with lots of Pi filtering and separate for digital and analog domains .
The IV conversion module is ready too :) it is the one found in Nelson's D1 except it works unbalanced ;)
I'll try to post them tonight too .
best regards
Anael |
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| nar |
| OK so let's go for IV :cool: |
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| nar |
OK so now it's 2 o'clock AM , I 've just finished the schematic that should WE HOPE SO ! work . I am exhausted and have worked from 5 PM to now on the schematic , put it into shape and convert it. The PCB is almost ready , without the ground plane for now .
But we might go for a dual layer type one . So we could shorten to max . the critical links ( FSYNC,SCK,SDATA ) . We are not quite sure .There is no problem to concept it on 2 sides but hell. A lot of work though :devilr: :smash: :smash: :smash:
Should go to ZZZZZZZZZZZZZZ
Regards
Anael |
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| nar |
A long time since ....
We've not lost hope to do it one day with my friend Borsa . Problem is we have lots of other obligations to make our living , and things are never easy .
We've also thought of an Aleph X version using devices solely biased at their thermal indifference point .
We thought it could be a good experience to make a prototype , with perhaps !!!! beter sound than the XA's series . Although not sure , it is worth and fun trying
We would choose some 2SK214 for the differential , at 20mA each and some IRF9610 for the output mosfets , polarized at their thermal equilibrium point , roughly 180mA , with 30 V rails . We believe the 9610s are wonderful components , and the 610 doesn't permit the thermal equilibrium option ( bias too high ) . To get the power we will use 15 9610 in parallel on each output stage , means a total bias of 5,4 A for the amp , will lead to a 100 W /8 ohms "that should prefer high speaker impedances" , but hell anybody can adapt it its own way ...
To get back again to the DAC , we've made a dual layer print , so that anyone that has time can try it :hot: :hot: :hot:
Regards ,
Anael
F.K.L chan , I will send you everything so you can try out ;-)
The files totalize 1,79MO , I can' reduce , so if someone has a mirror , and wants to get the files , please mail me . |
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| Elso Kwak |
| quote: | Originally posted by nar
A long time since ....
We've not lost hope to do it one day with my friend Borsa . Problem is we have lots of other obligations to make our living , and things are never easy .
We've also thought of an Aleph X version using devices solely biased at their thermal indifference point .
We thought it could be a good experience to make a prototype , with perhaps !!!! beter sound than the XA's series . Although not sure , it is worth and fun trying
We would choose some 2SK214 for the differential , at 20mA each and some IRF9610 for the output mosfets , polarized at their thermal equilibrium point , roughly 180mA , with 30 V rails . We believe the 9610s are wonderful components , and the 610 doesn't permit the thermal equilibrium option ( bias too high ) . To get the power we will use 15 9610 in parallel on each output stage , means a total bias of 5,4 A for the amp , will lead to a 100 W /8 ohms "that should prefer high speaker impedances" , but hell anybody can adapt it its own way ...
To get back again to the DAC , we've made a dual layer print , so that anyone that has time can try it :hot: :hot: :hot:
Regards ,
Anael
F.K.L chan , I will send you everything so you can try out ;-)
The files totalize 1,79MO , I can' reduce , so if someone has a mirror , and wants to get the files , please mail me . |
Hi I did not get connection to your www site. Please send me the file.:bawling: |
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