| pjacobi |
This is for the SPICE modeling related discussions, which started in the "Borbely Fet Follower" thread.
Let's avoid annoying the thread starter and others, who want to see practical issues, real circuits, discussed in that thread.
Regards,
Peter Jacobi |
|
|
| pjacobi |
Hi Frederico, All,
| quote: | Originally posted by pjacobi
.model 2sk170 NJF(Beta=51.76m Rs=8.008 Rd=8.008 Betatce=-.5 Lambda=11.22m
+ Vto=-.5275 Vtotc=-2.5m Cgd=18.28p M=.3367 Pb=.3905 Fc=.5
+ Cgs=20.07p Isr=112.8p Nr=2 Is=11.28p N=1 Xti=3 Alpha=10u Vk=100
+ Kf=92.85E-18 Af=1) |
| quote: | Originally posted by fscarpa58
using Micro-Cap 7
you can obtain
the 3 curves of post #60
with any generic njfet model
by putting IS= 1n , 15 p, 10F
respectively for curves 1,2 and 3.
I think gate current is not well
modelled here
I am disappointed
|
I've cross-checked with AIMSpice. Results are in agreement with Micro-Cap 7 results, i.e. not satisfactory.
Actually looking at the diagnostics, I can see that about half of the parameters are rejected as unknown. So there's no big guess, what 's happening.
Seems LTSpice is state-of-the-art regarding JFET modeling.
Regards,
Peter Jacobi |
|
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| pjacobi |
Hi Christer,
| quote: | Originally posted by Christer
For instance, with 10kHz 5V pk input, I got -94dB 2nd order
and -117dB 3rd order. With 100mV pk input I got basically no
visible distorsion above the -155dB noise floor of the FFT.
Those are just simulation figures, but they seem promising.
|
If you operate a x1 stage at +-24V, and you don't do something really strange, it's nearly impossible to get worse than -150dB for 100mV pk signals.
O.K. There may be a bareley visible K2 spike. But everything above starts at least with a bonus factor of 1/240 * 1/240 before even taking anything into account that makes the circuit well-behaved.
Regards,
Peter Jacobi |
|
|
| Christer |
Peter,
You started this thread before I made my recent post in the original
thread. As I pointed out there, Spice modelling was not really the
issue, but other people seemed to make it the issue, or assume it
was the issue. As I also said there, the distorsion figures should be
taken with a very large grain of salt. I think we can expect a real
circuit to have at least as much distorsion, but otherwise I am not
sure if we know much. I do think distorsion analyses in Spice can
serve a purpose for comparative purposes of the kind we discussed
in the Diamond buffer thread, but that is an assumption.
Just for the record, I see you put "Borbely FET follower" in the thread
title. Actually, the circuit wasn't one of Borbelys' but rather what I
understand to be John Curls own variant of the White follower. |
|
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| pjacobi |
The riddle of the gate current simulation differences is solved.
It's the JFET impact ionization current, see:
http://www.google.com/search?hl=en&...G=Google+Search
Its modeling appeared first in PSPICE and didn't migrate to all other SPICES.
Reading the name alone, it should best be avoided, I assume. Which correlates with the practitioners' advice seen in the mother thread.
Regards,
Peter Jacobi |
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| fscarpa58 |
Hi
Thanks Peter for the search
However I think that static curves of
ID versus VDS are more important in
distortion analysis. look at the difference
between M-Cap and the Toshiba sheets
Amazing
Federico
Toshiba curves |
|
|
| fscarpa58 |
MicroCap curves
I think it will be better to use
pentode models
Federico |
|
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| pjacobi |
Hi Federico, All,
| quote: | Originally posted by fscarpa58
[...]
However I think that static curves of
ID versus VDS are more important in
distortion analysis. look at the difference
between M-Cap and the Toshiba sheets
[...] |
JFETs, the neglected stepchild of SPICE modeling?
Perhaps some advanced MESFET models can be abused for better results, when it is possible to selectively disable the GaAs specific effects.
Anyway, careless parameter extraction is to blame for the huge differences seen in your posts.
Compare these Philips models with the datasheets:
.MODEL BF245A NJF(VTO=-1.7372 BETA=1.16621E-3 BETATCE=-0.5 LAMBDA=1.77211E-2
+ RD=9.01678 RS=9.01678 CGS=2.20000E-12 CGD=2.20000E-12 PB=7.80988E-1 IS=2.91797E-16 XTI=3 AF=1
+ FC=0.5 N=1 NR=2 MFG=PHILIPS)
.MODEL BF245B NJF(VTO=-2.3085 BETA=1.09045E-3 BETATCE=-0.5 LAMBDA=2.31754E-2
+ RD=7.77648 RS=7.77648 CGS=2.00000E-12 CGD=2.20000E-12 PB=9.91494E-1 IS=2.59121E-16 XTI=3 AF=1
+ FC=0.5 N=1 NR=2 MFG=PHILIPS)
.MODEL BF245C NJF(VTO=-5.0014 BETA=5.43157E-4 BETATCE=-0.5 LAMBDA=2.71505E-2
+ RD=1.20869E1 RS=1.20869E1 CGS=2.00000E-12 CGD=2.00000E-12 PB=1.24659 IS=3.64346E-16 XTI=3 AF=1
+ FC=0.5 N=1 NR=2 MFG=PHILIPS)
This almost makes sense, doesn't it? Add impact ionization current to prevent designers setting Vds too high, and the models would be good enough for most simulations.
Compare with power BJTs. Almost no models implement quasi-saturation. Didn't stop us from using them. Hexfets? If used in class B amplifiers, devices spend signifant part of the cycle in weak inversion, but you'll find models which doesn't model diffusion current at all!
Regards,
Peter Jacobi |
|
|
| Christer |
Peter,
Although I haven't really investigated that many manufacturers
models, my impression is that also BJT model are often mediocre
at best when compared to the datasheets. I spent quite some
time about a year ago trying to DIY models for some BJTs I couldn't
find any Spice models for. I tried to really understand the Spice
equations as described in my, admittely somewhat old, semiconductor
physics book, and figure out both by theoretical thinking and by
epxeriments with tweaking parameters how to create a good model.
It may be my due to limitations in my understanding, but I really
couldn't find any way either in theory or in practice to come up
with a suffciently good general-purpose model of any of these
BJTs. I ended up having to make a compromise fitting neither of
the most importand diagrams really well nor any of them
really bad. Some improvement could be achieved if tailoring the models
to the intended operating conditions, but some parameters seem
still impossible to model well. I couldn't find any way to get the
high injection effects (beta droop) as serious as often indicated
in the datasheets. There might be further parameters in some
modern Spice implementations that improve on this, but if so
they seem not to be standard Spice 3. |
|
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| pjacobi |
Hi Christer,
| quote: | Originally posted by Christer
[...] my impression is that also BJT model are often mediocre
at best when compared to the datasheets. [...] but I really
couldn't find any way either in theory or in practice to come up
with a suffciently good general-purpose model of any of these
BJTs. [...] I couldn't find any way to get the
high injection effects (beta droop) as serious as often indicated
in the datasheets.[...] |
You've done something I always planned to but it never got the top of priority list. As always I'll comment anyway.
- Not perfectly modeling beta droop shouldn't be a problem, as it is easy to operate all your devices below the F(transit) peak (in DIY, as you don't have to optimize your part cost)
- You have IKF, base and collector resistances as the most straightforward ingredients to model beta droop. Want to share one your attempts? I'll have a look on it.
- OTOH you can't avoid quasi-saturation, I'll consider this much more problematic
- If you have time and a C compiler at hand, you can experiment with the Philips MEXTRAM model for BJT:
http://www.semiconductors.philips.c...ipolar/mextram/
Regards,
Peter Jacobi |
|
|
| Christer |
| quote: | Originally posted by pjacobi
You've done something I always planned to but it never got the top of priority list. As always I'll comment anyway.
- Not perfectly modeling beta droop shouldn't be a problem, as it is easy to operate all your devices below the F(transit) peak (in DIY, as you don't have to optimize your part cost)
- You have IKF, base and collector resistances as the most straightforward ingredients to model beta droop. Want to share one your attempts? I'll have a look on it.
|
I ended up with the following models for some drivers. I am not
saying they are the best compromises, but I found I eventually
had to settle on something. Further tweaking of the models may
be worthwhile for a particular usage I suppose. I suppose some
parameters may be way off, but the main purpose was to try
mimicing the datasheets in an acceptable way, so the end results
was what mattered most to me.
.model 2SD669 NPN (IS=5p NF=1 BF=250 ISE=5p NE=1.5 IKF=3 VAF=150 RB=1 RC=0.25 RE=0.25 TF=1.14ns CJC=50p )
.model 2SB649 PNP (IS=5p NF=1 BF=250 ISE=10p NE=1.5 IKF=3 VAF=75 RB=1 RC=0.25 RE=0.25 TF=1.14ns CJC=50p )
.model 2SC4793 NPN (IS=0.1p BF=130 NF=1 ISE=0.1p RB=1 RE=0.1 RC=0.2 VAF=500 IKF=3 TF=1.6ns CJC=100p )
.model 2SA1837 PNP (IS=0.1p BF=130 NF=1 ISE=0.1p RB=1 RE=0.1 RC=0.2 VAF=500 IKF=3 TF=2.28n CJC=150p )
I know there is at least one book about making Spice models, but
I haven't read it, just worked from the theory in my old course
book. |
|
|
| john curl |
| The Mcap curve sucks! It is not reality. |
|
|
| andy_c |
| quote: | Originally posted by Christer
I know there is at least one book about making Spice models, but
I haven't read it, just worked from the theory in my old course
book. |
Christer,
Here's the link to Massobrio and Antognetti.
http://www.amazon.com/exec/obidos/t...=glance&s=books
The whole issue with models can get quite discouraging. I recently worked with a guy that was responsible for the code of a harmonic balance simulator. It can do intermods with a large number of tones. He was extending the software to use SPICE models for devices in addition to the native models for the simulator. The harmonic balance simulator is very sensitive to discontinuities in the equations for the device characteristics. It fails to converge in the presence of certain types of discontinuities. He had to completely abandon the use of level 1, level 2 and level 3 MOSFET SPICE models because of convergence problems due to discontinuities. So I suspect that SPICE distortion simulations with these devices will indicate a lot of high-order harmonics that are just artifacts of the discontinuities in the models.
In looking at distortion simulations for a power amp using MOSFET drivers and output stage, I was disappointed to find out that the level 1, 2 and 3 MOSFET models model the gate-to-drain capacitance as constant with gate-to-drain voltage. This is completely wrong for vertical MOSFETs. So I'm looking at trying to fit the LTSpice VDMOS model to the data sheet parameters. I'd like to find out how much the nonlinear gate-drain capacitance of the MOSFET drivers affects the distortion, and what kind of improvement I might expect by bootstrapping the drain to the level-shifted output voltage a la Halcro. But this is very time-consuming! Right now, other responsibilities prevent me from taking the time to do this, but I will get there eventually. |
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| Pedja |
| quote: | Originally posted by john curl
The Mcap curve sucks! It is not reality. |
It is the model. SwCAD shows the similar curves. But no problem, keep the Vds constant in your circuit, and you have the model. ;)
Pedja |
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|
| Pedja |
This does not seem that bad?
(MicroCap plot for Vds=10V) |
|
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| pjacobi |
Hi Pedja, All,
| quote: | Originally posted by Pedja
It is the model. SwCAD shows the similar curves.
[...] |
Three graphs, three problems.
a) IGSX / VDS => SPICE version problem, only some SPICEs model the impact ionization current at all.
b) ID / VDS => Sloppy models, compare the BF245 models.
c) ID / VGS => Bad theory, this looks too good, as it looks rather quadratic. Despite endless repititions this ain't right. Compare formulas 3-11 and 3-12 in Massobrio/Antognetti. And the datasheet curves.
Regards,
Peter Jacobi |
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|
| fscarpa58 |
| quote: | Anyway, careless parameter extraction is to blame for the huge differences seen in your posts.
Compare these Philips models with the datasheets: |
I did it.
Look at the following 3 sets of curves referring to BF245C
1) from philips
2) from Micro-Cap
3) drawn using a pentode model with parameter fitting
made manually in five (5) minutes
Yes, it is not perfect, but with more time I am sure to
obtain near perfect curves.
I think spice model developers
have to work more and better.
Any comment ?
Federico |
|
|
| pjacobi |
Hi Federico,
Very impressive comparison!
| quote: | Originally posted by fscarpa58
[...]
3) drawn using a pentode model with parameter fitting
made manually in five (5) minutes
[...]
|
Will you make this available? Which pentode model are you using?
| quote: | Originally posted by fscarpa58
I think spice model developers
have to work more and better.
|
IMHO there is a problem with the monolithic architecture of SPICE. Either you have to recompile the whole mess to add a new model or you are confined to what's possible with subcircuit models.
If it would be possible to add experimental models as seperately compiled modules (DLLs) or if a reasonable fully featured programming language interpreter would be included (Javascript, Python, whatever), it would be much easier to tinker around and try things and share improved models.
The ngSpice project had this on its agenda, but it seems to be abonded: http://geda.seul.org/tools/ngspice/
Regards,
Peter Jacobi |
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| fscarpa58 |
Hi Peter
It is the classic pentode model slightly modified
to account for the square law of FETs.
Actually overparameterized, you can move
k inside the brakets and so avoid a parameter.
Federico |
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| fscarpa58 |
obviously the term 2/pi can be incorporated in k.
Thus, four parameters.
It doesn't model leakage gate current but I am working
on it.
It is valid only in the first quadrant ( functions like
pow(), pwr(), pwrs() have to be used).
F |
|
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| pjacobi |
Hi Federico,
| quote: | Originally posted by fscarpa58
It is the classic pentode model slightly modified
to account for the square law of FETs.
|
Thank you for giving the formula and the parameters.
I see two problems with using this formula for FETS
a) I'll guess IDS/VDS => 0 as VDS => 0. In the FET this should have a non-zero limes.
b) the square law isn't a square law
Nevertheless the pragmatic fitting is great!
The level 1 FET model just stitches three different functions together, if using instead a continuous blending function like atan, things would looks nicer. But I'll have to read more about higher level FET models to see if anything there can be re-used for JFETs.
Regards,
Peter Jacobi |
|
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| fscarpa58 |
| quote: | a) I'll guess IDS/VDS => 0 as VDS => 0. In the FET this should have a non-zero limes.
b) the square law isn't a square law |
Hi
I just tried, IDS/VDS has a finite, non-zero, limit if VDS tends to zero as you can see in the attached pic.
Regarding the square law the problem
can be faced by using the variant from
Koren.
regards
Federico |
|
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| Pedja |
| quote: | Originally posted by pjacobi
Compare formulas 3-11 and 3-12 in Massobrio/Antognetti. And the datasheet curves. |
Peter, sorry, I do not have that book so can not know what you are referring to. Curve matches to the datasheet (below) very well, that is why I posted it. Many models are doing here just fine.
| quote: | Originally posted by fscarpa58
I think spice model developers
have to work more and better.
Any comment ? |
I am interested in SPICE only like a user, but generally I would say :nod:.
And comment on the findings you posted is: excellent work!
Slightly out of topic, but one parallel with bjt models: similarly to JFETs, many of them have wrong (too good) Ic/Vce characteristic and I guess this is (one of) the reason why harmonic distortion often looks lower in the simulators than in the real world. Well modeled hFE/Ic is also rather exception than rule.
Pedja |
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| fscarpa58 |
II agree with your statement about
BJT, Pedja ( and thanks for your appreciation).
However I have to admit my ignorance
about this subject. BJT modeling is more
difficult for me owing to the presence of a
significant base current.
So, I feel more familiar with tubes and FETs.
Regarding tubes, I have to say that models are, in
general, quite good (at least using Koren approach).
I always observed great correlation between the
real distortion spectrum and the simulated one.
Regarding the analysis of the ID versus VGS curves, I think
(my opinion) that it is not a good way to judge
a model. The ID vs. VDS curves are
a better one.
Regards,
Federico |
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| pjacobi |
Hi Federico, Pedja, Christer, Lurkers,
Had some day work to do, so that I can't fully address all topics raised so far. So only some short comments:
*** a) Pentode model adapted for JFETs ***
If this is the homegrown JFET model contest, where shall we send the entries to, and what's the price?
For a direct comparison of the SPICE level 1 model, and two alternatives which smoothly interpolate, look at this deck:
* JFET models
V1 D 0 0
V2 G 0 0
B1 0 D I=12m*2/pi*atan(pi/4*V(D,0)/(V(G,0)/3.9+1.0))*(V(G,0)/3.9+1.0)**2*(V(D,0)+200)/200
B2 0 D I=12m*tanh(0.5*V(D,0)/(V(G,0)/3.9+1.0))*(V(G,0)/3.9+1.0)**2*(V(D,0)+200)/200
B3 0 D I=12m*(V(D,0)+200)/200*if(V(D,0)<V(G,0)+3.9,V(D,0)/3.9*(2*(V(G,0)/3.9+1)-V(D,0)/3.9),(V(G,0)/3.9+1.0)**2)
.dc V1 0 24 10m V2 0 -3 -1
.end
B1 is SPICE level1, B3 is much like the pentode, B2 is another interpolation nearer to B1. All matched to coincede for VDS=>0 and VDS=>inf.
This is for a JFET with VGSoff=3.9V, IDSS=12mA and pseudo-Early voltage of 200V (some similarity with BF556B).
*** b) square law or not ***
(3-11 and 3-12 in Massobrio/Antognetti)
3-12: IDS = IDSS * (1 - VGS/VGSoff)**2
Set
VGSoff = V0 + PHI0
X = (PHI0 - VGS) / VGSoff
3-11: IDS = C * (1 - 3*X + 2*X**1.5)
3-12 is a reasonable approximation to 3-11, especially when VGSoff is smaller than 2...3 * PHI0.
I'll have to double check the formulas, do some curve plotting and re-activate my TeX skills to give a better presentation of this.
*** c) BJT modeling ***
Just learned that there is a differentation operator available in LTSpice curve plotting (D), so that's easy to do hfe/Ic plots.
Yes, most models look really ugly. The few LEVEL 2 models I have access to, look much better. I don't think you can do 2SB649/2SD669 in LEVEL 1.
But, whatever, simply let's use all our BJTs in the constant hfe region! I'll suppose it will sound better.
Regards,
Peter Jacobi |
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| fscarpa58 |
Thank you, Peter
Federico |
|
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| pjacobi |
Can't make a single post without a typo or number confusion...
| quote: | Originally posted by pjacobi
B1 0 D I=12m*2/pi*atan(pi/4*V(D,0)/(V(G,0)/3.9+1.0))*(V(G,0)/3.9+1.0)**2*(V(D,0)+200)/200
B2 0 D I=12m*tanh(0.5*V(D,0)/(V(G,0)/3.9+1.0))*(V(G,0)/3.9+1.0)**2*(V(D,0)+200)/200
B3 0 D I=12m*(V(D,0)+200)/200*if(V(D,0)<V(G,0)+3.9,V(D,0)/3.9*(2*(V(G,0)/3.9+1)-V(D,0)/3.9),(V(G,0)/3.9+1.0)**2)
.dc V1 0 24 10m V2 0 -3 -1
.end
B1 is SPICE level1, B3 is much like the pentode, B2 is another interpolation nearer to B1. |
B3 is SPICE level1,
B1 is much like the pentode,
B2 is another interpolation nearer to B3.
Also note that the 0-node is the S-node. |
|
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| Pedja |
| Nice, Peter. At the moment I can not do much more than to plot this. Seems like it will work. Thanks. |
|
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| Pedja |
Peter, others,
For probably easiest check, MicoCap (there is a free demo) from version 7 has that nice possibility to show a few plots for any used component and for BJTs this includes hFE vs. Ic plots.
For possibly better overview, attached (zipped) MicroCap’s .cir file (done for version 6, normally works in 7) plots these curves for both NPN and PNP device in one page.
Pedja |
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| fscarpa58 |
Hi, Pedja, All
Thinking at a given IC as to a working point, if the small signal current gain is required,
is it not better to plot the local derivatives of IC in respect with IB as a function of IC?
The plots are slightly different from your's
Bye
Federico |
|
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| Pedja |
| quote: | Originally posted by fscarpa58
Thinking at a given IC as to a working point, if the small signal current gain is required,
is it not better to plot the local derivatives of IC in respect with IB as a function of IC? |
Hi Federico,
Yes, that is interesting difference to think about. Probably those graphs that show local derivatives might be even more important for the real applications. But I think what we have in the datasheets and what could be the reference for model check is still only the plain Ic/Ib relation in the term of the established currents.
But nice addition to the file, I appreciate.
Pedja |
|
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| pjacobi |
Sorry, I assume I started the confusion.
I must correct myself. As Pedja said, the datasheets plot
hFE = Ic/Ib
The other one is called hfe. Fine distinction.
hfe = dIc/dIb
Regards,
Peter Jacobi |
|
|
| fscarpa58 |
Yes Pedja,you are right.
Thank you, Peter for the info
Federico |
|
|
| pjacobi |
| quote: | Originally posted by pjacobi
[...]
* JFET models
V1 D 0 0
V2 G 0 0
B1 0 D I=12m*2/pi*atan(pi/4*V(D,0)/(V(G,0)/3.9+1.0))*(V(G,0)/3.9+1.0)**2*(V(D,0)+200)/200
B2 0 D I=12m*tanh(0.5*V(D,0)/(V(G,0)/3.9+1.0))*(V(G,0)/3.9+1.0)**2*(V(D,0)+200)/200
B3 0 D I=12m*(V(D,0)+200)/200*if(V(D,0)<V(G,0)+3.9,V(D,0)/3.9*(2*(V(G,0)/3.9+1)-V(D,0)/3.9),(V(G,0)/3.9+1.0)**2)
.dc V1 0 24 10m V2 0 -3 -1
.end
[...] |
See also the graph in #23
http://www.diyaudio.com/forums/show...8580#post318580
By symmetry (if this is a symmetric JFET, but the essentials should also hold for unsymmetrical ones), we should have:
IDS (VGS, VDS) = -IDS (VGS - VDS, -VDS)
and not
IDS (VGS, VDS) = -IDS (VGS, -VDS)
This implies, that the second derivative of IDS in the VDS=>IDS isn't zero. So, the 'crude' Spice Level 1 model (in B3) is right, and the more elegant looking atan or tanh functions are wrong in this aspect. You can (bareley) see it by plotting for VDS=-0.3..0.3V
Some JFET datasheets have a good plot of the low VDS region, where you see this too. In the moment, I'm totally messed up with datasheets flying around, so I can give you concrete references only later.
BTW, can anybody volunteer a (free) tool for doing all the calcs and plotting?
With the help of the LTSpice mailing list (which mostly, and correctly, said 'read the fine online help'), I got my LTSpice experiments less messy. Nevertheless it looks like the wrong tool.
In the past I played a lot with Excel, but this wasn't very satifying.
I now tried (again) to get myself comfortable with SciLab (http://scilabsoft.inria.fr/).
Suggestions?
Peter |
|
|
| Pedja |
| quote: | Originally posted by pjacobi
So, the 'crude' Spice Level 1 model (in B3) is right, and the more elegant looking atan or tanh functions are wrong in this aspect. You can (bareley) see it by plotting for VDS=-0.3..0.3V
Some JFET datasheets have a good plot of the low VDS region, where you see this too. In the moment, I'm totally messed up with datasheets flying around, so I can give you concrete references only later. |
Peter, are you sure about this? If you know any datasheet that shows the curve for negative Vds it will be really a great reference now.
For those who won’t plot that, attached graph shows what Peter is talking about, so if anyone has any idea… As far as I can remember drain and source of JFETs are mostly interchangeable, so what is right and what is wrong here?
| quote: | | With the help of the LTSpice mailing list (which mostly, and correctly, said 'read the fine online help'), I got my LTSpice experiments less messy. Nevertheless it looks like the wrong tool. |
I am not sure, what is a problem with it?
Pedja |
|
|
| pjacobi |
| quote: | Originally posted by Pedja
Peter, are you sure about this? If you know any datasheet that shows the curve for negative Vds it will be really a great reference now. |
I don't know a datasheet which shows the negative Vds region, but for symmetric JFETs, e.g. the Fairchild 2N5484 series, you can always relabel S<->D, to get the values for negative Vds, using the formula above.
A datasheet, where with the help of a ruler, you can see that d²Id/dVds² stays rather constant when Vds => 0, is Vishay J/SST111 series.
But of course, unless you are really using a JFET with current flowing both ways, the numerical deviation is rather small. Just perfectionism (a.k.a. not-picking) at work.
Regards,
Peter Jacobi |
|
|
| fscarpa58 |
Hi Peter, All
| quote: | | IDS (VGS, VDS) = -IDS (VGS - VDS, -VDS) |
I agree with this relation but I use to put it in a more manageable ( for me) manner that is
IDS (VGS, VGD) = -IDS (VGD, VGS)
In other words, we have to solve the functional equation
F(x,y)=- F(y,x)
Referring to model B3, I note that if I turn over (top-down) the device I do not obtain similar curves. ( I plot current by using
a little (1u) res. on the top of the device to avoid sign proiblem)
federico |
|
|
| fscarpa58 |
Hi
I also note that B3 works
only if vgs>-3.9
Federico |
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| pjacobi |
And fig 2 in this nice paper shows the non-vanisching second derivative at the origin very clearly.
| quote: | Originally posted by fscarpa58
I agree with this relation but I use to put it in a more manageable ( for me) manner that is
IDS (VGS, VGD) = -IDS (VGD, VGS)
In other words, we have to solve the functional equation
F(x,y)=- F(y,x)
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I agree. Putting it this way, it's much easier to visualize, what the fuction should look like.
| quote: | Originally posted by fscarpa58
Referring to model B3, I note that if I turn over (top-down) the device I do not obtain similar curves. ( I plot current by using
a little (1u) res. on the top of the device to avoid sign proiblem)
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This looks fine already for the non-saturated region. Should be tweakable for a solution in the complete plane.
Other points to note:
The 2004-02-09 version of LTSpice did get the MESFET working. It's Statz' model (LEVEL 1 in AIMSpice, LEVEL 2 in PSPICE).
Not checked everything, but would also be nice to use for JFETs.
Main differences to JFET LEVEL 1
Uses 1 - (1 - x**3) instead of 1 - (1 - x**2) to interpolate between linear and saturated region.
Has an additional parameter for VGS=>VDS which allows to model the transfer characteric of devices which higher VGSoff, which approach linear near 0 VGS.
Regards,
Peter Jacobi |
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| fscarpa58 |
Thank you again for the info, Peter
F. |
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| pjacobi |
Hi Christer, All,
| quote: | Originally posted by Christer
Although I haven't really investigated that many manufacturers
models, my impression is that also BJT model are often mediocre
at best when compared to the datasheets.[...] |
Just popping this thread to the front page to note, that LTSpice just got the VBIC model implemented (as I have the impression, not all LTSpicers here are on the mailing list).
Mike's example to see the differences is this deck:
* Verilog-A vbic_3T_it_cf test circuit
vbe bx 0 0
vcb cx bx 0
vib bx b 0
vic cx c 0
q1 c b 0 vbic
.model vbic npn(level=9 RCX=10 RCI=10 RBX=1 RBI=10 RE=1 RBP=10 RS=10
IBEN=1.0e-13 RTH=100)
.dc vbe 0.5 1.0 0.001
.probe i(vib) i(vic)
.end
Do a gummel plot (log(i(vib)) and log(i(vic))) or simply i(vic)/i(vib)
For an intro to VBIC, see e.g. http://people.web.psi.ch/palfinger/dipl/dipl/node3.html
Regards,
Peter Jacobi |
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| lineup |
| quote: | Originally posted by pjacobi
This is for the SPICE modeling related discussions,
which started in the "Borbely Fet Follower" thread.
Let's avoid annoying the thread starter and others, who want to see practical issues, real circuits, discussed in that thread.
Regards,
Peter Jacobi |
| quote: | Originally posted by pjacobi
Hi Federico, All,
JFETs, the neglected stepchild of SPICE modeling?
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Compare these Philips models with the datasheets:
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This almost makes sense, doesn't it? Add impact ionization current to prevent designers setting Vds too high, and the models would be good enough for most simulations.
Compare with power BJTs.
Almost no models implement quasi-saturation.
Didn't stop us from using them.
Hexfets?
If used in class B amplifiers, devices spend signifant part of the cycle in weak inversion,
but you'll find models which doesn't model diffusion current at all!
Regards,
Peter Jacobi |
Hi, Peter Jacobi.
I hope you read this ... :)
I was searching for some better JFET BF245 A/B/C models.
Because I do not trust them I have ... I have some doubts :D
Now, I ended up in this execellent thread :cool:
Using Modified Tube Penthode model Formula, to better predict JFET
Great!
Give me some of those, please.
Spicy simulated regards, Lineup |
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