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TDA1541A/S1 Arrangements - Click HERE for Original Thread

rah

Hi all,

Recently we’ve become interested in building a DAC, and after spending a lot of time looking into design issues. We’ve decided to give non-oversampling DACs a go (As a cheap start into a never-ending process). ;)

Being engineering students, the theory has never been a problem for us, but the lack of funds/time a student has means that we rarely get to do subjective development. If you could help us out with your experience with the TDA1541A, and get us started, it would be great.

Two questions for the TDA1541A fans:

Question 1
-----------

We know that some of you have tried many arrangements of using TWO TDA1541A DACs, including:

1) Parallel TDA1541As
2) Balanced TDA1541As with R+ and L+ on one, and R- and L- on the other.
3) Balanced TDA1541As with R+ and R- on one, and L+ and L- on the other.

In your opinion, and listening tests, which gives the best sound subjectively?

Question 2
------------

Can any arrangement of TWO TDA1541As equal a single TDA1541A S1 in sound?
Or will the single TDA1541A S1 always outperform two TDA1541As using the best arrangements for each ?

Basically we have a choice, we can either obtain a single TDA1541A S1 or two TDA1541A. We want to take the one from which we can obtain best sound (Applying all tweaks, arrangements, etc...). But the TDA1541A S1 is 3 times the price of 2 x TDA1541A.

till

did you build a balanced TDA1541 DAC? Do you have any drawing of you circuit?

rah

Unfortunately not, I never got the time, and those DACs are still sitting where I put them :(

If you're interested, take a look at:

http://www.diyaudio.com/forums/show...15&pagenumber=1

I've posted some info here, but you'll have to work out a few things.

I'll post what I did, when I get around to doing it, hopefully soon...
(But plz don't wait) :)

till

I´ll wait. I have some TDA1541A (and some AD1865 etc) laying around for some time, because of the plan to build a balanced DAC ... but same as you describe.

The thread above i know, but i fell not skilled enough to work thing out. I´ll wait until someone posts a simple and working circuit for feeding the DAC right way for balanced operation.

guido

quote:

Originally posted by till
I´ll wait. I have some TDA1541A (and some AD1865 etc) laying around for some time, because of the plan to build a balanced DAC ... but same as you describe.

The thread above i know, but i fell not skilled enough to work thing out. I´ll wait until someone posts a simple and working circuit for feeding the DAC right way for balanced operation.

Simple: one dac for L+ and R+ connected in the normal way.
other dac for L- and R- by inverting the dataline.

one dac for L+/L- and one for R+/R- here:

http://www.diyaudio.com/forums/show...t=&pagenumber=1

I'm still looking at the output options, so no comment on 'sound' yet (i know it is taking loads of time with this thing...).

Regards,

till

i did see that thread also, i can´t make GALs, and i think the circuit has not really few parts. Lots of ICs. I had the hope for something more simple to build. What about DACs with parallel input? Or one programmable chip doing all the work for digital inverting.

guido

quote:

Originally posted by till
i did see that thread also, i can´t make GALs, and i think the circuit has not really few parts. Lots of ICs. I had the hope for something more simple to build. What about DACs with parallel input? Or one programmable chip doing all the work for digital inverting.

Indeed lots of parts. But you can buy the pcb, so if you really want to get the TDA's working like this it is just a matter of buying pcb and the components. And yes, you need to find somebody to program the GAL (there is one obvious person to ask, i guess ....:cannotbe: )

You could program the whole lot into one modern CPLD, but then you need to find somebody to do this with a programmer.

For DACs with parallel input, you need logic to convert I2S into parallel datastream = more parts. Early BB are parallel: PCM53, 54 and 55, but they are mono: you need four of them :cannotbe:

If you want differential but with not so many parts: use the DACs in stereo and just invert the dataline to one of them.

The GAL has advantages: looking at the cambridge cd3 way of getting to 16Fs, i had a look if i could get 2Fs. It is possible with some reprogramming of the GAL (output DAC1: left sample & previous left sample, DAC2 right sample and previous right sample).

I sacrifised mute to switch into this mode (muting done with 7210). If it gets me anywhere, i dont know. But just to show that progr. logic has it's advantages.

Just to show off :D :D :D :D :

DAC
GUIDO BALTUS

CHIP GAL GAL20V8

LATCH GO WSDELAY SHIFT64 SHIFT32 DATA WS DIFFERENTIAL ONEFS CLKDIV2 CLKDIV4 GND
/OE NU1 DATAL WSL I2SCLK WSR DATAR FIFOREAD CLOCK CLOCK_INV NU2 VCC

EQUATIONS

FIFOREAD = /GO + GO * /CLKDIV2 * CLKDIV4 +
GO * CLKDIV2 * /CLKDIV4

CLOCK = CLKDIV4
CLOCK_INV = /CLKDIV4

I2SCLK = /CLKDIV4

WSL := ONEFS * /WS + /ONEFS * WS

WSR := ONEFS * /WS + /ONEFS * WS

DATAR := ONEFS * WS * DATA +
ONEFS * /WS * SHIFT32 * DIFFERENTIAL +
ONEFS * /WS * SHIFT32 * /DIFFERENTIAL * WSDELAY +
ONEFS * /WS * /SHIFT32 * /DIFFERENTIAL * /WSDELAY +
/ONEFS * /WS * SHIFT32 +
/ONEFS * WS * DATA

DATAL := ONEFS * WS * SHIFT32 +
ONEFS * /WS * SHIFT64 * DIFFERENTIAL +
ONEFS * /WS * SHIFT64 * /DIFFERENTIAL * WSDELAY +
ONEFS * /WS * /SHIFT64 * /DIFFERENTIAL * /WSDELAY +
/ONEFS * /WS * SHIFT64 +
/ONEFS * WS * SHIFT32

till

quote:

you can buy the pcb,

in case some people descide to do, i´m in. Alone i fear that i´m not skilled enough to solve the problems until it works.

quote:

If you want differential but with not so many parts: use the DACs in stereo and just invert the dataline to one of them.

simply connect one normal, and one with an inverter in sdata line? thats all?

this http://www.diyaudio.com/forums/show...0953#post300953 looks more difficult

whats the drawback of this solution? does it also work with other DACs?

Another point: could you please give me a link to a TDA1541 datasheet? i can´t find it.

rfbrw

quote:

Originally posted by till
this http://www.diyaudio.com/forums/show...0953#post300953 looks more difficult
whats the drawback of this solution?

None that I can see but I do not know what you consider a drawback.

quote:

does it also work with other DACs?

No. It is strictly for the TDA1541/A and and it must be balanced.

quote:

Another point: could you please give me a link to a TDA1541 datasheet? i can´t find it.

Go to Google and click on advanced search. Set the search to return pdf files only and search for the TDA1541 or TDA1541A.

ray.

Andypairo

quote:

I can easily program GALs at work, just in case... (not sure but probably have the right GALs/PALs too)

Guido, is this the JEDEC file or do you provide one on request?

Cheers

Andrea

guido

quote:

Originally posted by till

in case some people descide to do, i´m in. Alone i fear that i´m not skilled enough to solve the problems until it works.

simply connect one normal, and one with an inverter in sdata line? thats all?

this http://www.diyaudio.com/forums/show...0953#post300953 looks more difficult

whats the drawback of this solution? does it also work with other DACs?

Another point: could you please give me a link to a TDA1541 datasheet? i can´t find it.

I did not have big problems with building the thing. One resistor missing at the reset ic, that was it. It's in the earlier post. But it is a lot more hassle than the one inverter. And it is NOT a complete DAC, no output circuits, no powersupply.

So my pcb does: Dac1: L+,L+ or L+,L-
Dac2: R+,R+ or R+,R-
depending on a jumper setting.

The inverter does Dac1: R+,L+
Dac2: R-,L- the one with the inverter on data

But the pcb is more than i2s split: also included is a fifo so the master clock can be in the dac (works with older philips/marantz players).

It should be possible to not have a fifo and take the incoming clock from i2s. That would mean no fifo, no buffer and no reset ic, i think. And some GAL reprogramming. Could look at this on request.

The other link shows a circuit for conversion from I2S to balanced 'parallel data in' as far as i could see with a quick view.
Indeed tda1541 only (also 1540 has (only) this mode, but that's 14 bit). Also possible i guess.

Regards,

guido

quote:

Originally posted by Andypairo

I can easily program GALs at work, just in case... (not sure but probably have the right GALs/PALs too)

Guido, is this the JEDEC file or do you provide one on request?

Cheers

Andrea

The original equasions are here: http://www.diyaudio.com/forums/show...t=&pagenumber=2

They can be processed with opal (junior). I can post the file which can be used to program the GAL, no problem.

The equasions in this post (2fs mode included) are not tested. I just fiddled a bit so see if i could do this.

Reread the whole old threat if you are interested. If you still are, you can directly order the pcb at olimex. As far as i know there is one more pcb sold to a person in thailand. The poor guy is trying to get the components...

Greetings,

guido

:D :D :D :D :D It would be great if more people would try balanced mode. Either invertor or the whole lot, does not matter.

I could use some good idea's for output ciruits:cannotbe: :cannotbe: Have been lazy lately:angel:
Saw the cd7 output circuits, too many hdam's xeye: :xeye:

:mad: :( :confused: :cannotbe: :apathic: :rolleyes: :) ;) :cool: :D :clown: :

till

Andypairo, are you going to build a balanced DAC?

anyone else interested?

guido

quote:

Attached it with the equasions file.

GuidoB

rfbrw

quote:

Originally posted by till
Andypairo, are you going to build a balanced DAC?

anyone else interested?

Why not design your own?

Andypairo

quote:

Originally posted by till
Andypairo, are you going to build a balanced DAC?

anyone else interested?

At the moment I'm populating a board (of the 2 I have) from Pedja with a single TDA, was temted to do a balanced DAC but still don't know.

Cheers

Andrea

mikelm

Hi

A balanced DAC is exactly what I would like to build.

I'm just ordering some parts !

after that the real fun will begin because I have absolutely zero knowledge of digital.

My aim would be to have R + L completely separate.

Also I will leave the o/p balanced as the rest of my system is already balanced.

I wonder if there is a good book that deals with the practicalities of digital that I could have a look at.

any suggestions ?

till

quote:

Why not design your own?

Because i don´t know much about DACs, the moste complicated circuit i dealt with are those until now: http://home.tu-clausthal.de/~tpa/

But ok, the most simple variant would be like this?

(should we ask a moderator to split threads as this isn´t "TDA1541A/S1 Arrangements" ?)

rfbrw

quote:

Originally posted by till

But ok, the most simple variant would be like this?

Near enough except the inverter should be on the data line.

quote:
[B]
(should we ask a moderator to split threads as this isn´t "TDA1541A/S1 Arrangements" ?)

Not really it's all much the same thing be the dac a '41 or a '43 unless you opt for the simultaneous input mode.

Knowing about dacs wouldn't help that much anyway. You need some understanding of digital logic. Once you can visualise the data flow in your head, everything else is easy.

ray.

till

Sorry, the inverter on the wrong line was a really stupid mistake, i should have looked closer...

This? What should be on OB/TWC for I2S input?

And one really important question: how could i obtain some of those connectors for I2S from my CDPRO2 ???

till

Why did this one use Inverter on Data and Fsynk?

till

The difference would be, in his Retro- Dac he uses one AD1865 for L +/- and one for R +/-, whereas this would use one chip for L/R + and one for L/R -. What are advantages/disadvantages?

Bricolo

quote:

Originally posted by till
The difference would be, in his Retro- Dac he uses one AD1865 for L +/- and one for R +/-, whereas this would use one chip for L/R + and one for L/R -. What are advantages/disadvantages?

The picture you posted hasn't a DAC for L+- and one for R+-

Each dac has L AND R, one has the + the second has the -

till

quote:

whereas this would use one chip for L/R + and one for L/R -

Thats what i said.

the thread will not be more easy to read by quoting pictures

Bricolo

ok, I've read to fast.

but inverting the dataline (-> havine one dac for r+ l+ and one for r- l-) is a far more easy solution. At least for I2S signals.

till

yes, but whats the advantage of the solutions with two inverterts or glue logic?

Calimero

I don't precisely know the audible effect of time differences between the non-inverted and inverted signals, but they can be simply preventd by using xor-logic for both signals.
Connect L and R to each input of a separate XOR-gate (74ls86)and connect the other input to 0 (you get L+ and R+). Mirror this solution but connect inputs to 1 and you get L- and R-.

I wonder if there is a better solution to this (in terms of jitter) and not considering asynchronous reclocking. Should the CLK also be considere.

till

So the point is phase difference between the Data and INV(Data) is not exactly 180° with inverter in one line? are there high speed inverterts?

Or what about a unity gain phase splitter (one transistor) or a differential pair instead of inverter?

rfbrw

You can probably split the datastream with anything. In the general scheme of things I doubt that it adds up to much, though I am sure there are those who are certain to claim they can discern a difference between a circuit with the inverter and one with the xor while at the same time overlooking the lack of LSB inversion.
The idea behind using one dac for L and L- is that any noise generated in the dac common to both channels is rejected when the outputs are summed.

ray

till

OK, this reason i do understand.

Would this work?

Any idea were i could obtain the connector for I2S out on my CD PRO2?

till

or this

Still don´t know how to set mode at OB/TWC and how to obtain the damned I2S connector of CD PRO2

guido

OD should go to pen 28, as for normal i2s.

http://www.diyaudio.com/forums/show...t=&pagenumber=2

As Ray pointed out: inverting the dataline is not a 100% inversion of the signal. The correct procedure would be : invert bit 2 to 16, but do not invert bit 1 (LSB). So by inverting the dataline, you're one bit off.:xeye:

You have connected the i2s signals incorrect to the tda :att'n:

In one of your previous posts you connected 180 i/v resistor to the tda1541. That is way too high, i'll get distortion. Check some posts/designs.

Put i see new idea's for i/v ciruits :D :D

Greetings,

guido

quote:

Originally posted by guido
OD should go to pen 28, as for normal i2s.

http://www.diyaudio.com/forums/show...t=&pagenumber=2

As Ray pointed out: inverting the dataline is not a 100% inversion of the signal. The correct procedure would be : invert bit 2 to 16, but do not invert bit 1 (LSB). So by inverting the dataline, you're one bit off.:xeye:

You have connected the i2s signals incorrect to the tda :att'n:

In one of your previous posts you connected 180 i/v resistor to the tda1541. That is way too high, i'll get distortion. Check some posts/designs.

Put i see new idea's for i/v ciruits :D :D

Greetings,

Oeps, OB i mean

till

quote:

Put i see new idea's for i/v ciruits

sorry, its not new, its Pass... as seen on www.passlabs.com

thanks for corrections.

guido

Thought so, but as far as i remember the pass design used the PCM63 with the current source connected.

Therefore signal in with zero's (mute, no signal) would output
0 mA to the output circuits.

The TDA is -2mA at zero's in and has no current cource to corrrect.
Look at pedja's AD844 design were he uses a current source to correct this.

Guido

rfbrw

Till,
The second circuit should work giving +(L/R) and -(L/R) and datasheet covers OB/TWC. BTW, OB is for simultaneous mode only.
The first circuit will not work as the data is I2S. Multibit AD dacs are LSB justified. I2S is MSB justified to 1 serial clock cycle after a L/R clock transition. If the format was correct, there would be an interchannel delay of 11microseconds.

Bricolo

IHO, the easiest way to get +-R and +-L would be to convert the I2S to another format, that uses different lines for L and R

Then, simply feed the DAC with digital L (or R) at one input, and inverted digital L (or R) at the other input

till

second circuit is posting #32 and first circuit posting #31, right?

so at the #32 circuit i have to look at this -2mA / current source problem.

How do i connect an AD DAC to I2S? or is it only possible with SPDIF and reciver chip?

And an answer for the connector problem?

quote:

You have connected the i2s signals incorrect to the tda

What is wrong and how is it right? what # ?

quote:

the easiest way to get +-R and +-L would be to convert the I2S to another format, that uses different lines for L and R

good idea - with any chip, or with a microcontroler / DSP? how fast do i need to feed the DAC / what is the I2S clock? 2,82MHz like in DDDAC?

till

- I have seens loads of circuit connecting some DAC with recivers (8412 or 8414) to SPDIF, but not to I2S.

Is this better or still wrong? #40

- I don´t understand / find this current source issue in D1 circuit, some hint?

- What abaut TDA1543, same problem when I/V with D1 stage?

Bricolo

quote:

Originally posted by till

good idea - with any chip, or with a microcontroler / DSP? how fast do i need to feed the DAC / what is the I2S clock? 2,82MHz like in DDDAC?

There must be some chips made for I2S->4 lines conversion. No need for an µc for this.
Yes, I THINK that the I2S clock is 2.82MHz in a non os configuration

Bernhard

quote:

Originally posted by guido

i had a look if i could get 2Fs.

Guido,

do you want to do that to cancel RF garbage on the output ?

I had that idea too, but there was not much response to my thread...

Bernhard

quote:

Originally posted by guido
[B]I could use some good idea's for output ciruits:cannotbe:

What you think about this one ?

Bernhard

quote:

Originally posted by Calimero
I don't precisely know the audible effect of time differences between the non-inverted and inverted signals, but they can be simply preventd by using xor-logic for both signals.

You could use a noninverting buffer in the other line.

Bernhard

quote:

Originally posted by guido
The TDA is -2mA at zero's in and has no current cource to corrrect.

Ups, what is the current range for positive and negative max. output ?

Bricolo

Can someone explain me the problem with I2S and dataline inversion?

And the difference that a XOR would do, compared to an inverter

till

rfbrw,

you wrote

quote:

The first circuit will not work as the data is I2S. Multibit AD dacs are LSB justified. I2S is MSB justified to 1 serial clock cycle after a L/R clock transition

i admit i don´t really understand:

From AD1865 datasheet:
Data is transmitted to the AD1865 in a bit stream composed of 18-bit words with a serial, twos complement, MSB first format.

From TDA1541 datasheet:
The TDA1541 accepts input sample formats in time multiplexed mode or simultaneous mode with any bit length. The most significant bit (MSB) must always be first.

looks both are MSB first. Is the twos complement the point?

till

Bricolo, as i understand the XOR is only because some fear the inverter in only one of the datalines needs some time to invert and such one the inverted dataline is a bit laid back relative to the noninverted. This should be easy corrected by using a phase splitter or an additional buffer in the noninverting dataline.

The main proble seems to be we loose one bit, as guido posted: http://www.diyaudio.com/forums/show...0783#post340783

The inersion of data isn´t really the inverted dataword.

The inverted dataline tells only 15 bit words to the DAC what means our - signal is one bit less accurate tha the + signal.

I would ignore the problem with the time allignement of inverted and noninverted word as it will be about nothing. We should better think about the lost bit.

Bricolo

quote:

Originally posted by till

looks both are MSB first. Is the twos complement the point?

I think, yes.
2's complement is a way of coding digital information, that has a special feature: when you invert the MSB, you change the sign of the coded number

that's all I know. But I'm not sure if it's usefull here, since we invert all bits, and not only the MSB

till

I don´t know is only for the AD1865 the dataword twos complemet or for I2S also?

because http://www.diyaudio.com/forums/show...0803#post340803

quote:

The first circuit will not work as the data is I2S. Multibit AD dacs are LSB justified. I2S is MSB justified to 1 serial clock cycle after a L/R clock transition. If the format was correct, there would be an interchannel delay of 11microseconds.

i inverstigate on timing:

TDA1541

shows the timing: word clock changes 1 serial clock before last bit is clocked into DAC.

AD1865

shows the word clock changes direct after last bit of the word is clocked into DAC. DAC want a falling edge, such WCLK would have to be inverted for Left channel LL.

but now:

I2S out of Philips CD PRO2

surprise surprise, this doesn´t look like the I2S the TDA1541 does like. For me it looks more like the ADs timing. Whats going on here?

And again: is format twos complement only for AD or also in I2S?

So we would need some twos complement inverter for correct inversion.

till

In case I2S has also twos complemet would interfacing the AD look like this?

twos complement words looks like this, it´s obvios simple inversion gives not the inverted value but is always wrong with 1.

rfbrw

The datasheets cover all this but here goes.
There seem to be a number of distinct issues being rolled into one.
Offset binary and 2's complement are issues in their own right. They cover the number formats and what the bits actually mean.
MSB first is about the orientation of the data.
Justification is about the position of the data word as a whole. Using the output of the CS8412 as an example each L/R frame has 64 bits i.e. 32 bits per channel. Right justified 16bit data would occupy bits 1 to 16 with the MSB for MSB first data in the bit 1 position. Left justified 16bit data would occupy bits 17 to 32.
The I2S bus is right justified with a quirk. 16bit data would occupy bits 2 to 17. Things are can be somewhat different with mono and simultaneous input dacs.

ray.

till

Thanks.

some still confusing things:

The I2S from the CD PRO 2 manual doens´t show the "quirk" , it looks like simply bit 1 to 16 are dataword. The TDA1541 datasheet shows the quirk, 2 to 17 are one word. Both I2S , both Philips, connect or not?

The AD can´t be connected because it wants left justified (last 18 Bit clocked into Dac are writen into shift register...) but I2S is right?

So the only way for AD DAC is using a CS8412 or CS8414 and SPDIF?

rfbrw

quote:

Originally posted by till
The I2S from the CD PRO 2 manual doens´t show the "quirk"

See Fig3 in post number #50

quote:

The AD can´t be connected because it wants left justified (last 18 Bit clocked into Dac are writen into shift register...) but I2S is right?

The CD Pro2 supports a number of formats. It can be configured using the DSA command set. See the manual. Yes, I2S is right justified.

quote:

So the only way for AD DAC is using a CS8412 or CS8414 and SPDIF?

No. Added logic between the CD Pro2 and the AD1865 is another option.

ray.

till

- I must be stupid, but i can´t see why figure 3 has the 1 bit offset. Maybe because quality of the diagramm is that bad i can´t read the numbers or words in the bits. To me it looks like one 16 bit word into one WCLK frame.

quote:

The CD Pro2 supports a number of formats. It can be configured using the DSA command set. See the manual. Yes, I2S is right justified.

I have "USER MANUAL PREMIUM 10501" and "VAU1254bis.pdf" the Datasheet. I find the DSA commands, and i find there is a command set DAC mode 70h but all infoormation about the possible DAC modes given is parameter = XX; XX= don´t care. It doesn´t help me the VAU1254 is able to send in other formats as long as i have no table with parameters for 70h and diagramm or description of possible modes. In the docs provided with the unit they are not.

quote:

No. Added logic between the CD Pro2 and the AD1865 is another option.

I fear its behind my skills. Not at least because it seems very difficult to find all information necessary. If i would have the equipment to programm a fast enough DSP or so, it would be possible to solve inverting the datawords and serve them in right format and order in software.

rfbrw

quote:

Originally posted by till
- I must be stupid, but i can´t see why figure 3 has the 1 bit offset. Maybe because quality of the diagramm is that bad i can´t read the numbers or words in the bits. To me it looks like one 16 bit word into one WCLK frame.

Can't see how you can miss it. Unless you are looking for the wrong thing.
The MSB of each 16bit word, i.e bit 1, is positioned one serial clock cycle after the transition of WDCLK.

quote:

70h is the command value that tells the device what the following value is for. You need to follow the value 70h with the value for the mode you require.
The document "DSA Interface Bus Protocol & DSA Command Set Premium 10501" lists the values for all possible output formats on page 31.

quote:

Digital Audio is slow. Glacially slow. Any DSP, never mind a fast one, would be wasted. Inverting the data, adding the 1 and then reordering the data would barely make a dent in the smallest sizes of the latest FPGAs and CPLDs. A few 74 series TTL chips or a XC9536 CPLD would make short work of connecting the CDPro2 to the AD1865.

ray.

till

quote:

The document "DSA Interface Bus Protocol & DSA Command Set Premium 10501" lists the values for all possible output formats on page 31.

Thanks, your help is invalueable. I found it.

quote:

Digital Audio is slow. Glacially slow. Any DSP, never mind a fast one, would be wasted.

But to fast for PIC, even at 40MHz i fear. I hope for DSPics. A Software for processing the Bitstream has the advantage its very easy to change format for different DACs. It would be possible to build different DACs in one unit and simply software switch them for example. And in case you do not develop for mass production but only one unit, its much easyer to make your mistakes in software as its easy to correct them.

guido

Mucho posts here, hard to keep up.

Till,

Your previous tda schematic had le/ws unconnected. Just look at any of the schematic on the net for tda1541 connections. Never saw anything else but i2s. Forget a PIC for this, you need logic. DSP is indeed overkill.

Dont know if it would be a problem, but the DAC in the D1 circuit is 0mA out for 'dig silence' data in. That is because the internal current source of the PCM63 is used (the output pin is connected to another pin of the DAC, check it out).

A tda1541 is -2mA at rest, so the there is current running when
there is no music. Again, i'm not an analogue expert, so don't know if it matters. But i guess pass did not use the internal PCM63 current source for nothing! (reports are that it is better not to use it, but then your output circuit must be capable of handling this).

Bricolo,

If you go from i2s to "4 line format" you should check the way the data is coded (for 1541). From memory, it is different than the i2s coding. If so, inversion by just inverting the dataline might not be possible (after you created the separate datalines)! Check the datasheet and the used coding formats and start drawing.

I2S clock is 2.82 MHz because wordlengths are 32 bit (16 bit used, 16 unused) as for SAA7210 or the 8412. samplefreq = 44kHz times 64 = 2,816 MHz. E.g. 7220 output is 16 bit wordlenghts. So 44kHz * 4 (oversampling) * 32 = 5.632 MHz.

Bernard,

2Fs was just an idea, did not really look into it. TDA1541 is 0 to -4mA out.

I'll have a look into not inverting the LSB. Did not bother before (nobody did in any design i saw on the net (including D1). I wonder if it matters (is audible).

Greetings,

till

Hi guido,

I changed the connection in post #40, i hope this way its correct.

Indeed i can forget a normal PIC as it is to slow and thus not easy to program in an way the bitstream comes out isochron. A DSP is much more difficult to get running, so its not the solution also. Logic may be easy for someone from the days IBM build ATs with about 200 TTL 74xxx ICs on mainboard. But for one who does not know all the logic chips by name and funktion and is not used to hardware logic its a pain and nothing else. Software is much more easy to handle. I hope there will be a MC with DSP features or a ten times faster MC soon, so it would be easy to do all it in software and one IC.

For the inverting: If we invert the twos complement incorrect (inverter) we loose information for - side of balanced DAC. So waveform on + and - is not symmetric. In this situation i estimate 2 parallel DACs, one of them running the out signal in an inverter / the other in a identical buffer ( 2 diff. pairs) would be better balanced signal than one were the - side is generated digitally but with assymterical waveform by principle.

I hope you or someone else skilled in 74xyz stuff will find time for a elegant solution for inverting the word and add 1, for a correct inverted signal. I´ll try some tests with simple interconnects of DACs to the transport. And hope i´ll find something to make the format transfomation and inversion with some kind of programmable one chip solution on the long run.

The -2 mA issue: does this mean range is from -2 to +2 mA ?

Bricolo

guido said the range is 0 to -4mA on a 1541 (the signal is -2mA at iddle)

inverting and adding 1 isn't easy to do. I don't think it's possible with basic logic

till

In the PCM63 datasheet they say that DAC is -2 to +2 mA. Whats the funktion of bipolar offset current i don´t understand. But i can´t see what would be a very big problem in this current offset. Why shouldn´t the stage work with little different current values?

guido

Till,

Inverting after the DAC is not good. The idea to do it in the DAC is to cancel out any garbage on the powersupply which would be on both outputs. Therefore +L/-L +R/-R is better than +L/+R -L/-R since you have one powerline for +L/-L instead of two (in theory).

The pcm63 has a pin BPO (5) which is a bipolar offset current output pin (+2mA). When connected to 6 (out) you get an output of +/- 2mA. Without it, output on pin 6 will be 0 to -4mA like TDA1541. Kirchhoff is watching:

output full positive:
out + offset = 0 + 2 = 2

output at data 'zero'
out + offset = -2 + 2 = 0

output full negative:
out + offset = -4 + 2 = -2

hope this makes it clear

So when offset is connected like D1 (check the schematics) you get +2/-2 on the i/v circuits. The TDA1541 does not have the +2mA offset pin, so you put 0/-4 on i/v ciruit. Q is can it handle it?
Answer: probably not, otherwise the D1 would not have the offset pin connected (?).

Not inverting the MSB is a bit difficult, since it is in the middle of the dataword. Remember this is 32 bits. One easy solution i see for my DAC: find a spdif receiver which outputs i2s with 16 bit words (dont know if there is one, i'll have a look).

This would but the LSB just before the MSB of the new dataword.
I have WS and WSdelayed. XORing them would give me a signal which is low, except for the time when the LSB is on the dataline!

I can then easily reprogram the GAL to not invert the dataline if (WS XOR WSdelayed) is high. However, the shiftregister i use has to be modified from 32+32 to 16+16. That's a hardware change...

Basic logic would also be possible:
- make a ws delayed like i did
- xor it with ws
- clock the pulse through some shift registers to 'move' it to the
lsb position.
- use that to not invert the dataline at that moment.

Would it be audible :xeye: :xeye: :xeye:

mvg,

till

The +-2 or 0 to -4 mA problem should be easy to solve in the one or other way.

For inverting the dataword i don´t see why inverting all but the MSB is the right way to the inverted word. If these words are twos complement formated inverting the sign would be inverting the word and then increment by one.

2nd picture in #51:

-2. = B'11110'

INV(11110) = 00001
INC(00001) = 00010

B'00010' = +2.

This made with logic ICs i can´t do. I would need software. Or some kind of logic chip i can program like software.

The device desired looks for me like : serial I2S clock into device, now we have 16Bit words. Invert a copy, inc the copy, clock serial out the noninverted and the inverted with a stable isochrone SCLK at the same phase to two DACs in the format they DAC likes.

Now for the less serios intended part of this posting:

The device could - in case it would be doable what it isn´t - also do the following: Depending on DAC R/L channel muliplexed or to separate lines, and MSB or LSB first, with "quirk" or without, and left or right justified. Idealy this device is also able to real time interpolate a spline thru the words read, and generate words for indermediate timeframes beween the 44100Hz words, and clock them out with n*44100Hz * word. Also it could enhance intermediate words in bitlenght as they are interpolated .... and so on. Good job for a DSP - and 2 Years of development work.

Bricolo

the easiest would be to use a format that isn't 2s complement. One that gives -x from x if you invert all bits from x

But I don't know if this exists.

till

There is not much choice i fear - what we have avaiable is Spdif, and sometimes I2S - out of the transports or CDPs. I would prefer to use the I2S if possible. To tell the CD PRO2 unit - or only those few DSA units out there - to use another format on the I2S than what it sends by default would need the additional task to build a own controller. This task is intersting, but i fear also very time consumtive.

formats:
I 2 S - FS mode (default)
2 I 2 S - 2 FS mode
3 I 2 S - 4 FS mode
4 Sony 16 bit FS
5 Sony 16 bit 2 FS
6 Sony 16 bit 4 FS
7 Sony 18 bit FS
8 Sony 18 bit 2 FS
9 Sony 18 bit 4 FS
81 I 2 S - CD-ROM mode
82 EIAJ CD-ROM mode

I don´t know the format of all these modes, some work to find the specs

Bricolo

Let's see if we can easilly invert the SOny format.
If I remember correctly, it's an unsigned format. So for a 16bit data, 32768 means zero

till

2nd construction site...

we have to design a controller that at least have to set the DAC mode via DSA and tell the transport to play...

Bricolo

What do you want to do?
To be abble to test many configurations, or simply to set the DAC to a given mode?

If it's the 2nd solution, and that the DAC settings are stored (if they stay the same after a shutdown) you only need a computer

till

I don´t think the setting will stay after power down. Do you have a DSA cable, could you try it?

Bernhard

I have built a few large digital circuits, maybe I can do it.

What exactly do we need ?

till

i hope i will be able to describe it in english

A black box, reciveing SPDIF or better I2S.

recieving the words 16Bit for left and right channel MSB first (difficult because of the one bit time offset in I2S, here called the "quirk") and build the inverse. As the word are twos complement this must be done by inverting and increment 1. Than serial transfer this words both syncronous, in inverted and noninverted, to two DACs. One DAC recives inverted and noninverted words for right, the other one for left channel.

In case of TDA1541 DAC this transfer has to be into the DAC in I2S with the "quirk" MSB first, right justified. This means the noninverted and inverted words must be feed time multiplexed like the DAC normally expects right and left channel.

In case we use AD1865, without quirk, with at least 2fs speed, left justified (and 2 zeros added each word for 18Bit). Here the noninverted and inverted are feed into separate lines syncronous, no time multiplexed, as the AD has separate left and right data in. This i think would be an intersteing second step, TDA1541 first because demand should be higher in this board. (?)

please rfbrw and guido, check and correct this.

Bernhard

For me it must be SPDIF because of the Ultracurve which is input & output SPDIF.

So just invert the 16 bit words + add 1 after cs8414 chip ?

How are the words marked in the other signals ?
Start / stop bits ???

mikelm

I think we are trying to:

get a balanced o/p from TDA1541A or TDA1543N

L- / L+ & R- / R+ to minimise noise

using I2S

without loosing any bits

using logic hardwear with minimum noise & jitter

I think / hope in zero OS mode

I am a digital virgin so I hope my summary is sensible and correct

I hope it won't be too boring for the others if you explain even basic terms / abreviations.

thanks

mike

OK Till you beat me to it !

Bernhard

Please be human and care for the people who have to go with the crystal receiver chip.

mikelm

quote:

Originally posted by Bernhard
Please be human and care for the people who have to go with the crystal receiver chip.

OK, as it happens I have one on order, ( I thought it might come in handy...;) )

mike

till

What about using a CS8412 or 14 for your SPDIF and convert to I2S, and at this point the black box device feeding the DACs, this would make it usable also for I2S input from a transport directly by leaving away the reciver. This would fit all.

For the timing http://www.diyaudio.com/forums/show...1149#post341149

first picture.

description here http://www.diyaudio.com/forums/show...1183#post341183

we don´t add one bit, we need to invert the words by first step: invert it, second step, increment it by 1. Its still a 16 Bit word now. The 17th bit is truncated --> example inverse of 0. = B'0000000000000000' would be B'1111111111111111' now we inc (B'1111111111111111') and because we truncate result is again 0. = B'0000000000000000') works for all other values also, check http://www.diyaudio.com/forums/show...1156#post341156 picture 2

The words are marked by the Wordclock, but to make things not easy god made the word not start at the WCLKs transient but one bit later. Word is bit 2 - 17 of 32 bits, the others are garbage. Bit 2 in one frame of the WCLK is MSB.

I hope this is correct.

Bernhard

quote:

Originally posted by till
What about using a CS8412 or 14 for your SPDIF and convert to I2S, and at this point the black box device feeding the DACs, this would make it usable also for I2S input from a transport directly by leaving away the reciver. This would fit all.

Is that easy to convert to I2S after CS8414 ?

Does your description apply for the standard 3 line signal: SCK SDATA FSYNC ?

Elso Kwak

Hi,
This has been discussed before:
http://db.audioasylum.com/cgi/m.mpl...+guido&session=
I stand corrected that the TDA1543A is NOT offset binary but Sony Japanese format.
I fear that the logic scheme needed to correct the LSB for the inverted signal will damage the sound more than leaving the LSB faulty as it is. Also the two DAC's constituting both polarities of the audio signal should be exactly equal. In practice this is not the case.

till

In case we have a circuit with CS8412 connected to TDA1541 the connection with SCK SDATA FSYNC should be I2S, or? So the CS should be able to give I2S at output

till

elso,

from TDA1543.pdf:

quote:

The TDA1543 accepts input serial data formats in two's complement with any bit length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The format of data input is shown in Fig.5 and Fig.6.

timing looks exactly like in 1541 datasheet

i don´t really understand your point.

Bernhard

I am a little confused about MSB and LSB.

The LSB is the one that makes the smallest change and MSB makes the biggest change ?

Here was written MSB does not have to be inverted.

What I got:

444 = 0110111100
-444= 1001000100

The three least significant bits are equal.

There are no rules, sometimes 1, sometimes 2, sometimes three LSBs are equal.

What am I missing here ?

till

444. in 16 bit word, Zweierkomplementdarstellung

444. = B'0000000110111100'

invert -> 1111111001000011

incr -> 1111111001000100 = -444.

siehe #76 und #52 or google zweierkomplementdarstellung

Bricolo

Zweierkomplementdarstellung= 2's complement ;)

Bernhard

quote:

Originally posted by till
444. in 16 bit word, Zweierkomplementdarstellung

444. = B'0000000110111100'

invert -> 1111111001000011

incr -> 1111111001000100 = -444.

siehe #76 und #52 or google zweierkomplementdarstellung

I don't question this.

But here was written, that instead of inverting the whole word plus adding 1, it is possible to just invert the whole word except for the MSB.

???

till

Ah! we have to discriminate between LSB and MSB of our 16 Bit dataword, and of the word - row of bits coming out of the CS8412 or I2S in one wordclock cycle. When is written the MSB (the first one in the hole bunch of bits in one frame) does not have to be inverted, its the Bit that is not part of the dataword, as the 2nd bit in the frame is the MSB of our dataword. After we separated the dataword from the other bits in one frame its the invert and increment.

till

except the LSB?

from #34:

quote:

As Ray pointed out: inverting the dataline is not a 100% inversion of the signal. The correct procedure would be : invert bit 2 to 16, but do not invert bit 1 (LSB). So by inverting the dataline, you're one bit off.

I don´t really understand why inverting all but the LSB would be correct twos complement inverting.

maybe twos complement is not = twos complement?

but datasheet says:With OB/TWC connected to VDD the mode is the same but data format must be in two’s complement. And guido in #33 OB/TWC to Vdd is I2S mode.

This tells us words are in twos complement and twos complement is inverted as above.

Bernhard

quote:

Originally posted by till
Ah!

Ah!

So SCK and FSYNC are active low signals and the word starts after one clock cycle of the SCK signal after FSYNC goes low.

What is in the data line during our wait cycle ? Garbage ?

Bernhard

quote:

Hä ?

Bit 2 to 16 of the data word ?

Otherwise it should be bit 2 to 17.

Otherwise one bit would be missing on the end.

???

till

Fsynk is WS and its low for the left channel word and goes high one bit before the MSB of the righ channel word starts. Then it goes low again one bit before the next leftchannel word starts. There are more than 16 bit transmitted in each frame the WSis high (low). There are as posted somewere before 32 bit transmitted, but the number is not of interest for us. We only need the 2nd to the 17th as this are, MSB first, our 16Bit containing the sample. The others are garbage.

As i understand until now.

i can only say hä? too, i did not understand what inverting all but LSB means here.

Bernhard

quote:

Originally posted by till
Fsynk is WS and its low for the left channel word and goes high one bit before the MSB of the righ channel word starts. Then it goes low again one bit before the next leftchannel word starts. There are more than 16 bit transmitted in each frame the WSis high (low). There are as posted somewere before 32 bit transmitted, but the number is not of interest for us. We only need the 2nd to the 17th as this are, MSB first, our 16Bit containing the sample. The others are garbage.

As i understand until now.

Okay, FSYNC low left, high right.

But

"invert bit 2 to 16"

does definitely say that only 15 bits have to be inverted.

Does not make any sense to me.

till

Arbeitshypothese

we invert all and increment, as this should be correct. If not someone will post and correct us.

Bernhard

quote:

Originally posted by till
Arbeitshypothese

*lol*

guido

Here we go:

Check out pedja's AD844 design, it has a +2mA current source to do this.

MSB was type error, i meant LSB! Seems to have caused a lot of confusion...

Serial I2S does NOT have to be 16bit words, with 8412 and 7220 it's 32bit words. I2S does not tell you the coding of the data, could be anything. Check out the 1541 datasheet. Both serial modes are I2S, where one is offset binary and one two's
complement (the one we use).

TDA1543 != TDA1543A: first is two's complement, second is Sony Japanese. You will not find a datasheet for the last one...

For Elso: trying to get the dac's as equal as possible by using them +R/-R +L/-L and using S1 matched version.

Back to correcting the LSB, i'll try to explain. If you feed my design with 16 bit words it is very easy: We have WS toggling at LSB. Thank god for that!! Delay with one ff as i have done and you know where the data is. Now XOR WS and WSdelayed and you have this:

MSBXXXXXXXXXXXXXLSBMSB data
1111111111111111000000 WS
1111111111111111111000 WS delay
0000000000000000111000 WS XOR WSdelay

So you have a 'marker' for the LSB. That can be used to not invert data if this is high. Since the data is 16 bit now, the shift register needs to be two times 16 bit. So the connections to the 4517 should not be 32 and 64 output, but 16 and 32. Minor cut and
a small wire.

I will have a look at some receivers to see if i can find one that works with 16bit words i2s out. If it exists, i will use it and correct the LSB error.

And again, a nice programmable cpld can do this easly with 32bit words...

Find yourselfs the application bulletin "Coding schemes used with data converters" from BB.

Greetings,

guido

copy/paste the timing diagram into notepad.
makes more sence then....;)

till

But this doesn´t give a correct inverted dataword?

Bernhard

quote:

Originally posted by guido
Here we go:

Check out pedja's AD844 design, it has a +2mA current source to do this.

MSB was type error, i meant LSB! Seems to have caused a lot of confusion...

Serial I2S does NOT have to be 16bit words, with 8412 and 7220 it's 32bit words. I2S does not tell you the coding of the data, could be anything. Check out the 1541 datasheet. Both serial modes are I2S, where one is offset binary and one two's
complement (the one we use).

TDA1543 != TDA1543A: first is two's complement, second is Sony Japanese. You will not find a datasheet for the last one...

For Elso: trying to get the dac's as equal as possible by using them +R/-R +L/-L and using S1 matched version.

Back to correcting the LSB, i'll try to explain. If you feed my design with 16 bit words it is very easy: We have WS toggling at LSB. Thank god for that!! Delay with one ff as i have done and you know where the data is. Now XOR WS and WSdelayed and you have this:

MSBXXXXXXXXXXXXXLSBMSB data
1111111111111111000000 WS
1111111111111111111000 WS delay
0000000000000000111000 WS XOR WSdelay

So you have a 'marker' for the LSB. That can be used to not invert data if this is high. Since the data is 16 bit now, the shift register needs to be two times 16 bit. So the connections to the 4517 should not be 32 and 64 output, but 16 and 32. Minor cut and
a small wire.

I will have a look at some receivers to see if i can find one that works with 16bit words i2s out. If it exists, i will use it and correct the LSB error.

And again, a nice programmable cpld can do this easly with 32bit words...

Find yourselfs the application bulletin "Coding schemes used with data converters" from BB.

Greetings,

This is very difficult to understand without seeing the design.

But still:

Why shall only 15 bits be inverted ?

Bernhard

quote:

Originally posted by guido
copy/paste the timing diagram into notepad.
makes more sence then....;)

Which timing diagram ?

till

this?

Bernhard

This is the timing diagram from the CS8414 data sheet with connections of M0 M1 M2 as found in the schematics here in the forum.

Bernhard

quote:

Originally posted by till
this?

This is
MSB + 13 bits + LSB (+MSB???)
makes only 15 bits.

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