| Russ White |
Greetings,
Today I have successfully tested a new I/V stage I designed to be used with the PCM1794A and the ESS9008 (though it will work with almost any current output DAC).
The design is loosely based on Nelson Pass' D1 MOSFET I/V stage, but my circuit has some unique features.
I chose to use a CCS load for both the casocde and the output emitter follower. I also made use of parallel devices (because the DACs I am using put out a lot of current) and voltage references. Obviously I chose BJTs instead of FETs and I also use +15V and -5V.
I have not measured it yet, but it sounds great. The simulations look very good, but I know they can't really be relied on.
Here is the CCT schematic. I hope some of you find some use for it in your own projects.
The circuit as shown is configured for the Buffalo(ESS9008) DAC with balanced output of 2VRMs at 0db.
VR3/VR4 set the bias current through the common base amplifier. I found the best results so far by adjusting these until the voltage at the bases of Q11/Q12 was about 6V
VR1/VR2 are used to adjust the voltage at the virtual GND input to 0V
As always, any constructive feedback welcome.
Cheers!
Russ |
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| fierce_freak |
| Looks very interesting to me, Russ, as I'm a fan of Nelson Pass' work. I'll be keeping my eye towards this thread and possible IVY vs. Haiku comparisons. |
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| khundude |
| Why BJTs over FETs? |
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| Blitz |
| THX Russ, great ! What need to be changed to make it work as well with a 1794 ? Can you give us the correct values for that one, too ? THX a lot ! |
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| Mazuki |
| quote: | | THX Russ, great ! What need to be changed to make it work as well with a 1794 ? Can you give us the correct values for that one, too ? THX a lot ! |
And TDA1541 too :D |
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| t5 |
| what's the estimated current draw of one balanced haiku i/v stage? |
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| timpert |
Interesting circuit. I have considered a setup like this myself. Although I never came to a physical implementation of my ideas, and your I/V concept looks really mature to me, I would like to share some contemplations I had when drawing mine up.
I wonder (nitpicking alert!), wouldn't your current sources be more stable hen you connect the ref input of the TL431 to the emitter of one of the current source transistors, instead of to its base? See page 6 on the Fairchild datasheet .
Furthermore, I would consider to generate the base voltage for Q5/6 with an identical transistor connected as a diode with the same bias current, to add thermal tracking. If that's not enough still, it might even be an idea to cascode Q5 and Q6 with an additional transistor, biased by another diode connected transistor in series with the base bias transistor, so both Q5/6 and their base bias transistors have identical Vce, identical dissipation and, when mounted in thermal contact, very good thermal tracking. This ensures that your DAC current output stays at 0V over a wide temperature range.
I didn't find an off-zero output voltage tolerance specification in many DAC datasheets (the TDA1541A sheet states 25 mV though as an exception), but many state that the current output should be held to GND as close as possible.
On the workbench, the benefits of these measures might not stand out immediately or even at all. But in an enclosure, with no knowledge where it is going to be used (on a cold floor, close to a warm lamp, or on top of a hot amplifier), thermal tracking might even prevent a situation where, on one occasion, sound is stellar, and on the other it sounds only so-so. The latter usually occurs when friends are around... |
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| timpert |
| I mean like this. And then thermally couple Q5 to the transistor to the left of it. All four transistors of the same type. And then null the input by adjusting the current through the bias transistors. |
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| timpert |
| Another thought that popped into my mind during lunch break: isn't it a good idea to use a folded cascode? That way, all signals are referred to ground. In the current situation, the output signal is referred to the positive supply, resulting in practically nonexistent PSRR. The demands on the power supply are quite severe this way. |
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| Russ White |
Wow Timpert, a lot to cover. :) Thanks for the comments and the input.
I may try changing the VREFs as you suggest, but in practice the way I have them seems to be working great.
The base voltage for Q5/Q6 needs to be adjustable to zero the virtual ground. I am not sure how I would accomplish that using your scheme.
In practice the circuit seems to be thermally stable. I have heated it with a heat gun and the input node only moved about 5mv. :)
The current through the rest of the circuit is less critical.
I thought about a folded cascode too, and I may try it, but it makes the cct more complex than it really has to be. With a good power supply like the LCBPS things should be just fine. It certianly has no worse PSRR than a D1. :)
Cheers!
Russ |
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| Russ White |
| quote: | Originally posted by Blitz
THX Russ, great ! What need to be changed to make it work as well with a 1794 ? Can you give us the correct values for that one, too ? THX a lot ! |
1.07K for R1A-C R2A-C (1K would be fine too)
Then you simply need to adjust the pots as described earlier.
Cheers!
Russ |
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| dougigs |
I'm always impressed with the things you manage to fit on those tiny PCBs, Russ, and a discrete balanced I/V is a real triumph.
I'll get one anyway, because you make these things fun and easy, but for a future upgrade, you want to think about replacing the board space occupied by those two huge capacitors with a well-designed servo? |
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| timpert |
| quote: | | I may try changing the VREFs as you suggest, but in practice the way I have them seems to be working great. |
Hence the nitpicking alert ;)
The idea behind my scheme is to generate the base voltage required to get an emitter voltage at Q5/6 of 0V by subjecting an identical transistor, connected as diode, to an identical current, and using the resulting base voltage as bias for Q5/6. To ensure that Vce is also identical (or very close) to that of the bias transistor, the second diode connected transistor plus the cascode transistor are included. In this way, both current and voltage for the bias transistor and for Q5/Q6 are identical, meaning identical dissipation, and identical temperature rise.
You could even consider eliminating one bias source and connecting both bases of Q5 and Q6 together to the same bias voltage. This way, the AC base currents cancel out due to differential operation.
If your transistors are identical (not of the same type, but really identical) the above will work and you'll get 0 V on the emitter of Q5/6 if biased like in my figure. And you get 100% thermal tracking because the bias and amplifier transistors are equally warm on the outside and dissipate the same. Even the most picky DAC will always perform as intended this way.
In practice, you'll only achieve this when both transistors are on the same silicon die, or very well matched by their Vbe/Ic characteristics. If you manage this with two transistors, then you'd naturally use them in in the position of Q5 and 6 and use the leftovers for the bias. Therefore, if you make the current source in my figure adjustable, then you can slightly change the voltage across the bias transistors by changing the current through them.
This all sounds like nitpicking XXL, but isn't this what the hobby is all about? ;) Otherwise, I don't intend to say you should do all this, but I hope I've given you some inspiration for further refinement, since there is clearly still room left for experimentation. |
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| Russ White |
Timpert, I am always happy to hear from folks like you I appreciate the food for thought.
Yes I think I see what your getting at with your VB scheme for Q5/Q6. In practice I think it may be difficult to get right.
As I have not seen any serious thermal drift I am happy for now. I can live with 5mv or so.
One other note here. One of the design goals was to make it all fit on a rather smallish PCB 2" x 3.3". This is one reason why the two current sources share a common VREF this is the reason the ref node is not connected to an emitter.
I am struggling a bit with the folded cascode implementation, so if you have an idea there I would be glad to see it, especially if it could be done with just a couple more Qs.
Thank you very much for your interest.
Cheers!
Russ |
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| Russ White |
| For now this has all been done on protoboard, but this is what the PCB will look like (pending any last minute changes). |
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| PigletsDad |
Trivial point about PSRR.
Although the single sided PSRR is small, the PSRR in balanced operation is more or less the CMRR of the following stage, which should be more than good enough, given the high signal levels. This assumes R1A-C and R2A-C are well matched.
For example, even if the +15V supply is pretty nasty (say a 7815 with 10mV of broadband yuckiness), as little as 60dB of CMRR in the next stage pulls this down to 10uV, which is 106dB down on 2V. |
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| Russ White |
| quote: | Originally posted by PigletsDad
Trivial point about PSRR. |
Actually this is a very good point. :)
Very glad to see your interest.
Cheers!
Russ |
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| timpert |
| quote: | | Trivial point about PSRR. |
Not true. The whole point of going for differential is to be more immune to noise and interference coming from the outside, and to double the available signal swing within the range of the power supply (and therefore improving SNR by 3dB, all other things being equal). It is definitely not intended to provide the designer more margin for compromises on signal integrity. At least, that's my personal attitude in this issue. Why double the amount of semiconductors, and after that allow yourself to squander the benefits it gives you? Furthermore, if someone wants to connect an amp that only accepts single ended signals (which most amps do), with a totally clean source he/she's free to do so. But not with a source that is only clean in the differential sense.
Russ, I think that most difficulty lies in the required match of the transistors. If you want to sell your stuff in kit form, that might not be practicable, agreed. I can only imagine the ways that customers invent to mix up matched transistors that all look exactly the same on the outside. If it were for personal use, I'd go for it, but in kits to sell, I would shy away from it too. I didn't take that aspect into account.
A folded cascode will take several more transistors per leg (so it will easily run into 10 or more total) if all the additional current sources are counted as well. Most difficult part will be a current source from the positive rail that is coupled to the one from the negative rail, so the current outputs will track. Although the cascode itself is only one extra transistor, it's the biasing that kills off the idea when space is tight. I could draw up something, but that will have to wait until tomorrow. |
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| Russ White |
Timepert,
I am still investigating your ideas.
I can see your point on PSRR especially as it relates to single ended signals, but this I/V is not really intended for single ended output.
I have no problem using an opamp for the summing. Then you should still get a good clean signal from the whole rig.
On my case I would just use the last half of my own IVY board.
Cheers!
Russ |
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| Russ White |
What about something like this...
I just tested it and even with pretty poorly matched Qs it seems to track pretty well. Less than 2mV drift when heated a good 30 degrees.
And it the nice thing is it does not effect the layout much. It just swaps one resistor for one transistor, and moves the pot.
I simulated it first like this: |
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| timpert |
Hi,
Just couldn't resist looking...
Much better! And it has an added bonus too: it will make the DC on the DAC output much less susceptible to power supply variations than the resistive divider you used previously. All in all a superior solution with the equal amount of parts. If you wish to eliminate even more, connect the bases of Q5/6 (in the original schematic) together and use a single bias voltage. That way, the base AC currents cancel out. Of course, this requires Q5/6 to be matched.
The folded cascode is something I'd have to draw in a schematic, and I don't have time for that right now. You already seem to have a workaround for single-ended output, but if you're still interested, please let me know and I'll find some time. |
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| Russ White |
Thanks Timpert,
I will change the circuit to reflect what I have learned. Thanks for the ideas.
I am experimenting with the folded cascode idea. Please share if you draw something up. I would love to see it.
Cheers!
Russ |
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| lfat |
Hello Russ!
About discrete oprational amplifiers...I had good experiences with the stuff Erno Borbely makes..what do You think of his designs.?
Do want to achieve the same level or beyond with fewer and cheaper parts?
regards
Georg |
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| Russ White |
| quote: | Originally posted by lfat
Hello Russ!
About discrete oprational amplifiers...I had good experiences with the stuff Erno Borbely makes..what do You think of his designs.?
Do want to achieve the same level or beyond with fewer and cheaper parts?
regards
Georg |
I have a fully differential (super symmetrical) discrete op amp in the works, and it works very very well, but this particular design is for those who want to try something with no global feedback.
You can read about that design here:
http://www.diyaudio.com/forums/show...986#post1444986
Cheers!
Russ |
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| Russ White |
OK one option would be to use a THAT300 device and parallel two of the Qs to get the base reference voltage for Q5 and Q6. The should give us ideal thermal tracking/coupling and excellent device matching.
I am guessing I would want to put a small resister at the emitters of the ref Qs to make them share current equally.
What do you guys think?
Something like this, and please forgive the roughness of the simulation I did it quickly:
Cheers!
Russ |
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| Russ White |
OK, here is a proper schematic with the THAT300 devices and only one TL431. :) Don't need the big caps at the VREF anymore.
I don't have any of the THAT300s handy to test right now, so I just am using BC550s. But it works fine! :)
Here is revision 2:
Cheers!
Russ |
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| Terry Demol |
| quote: | Originally posted by Russ White
OK, here is a proper schematic with the THAT300 devices and only one TL431. :) Don't need the big caps at the VREF anymore.
I don't have any of the THAT300s handy to test right now, so I just am using BC550s. But it works fine! :)
Here is revision 2:
Cheers!
Russ |
Hi Russ
2 questions,
- How does it measure (simulated)?
- How does it sound compared to the OPA version?
You previously mentioned a lot of OOB noise from this dac,
so the non GFB design may be an advantage in this regard.
cheers
Terry |
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| Russ White |
Hi Terry,
Well I have only heard one mono channel. :) So I can only say it seems to sound fine. Absolutely no noise or hiss. I will have to leave the heavy duty listening until I can make up another channel.
This is what the simulation says for 20khz into 47K load 2VRMs differential.
| code: |
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 2.968e+00 1.000e+00 179.99° 0.00°
2 4.000e+04 3.328e-09 1.121e-09 158.19° -21.79°
3 6.000e+04 1.558e-06 5.250e-07 -144.69° -324.68°
4 8.000e+04 1.296e-09 4.366e-10 -77.55° -257.54°
5 1.000e+05 1.627e-08 5.483e-09 39.11° -140.88°
6 1.200e+05 2.221e-09 7.484e-10 83.65° -96.34°
7 1.400e+05 5.012e-09 1.689e-09 170.24° -9.75°
8 1.600e+05 6.735e-10 2.269e-10 -168.03° -348.02°
9 1.800e+05 9.354e-10 3.152e-10 -113.09° -293.07°
Total Harmonic Distortion: 0.000053%
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| Russ White |
| Input impedance is about 180mOhm all through the audio range and up to 220mOhm at 1Mhz. |
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| Terry Demol |
| quote: | Originally posted by Russ White
Hi Terry,
Well I have only heard one mono channel. :) So I can only say it seems to sound fine. Absolutely no noise or hiss. I will have to leave the heavy duty listening until I can make up another channel.
This is what the simulation says for 20khz into 47K load 2VRMs differential.
| code: |
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 2.968e+00 1.000e+00 179.99° 0.00°
2 4.000e+04 3.328e-09 1.121e-09 158.19° -21.79°
3 6.000e+04 1.558e-06 5.250e-07 -144.69° -324.68°
4 8.000e+04 1.296e-09 4.366e-10 -77.55° -257.54°
5 1.000e+05 1.627e-08 5.483e-09 39.11° -140.88°
6 1.200e+05 2.221e-09 7.484e-10 83.65° -96.34°
7 1.400e+05 5.012e-09 1.689e-09 170.24° -9.75°
8 1.600e+05 6.735e-10 2.269e-10 -168.03° -348.02°
9 1.800e+05 9.354e-10 3.152e-10 -113.09° -293.07°
Total Harmonic Distortion: 0.000053%
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Good results and predictably H3 dominant.
If you look at each phase, the H2 will be around 10 x the residual
H3 of the balanced OP measurements as shown... it's like cheating
a bit :)
The almost zero PSRR of each phase means good PS is
required and will be pretty audible.
WRT noise, generators will be CCS's, a different scenario to the
typical opamp arrangement noise wise.
Nice design.
cheers
Terry |
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| Russ White |
| quote: | Originally posted by fierce_freak
Nice, Russ! |
| quote: | Originally posted by Terry Demol
Nice design.
cheers
Terry |
Thanks Guys! :)
Lets see how the real thing does.
I am still open to looking at a folded cascode solution.
Cheers!
Russ |
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| Russ White |
| quote: | Originally posted by dougigs
or a future upgrade, you want to think about replacing the board space occupied by those two huge capacitors with a well-designed servo? |
Hi,
Unfortunately in its current form a servo is not really practical.
I imagine it would be more plausible to do one on a cascoded version.
Cheers!
Russ |
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| wildmonkeysects |
Most XLNT.
This basic theme is classic, and to my ears, far superior to the use of monolithic opamps for i/v. No slew induced jitter or feedback exacerbated thermal tails.
Some ideas:
The emitter followers, Q1 and Q2 are optional or redundant here, as the output impedance without them is under 200 ohms per leg.
And, if you add a cascode at the collectors of the input transistors, QA1.1 and QA1.2 you will have a true stasis or constant power stage, ala Lavardin, with thermal tails an order of magnitude or more lower. And, more linear. Might need a bit of compensation to remain loop stable, might not, but well worth it for sonics. Likewise, add cascodes at the collectors of Q7 and Q8 to further reduce thermal modulations of the bias current.
The input devices can be jfets. Slightly higher input impedance, maybe an ohm rather than fractions of a ohm. Might be happier with an offset servo.
One can also (cough, cough) use an xfmr for the output. With the center tap to +15, a balanced feed with a single resistor and cap across the primary would give sufficient psrr, good filtering, and isolate grounds. Again, amorphous cores, to my ears, don't sound like traditional trannies...YMMV. Lundahl is your friend if purchased in Euros. |
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| timpert |
| quote: | | The input devices can be jfets. Slightly higher input impedance |
Wouldn't do that, because due to the high input impedance, the I/V converter is unable to maintain the DAC output close enough to 0V. Most modern DACs aren't amused by this and performance degrades.
As soon as time permits I'll draw up a folded cascode. It shouldn't be hard to implement. |
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| Russ White |
| quote: | Originally posted by wildmonkeysects
Most XLNT.
The emitter followers, Q1 and Q2 are optional or redundant here, as the output impedance without them is under 200 ohms per leg.
And, if you add a cascode at the collectors of the input transistors, QA1.1 and QA1.2 you will have a true stasis or constant power stage, ala Lavardin, with thermal tails an order of magnitude or more lower. And, more linear. Might need a bit of compensation to remain loop stable, might not, but well worth it for sonics. Likewise, add cascodes at the collectors of Q7 and Q8 to further reduce thermal modulations of the bias current.
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Hi WMS,
Thanks for taking the time to look and to comment.
I added the emitter followers just to get the output imedance as low as I could. I agree they may not be needed and are optional.
I just simulated adding in cascodes at the places you mentioned.
The cascode at the input pair has the bases of the cascode Qs(VBIAS) up 2.5V from GND. I needed 50pf compensation to make it stable in simulation.
The cascode at the CCS has VBIAS at GND.
THD number were just a tad worse (about .000098 at 20khz) , but the input impedance went down about 100mOhm to about 115mOhm.
The down side is it adds four more parts (resister, VREF,2 Qs) but I guess it is probably worth it. :)
Thanks for the ideas.
Cheers!
Russ |
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| Russ White |
| Simulation FFT with WMS cascodes added: |
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| timpert |
Hi Russ,
Could you post the new (cascoded) schematic? |
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| Russ White |
| quote: | Originally posted by timpert
Hi Russ,
Could you post the new (cascoded) schematic? |
Sure here it is, but keep in mind this one is untested. |
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| Russ White |
| Here is the frequency response with the 10nf filter caps and the DAC configured for the Buffalo. |
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| Russ White |
| Better with grid. :) |
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| Russ White |
I think I am going to go ahead and bag the emiiter followers at the output.
The reason is for any heavy load a person is going to want a buffer anyway. Any load from 10K up should be fine without it.
This way even if I add the cascodes I end up with a reasonable number of parts to try to fit on a Buffalo/COD size board, which is 3.3" x 2".
Cheers!
Russ |
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| Russ White |
I am also weighing the value of the two cascodes at the input CCS.
I am not sure how much they actually help, in simulation the results are pretty much the same with or without them, even with drastic temperature changes. |
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| Russ White |
Ok I figured it out how to lower the input Z. Or rather the relationship between the current through CFP and the input Z. :)
The more current through QA1.1/QA1.2 the lower the Z.
with 1K at R3/R4 the input Z is around 250mohm while changing those to 100ohm make the input Z 70mohm.
The trade off is slightly worse THD the lower R3/R4.
Cheers!
Russ |
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| fierce_freak |
| quote: | Originally posted by Russ White
the input Z 70mohm.
The trade off is slightly worse THD the lower R3/R4.
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Impressive...I think that's worth it :) |
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| Russ White |
| quote: | Originally posted by fierce_freak
Impressive...I think that's worth it :) |
Well the question is how low to go. :)
In simulation it seems 221R at R3/R4 is a sweet spot. The input Z is still < 100 mohm but THD is still right around .000085% at 20khz.
I think that's probably what I will try.
Cheers!
Russ |
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| wildmonkeysects |
With a decent topology like this, it's all varying degrees of good.
Lavardin might want a small royalty, even though this implementation is different enough that it probably wouldn't hold up. Their cascode is outside/above the CFB loop, and they use a current source to the positive rail rather than a Vbe set resistor as this (and peufeu's) do. But IANAL just ENGR.
One could argue that the virtual ground input node acts as a cascode for the current source(s), but, if there is space and budget, cascodes ususally sound better to my ears. Cleaner.
Yes, since it will likely be driving 10k and up loads, less than 200 ohms output impedance per leg is fine. Some designs deliberately "damp" emitter followers with 100 to 1k ohms series resistors to ensure stability with all potential reactive loads, so you are ahead of the game leaving them out.
Will you include an option to set the input node DC point, ie 1.6V for Sabre, and gnd/0V for others?
Share and enjoy,
WMS |
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| Russ White |
Hi WMS,
It seems there is nothing new under the sun. :)
As to the DC input point.
I have taken measurements of the Buffalo into the IVY(THS4131 configured for I/V) and it seems to settle at 760mv. So that makes me wonder, if the point should be 0V or 1.65V or .76V. :confused:
Or if the IV stage should be set to 0V with no input and allowed to drift naturally with the current applied from the DAC.
I really don't know what is best.
Cheers!
Russ |
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| Terry Demol |
| quote: | Originally posted by Russ White
Hi WMS,
It seems there is nothing new under the sun. :)
As to the DC input point.
I have taken measurements of the Buffalo into the IVY(THS4131 configured for I/V) and it seems to settle at 760mv. So that makes me wonder, if the point should be 0V or 1.65V or .76V. :confused:
Or if the IV stage should be set to 0V with no input and allowed to drift naturally with the current applied from the DAC.
I really don't know what is best.
Cheers!
Russ |
Russ,
Are you saying that Vref on Sabre drifts slowly??
cheers
Terry |
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| Russ White |
| quote: | Originally posted by Terry Demol
Russ,
Are you saying that Vref on Sabre drifts slowly??
cheers
Terry |
No, not at all, it stays right at 760mv all the time into IVY. |
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| Russ White |
I actually think it may have to do with the way the THS4131 works.
On my prototype Haiku I have the input node close to zero, and it seems to be working fine. So I am not sure why I would want to set it to 1.65V is what I am saying... |
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| Terry Demol |
| quote: | Originally posted by Russ White
No, not at all, it stays right at 760mv all the time into IVY. |
Russ
Are you saying if you were to disconnect I-V, then dac OP will sit at
+760mV with 0 signal?
T |
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| Russ White |
| quote: | Originally posted by Terry Demol
Russ
Are you saying if you were to disconnect I-V, then dac OP will sit at
+760mV with 0 signal?
T |
Terry, the THS4131 is at 0V with the DAC disconnected. Its at 760mv with it connected. But it stays at 760mv even with 0db (full scale) signal (checking with my PC oscilloscope) so I know the input impedance is indeed close to zero. I don't understand exactly why the 760mv appears. :)
Cheers!
Russ |
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| Russ White |
Interestingly, the same exact value appears in simulation with the THS4131 model provided from TI. :) And a similar value in my discrete opamp version which is quite similar.
Now, the Haiku is a very different beast. It only budges a few mv whether the DAC is connected or not. :)
Cheers!
Russ |
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| Terry Demol |
| quote: | Originally posted by Russ White
Terry, the THS4131 is at 0V with the DAC disconnected. Its at 760mv with it connected. But it stays at 760mv even with 0db (full scale) signal (checking with my PC oscilloscope) so I know the input impedance is indeed close to zero. I don't understand exactly why the 760mv appears. :)
Cheers!
Russ |
Russ,
OK I get it now.
Ref fig 29 THS413x data sheet for explanation of relationship of
Vocm to OP offset / IP.
THS413x IP's common mode point is set by the FB resistors,
CM current into IP and will shift to make OP match whatever Vocm is.
So if you set Vocm to 0V, THS413x OP will be at 0V. When Sabre
sources current from THS IP then that current must be equal to
the CM current in the FB resistors on THS. So the IP of THS shifts
high by whatever amount is required for these currents to
be equal.
Clear as mud? :cool:
cheers
Terry |
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| Russ White |
| Actually yes, I have been looking it over and it actually does make sense to me now. :) |
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| Terry Demol |
| quote: | Originally posted by Terry Demol
Russ,
OK I get it now.
Ref fig 29 THS413x data sheet for explanation of relationship of
Vocm to OP offset / IP.
THS413x IP's common mode point is set by the FB resistors,
CM current into IP and will shift to make OP match whatever Vocm is.
So if you set Vocm to 0V, THS413x OP will be at 0V. When Sabre
sources current from THS IP then that current must be equal to
the CM current in the FB resistors on THS. So the IP of THS shifts
high by whatever amount is required for these currents to
be equal.
Clear as mud? :cool:
cheers
Terry |
| quote: | Originally posted by Russ White
Actually yes, I have been looking it over and it actually does make sense to me now. :) |
Data sheet seems to indicate 1.65V is optimum for dac OP point
which would be 1.65V for Vocm on THS chip.
It would be interesting to know where Sabre is most linear, but only
Dustin will know that from the internal analog design.
Is he still around here?
cheers
T |
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| Russ White |
| I just wonder why it would matter for a current source, as long as the impedance is low.... |
|
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| Russ White |
| Ultra simplified folded cascode I/V :) Just to show I have not been lazy. ;) |
|
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| Terry Demol |
| quote: | Originally posted by Russ White
I just wonder why it would matter for a current source, as long as the impedance is low.... |
The answer is probably already looking at us in the data sheet.
With voltage OP Sabre still gets -108dB THD, and that is a dynamically
changing OP state.
Any fixed OP state has to be better WRT linearity of the unity
weighted bit OP architecture. |
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| timpert |
This thread is really going somewhere, but all the interesting discussions take place while I'm asleep! No matter what I try, I'll always be late with my replies. Quite hard to participate in this way.
The folded cascode you drew up looks like the concept to aim for. If you add the current mirroring of the original schematic to Q2, then you'll have something that is very hard to beat! |
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| Cauhtemoc |
| quote: | Originally posted by Russ White
Ok I figured it out how to lower the input Z. Or rather the relationship between the current through CFP and the input Z. :)
The more current through QA1.1/QA1.2 the lower the Z.
with 1K at R3/R4 the input Z is around 250mohm while changing those to 100ohm make the input Z 70mohm.
The trade off is slightly worse THD the lower R3/R4. |
The higher THD is because the transistors are less linear at the increased current. Otherwise you are pretty much spot on; higher current means a lower input impedance. |
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| matejS |
| quote: | Originally posted by Russ White
Hi WMS,
It seems there is nothing new under the sun. :)
As to the DC input point.
I have taken measurements of the Buffalo into the IVY(THS4131 configured for I/V) and it seems to settle at 760mv. So that makes me wonder, if the point should be 0V or 1.65V or .76V. :confused:
Or if the IV stage should be set to 0V with no input and allowed to drift naturally with the current applied from the DAC.
I really don't know what is best.
Cheers!
Russ |
IVY's 760mV is due to input resistors. Since Sabre is a voltage out w/ 195ohm output resistance, I say it should be referenced to 0V (you will get a little less than 9mA of bias current). Sabre output is really quite good and can handle output input impedance w/o problems (there is a little THD loss due to internal resistors' temperature coefficient).
But I might be wrong ;)
Cheers,
Matej |
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| matejS |
I've forgot to mention one thing: 100mOhm or 200mOhm would not make any sound difference (at to Sabre), more important is that it is constant no matter what output amplitude is.
Cheers,
Matej |
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| analog_sa |
| quote: | Originally posted by matejS
Since Sabre is a voltage out w/ 195ohm output resistance, |
It is? |
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| Russ White |
| quote: | Originally posted by matejS
IVY's 760mV is due to input resistors.
But I might be wrong ;)
Cheers,
Matej |
I was talking about the IVY configured for true I/V. No resistor on input, just a jumper. :)
Cheers!
Russ |
|
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| Terry Demol |
| quote: | Originally posted by matejS
IVY's 760mV is due to input resistors. Since Sabre is a voltage out w/ 195ohm output resistance, I say it should be referenced to 0V (you will get a little less than 9mA of bias current). Sabre output is really quite good and can handle output input impedance w/o problems (there is a little THD loss due to internal resistors' temperature coefficient).
But I might be wrong ;)
Cheers,
Matej |
Unfortunately, I believe on both accounts.
WRT offset, ref my post above and ref to THS41xx data sheet.
WRT voltage OP THD, it is more the active devices used for switching
the unity weighted OP bits rather than the resistors themselves.
cheers,
Terry |
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| Russ White |
:)
I will let the PDF do the talking.
Well ok a few hints...
No DC offset at the outputs, and no output caps.
Cascodes all over, including a couple folded ones.
Input impedance is about 80mOhm.
Only one resistor to set output voltage.
Only one cap for the bulk of filtering.
But this is no longer a Haiku. It deserves a name of its own.
I am leaning toward "Counterpoint".
Please keep in mind. The attached schematic is neither finished nor tested. Just simulated. But it only needs a few tweaks I think.
Cheers!
Russ |
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| wildmonkeysects |
Looks like you've caught cascode fever, which is a good thing. Fortunately, small signal silicon is relatively cheap.
But don't stop there...do consider also cascoding Q24, Q23, Q9/29, Q30/30, Q12, Q4. Fortunately...
Even if you decide these ones to be unnesc, do consider leaving pads/holes for mods to add them.
Possibly consider a large cap at the OCM node to have the offset track the average of the signal, rather than the actual signal. Offset loops are usually happier that way.
And, look at the corner frequency of the input impedance, wherever it occurs, 1k, 10k, wherever. Consider adding a cap (single cap hooked up differential) at the input to match somewhere around that knee. Adjust to keep the loop stable. This may seems counterintuitive, as in it would appear to increase noise gain of the loop. However, when tuned, it would further cut down out band noise.
Share and enjoy,
WMS |
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| Russ White |
Hi WMS. :) Yes I had thought about cascoding those Qs too, but was not sure how many Qs I really wanted to add. :)
As for the servo bit, I was actually hoping that by actually tracking the signal I might gain some linearity and that each end could then actually be used signal ended with lower distortion simulation bears this out. The two Cs at the summing point keep that bit stable.
I will look into the filtering bit.
Cheers!
Russ |
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| Russ White |
One other note the way I drew the schematic makes it seem that the two halves are inverting. They are not. :) It was just a typo when designating OUT+ and OUT-.
Cheers!
Russ |
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| Russ White |
| Here is a plot of input Z |
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| Russ White |
Simulation results. (I know, its just a sim)
Here is the FFT at 20khz 0db input for buffalo 2VRMS output 10K load.
-128db THD.
| code: |
Fourier components of V(out+,out-)
DC component:2.20805e-010
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 2.799e+00 1.000e+00 -6.90° 0.00°
2 4.000e+04 3.181e-10 1.136e-10 -71.26° -64.35°
3 6.000e+04 1.102e-06 3.936e-07 4.42° 11.32°
4 8.000e+04 6.027e-10 2.153e-10 -70.32° -63.42°
5 1.000e+05 6.899e-09 2.465e-09 166.18° 173.08°
6 1.200e+05 1.030e-09 3.680e-10 110.83° 117.73°
7 1.400e+05 5.653e-09 2.020e-09 -8.89° -1.99°
8 1.600e+05 6.990e-10 2.497e-10 -77.65° -70.74°
9 1.800e+05 1.046e-08 3.736e-09 130.35° 137.25°
Total Harmonic Distortion: 0.000039%
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| fierce_freak |
| Wow, very promising results. I'd love to see real world measurements eventually. |
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| Russ White |
Thanks freak.
I will probably lay this out pretty soon, along with the Haiku too (actually already done the Haiku). As I think both will sound great.
Whats interesting about this "counterpoint" circuit, is I basically took my own discrete fully differential opamp, removed the feedback and the output stage, added some current, and a resistor and filter caps, took the input at the emitters of the input pair instead of the bases, then some tweaking, and there you have it....
CMRR and PSRR should both be excellent.
Cheers!
Russ |
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| Terry Demol |
| quote: | Originally posted by Russ White
:)
I will let the PDF do the talking.
Well ok a few hints...
No DC offset at the outputs, and no output caps.
Cascodes all over, including a couple folded ones.
Input impedance is about 80mOhm.
Only one resistor to set output voltage.
Only one cap for the bulk of filtering.
But this is no longer a Haiku. It deserves a name of its own.
I am leaning toward "Counterpoint".
Please keep in mind. The attached schematic is neither finished nor tested. Just simulated. But it only needs a few tweaks I think.
Cheers!
Russ |
| quote: | Originally posted by Russ White
Simulation results. (I know, its just a sim)
Here is the FFT at 20khz 0db input for buffalo 2VRMS output 10K load.
-128db THD.
| code: |
Fourier components of V(out+,out-)
DC component:2.20805e-010
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 2.799e+00 1.000e+00 -6.90° 0.00°
2 4.000e+04 3.181e-10 1.136e-10 -71.26° -64.35°
3 6.000e+04 1.102e-06 3.936e-07 4.42° 11.32°
4 8.000e+04 6.027e-10 2.153e-10 -70.32° -63.42°
5 1.000e+05 6.899e-09 2.465e-09 166.18° 173.08°
6 1.200e+05 1.030e-09 3.680e-10 110.83° 117.73°
7 1.400e+05 5.653e-09 2.020e-09 -8.89° -1.99°
8 1.600e+05 6.990e-10 2.497e-10 -77.65° -70.74°
9 1.800e+05 1.046e-08 3.736e-09 130.35° 137.25°
Total Harmonic Distortion: 0.000039%
|
|
Russ,
Well you have done a pretty damn good job.
I was interested to see how you were going to get the (folded)
cascode linear, as this is where the linearity usually gets spoiled.
As you probably found out, you need the CFP in the folded cascode
part to get linearity similar to the non folded design.
I don't quite get the dc offset arrangement, I'm thinking Vocm
actually needs to come from a common mode sum of both outputs,
presumably LP filtered.
As such it becomes a type of CM servo comparing OP with ground,
yes?
I have been doing many folded cascode designs myself, somewhat
different to yours. They go from simple to pretty complex.
So far my best result, which is a fairly complex CCT simulates at
< 0.000002% (-156dB) between phases (balanced OP) and
~ 0.000005% (-146dB) at each phase OP THD.
That is with Sabres 195 R / 8mA at IP and 2V RMS OP per phase.
Admittedly at these low levels it's just a numbers game but it
was an interesting challenge to progressively identify and eliminate
/ reduce all the non linearities.
Also probably at these levels of simulated distortion, I think other
things will be more audible. As WMS has stated, probably thermal
junction effects will be one of them.
Also, when you implement the double CFP folded arrangement,
don't be surprised if you get oscillation problems. CFP's really love
to oscillate when done on real world pcbs. If such is the case,
base stoppers, usually a hundred ohms or so can settle things.
The only other thing I wanted to mention about your design is that
it looks to have a pretty high noise gain from the various CCS's
to OP R. This means that all the various CCS BJT's voltage noise will
be multiplied by the ratio of load R to CCS R.
This can be rectified by using lower noise BJT's in CCS's and
increasing the ref voltage and R value.
Also, just thinking about it the CCT appears to have very high CM
OP impedance, since load R is floating between phases.
This may have some large noise implications, depends on how the
CM servo is implemented.
Cheers
Terry |
|
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| Terry Demol |
| quote: | Originally posted by Terry Demol
Also, just thinking about it the CCT appears to have very high CM
OP impedance, since load R is floating between phases.
This may have some large noise implications, depends on how the
CM servo is implemented.
|
Just saw the OCM network on your schematic 20k//22p, I missed it
hiding down there.
So disregard the statement above about high CM OP impedance,
complete opposite. doh!
For OP noise gain calcs, it appears the effective OP load would be
365R. However, and this is pretty interesting, the CM servo will
force the noise to appear on both outputs differentially.
At a first educated guess, it appears that all the CCS noise
generators need to be multiplied by noise gain, summed
RMS and then will appear fully differentially at both OP's.
Bruno Putzeys would be interested to see this CCT, he is
a bit of a differential circuit wiz.
cheers
T |
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| Russ White |
Hi Terry,
Thanks for good input and kind words.
I can actually did get my cct to simulate next to zero distortion(which is why I think simulation distortion measurements are bollocks, but fun to look at) , but to do that I have to run a lot of current through it and run it right on the edge of stability. Distortion goes up a bit in the cct shown because I added some compensation, but it should be pretty stable I think. If I need to I will add base stoppers, but I am hoping not to have to.
BC550 and BC560 are low noise types, so things should be pretty good to use all the way around the CCT. Any other part suggestions?
Yes my servo is a bit more than an ordinary servo, that is to say its correction bandwidth extends well beyond audio range. :) The very very cool thing I am finding with this cct is that the outputs can easily be taken single ended with just a trivial loss in THD. So people can use this with no BAL/SE conversion. Just double the I/V resistor and halve the filter C and you will get 2VRMS at each phase OP and similar filter response.
Cheers!
Russ |
|
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| Terry Demol |
| quote: | Originally posted by Russ White
Hi Terry,
Thanks for good input and kind words.
I can actually did get my cct to simulate next to zero distortion(which is why I think simulation distortion measurements are bollocks, but fun to look at) , but to do that I have to run a lot of current through it and run it right on the edge of stability.
|
I'm surprised you actually ran it at higher currents, it already has
quite a bit running through those bc560's. You are a brave man!
| quote: |
Distortion goes up a bit in the cct shown because I added some compensation, but it should be pretty stable I think. If I need to I will add base stoppers, but I am hoping not to have to.
|
Are you referring to the 22pF // 20k on the OCM network?
| quote: | [/B]
BC550 and BC560 are low noise types, so things should be pretty good to use all the way around the CCT. Any other part suggestions?
[/B] |
BC337 type is lower noise.
TL431 is a big noise generator, ~ 40nV/rt Hz, but CM servo will come
to the rescue here as 431's noise will manifest CM, which is lucky.
T |
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| Russ White |
I was actually speaking of the 1nf to GND at the OPs. :) Its actually a filter but it seems to stabilize the cct, probably just by lowering the bandwidth.
Cheers!
Russ |
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| Bricolo |
Nice circuit!
Using common base, folded cascodes and cascoded CCS makes a lot of sense. Nice way to place R1 in a differential way, also!
But what is the secret behind the use of the CFP transistors here?
I played a bit with simulations on I/V converters some time ago, and found that a significant contribution to the THD is the current that gets "lost" (or leaked) by the common base input transistor.
You'll always get some leak there, with a basic transistor it's due to it finite beta. Having a leak is okay as long as it is constant, but it is not. Beta changes wrt current and voltage.
Switching to a darlington only reduces the effect by an order of another beta, but it doesn't dissapear.
Is the CFP better for that? |
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| Russ White |
Thanks Bricolo,
I am afraid I don't feel qualified to answer your questions. :)
I used the CFPs because the distortion went way down after I put them in. :)
The cascodes I used to remove thermal effects from key areas.
The folded cascode I used to refer the output to ground and improve PSRR.
For all to review here is a more polished schematic of the "Counterpoint" IV stage.
I think it nearly done.
Any suggestions for refinement are welcome.
Notice I changed the way I took the OCM voltage. :) I like this solution much better. RG1/RG2 set the voltage gain and create the common mode voltage at the same time. :)
I also figured out how to better compensate the servo Diff pair with C1.
Please forgive that some of the part numbers are out of sequence. I still need to clean it up for the final schematic.
Cheers!
Russ |
|
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| Russ White |
| quote: | Originally posted by Russ White
The folded cascode I used to refer the output to ground and improve PSRR. |
I have to correct myself here, the output is not referred to ground really, but to the opposing output. And both outputs are set to track GND via the OCM servo. :)
Cheers!
Russ |
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| Russ White |
OK, doing some more simulation I find that the schematic I just posted starts up (with DC supplies ramped from 0) very very badly.... So forget it....
Fortunately the fix is easy. It looks like the gain setting resistors need to be referred to GND and not each other to get a good startup.
I will post a fixed schematic tomorrow. Time for bed here.
Cheers!
Russ |
|
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| Cauhtemoc |
| quote: | Originally posted by Terry Demol
I have been doing many folded cascode designs myself, somewhat
different to yours. They go from simple to pretty complex.
So far my best result, which is a fairly complex CCT simulates at
< 0.000002% (-156dB) between phases (balanced OP) and
~ 0.000005% (-146dB) at each phase OP THD.
That is with Sabres 195 R / 8mA at IP and 2V RMS OP per phase. |
Do share. :) |
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| wildmonkeysects |
Major logorheia here...FWIW, here's a way I look at circuits, ss ones. Please forgive if it, or some of it seems obvious, or not very original, but the magic is in the subtlties.
In rare moments of organization I divide circuits into support (static, bias, current source) and active (signal path), of which the active parts are further categorized as brain and brawn parts. Servos, if they are truly subsonic, I will call support, but if in the audio band, are active.
In Haiuku 4, Q11 is the brain, Q26, 25, 13, 34 are the brawn for example.
The load line of Q11, or any active "brain" device will be somewhat non-linear; by adding brawn as either constant current or constant voltage, the load line becomes horiz or vert, or with both CC and CV, a "load dot". Beyond sims, in meatspace usually takes a few compensation tricks to stay stable, but lots of good things happen. The composite/stasis is very linear, minimal thermal tails, minimal base current variations with signal. Keep the brain on a separate die/substrate/package from the brawn to keep the brawn from thermally modulating the brain. Halcro, Lavardin, and our own peufeu have touched on this before.
For each brain device, look at the ratio of delta power under signal conditions to idle power. The smaller the better. Depending on the sim tool, this will be easy, or may need to be done manually, but can be used to fine tune implementations.
For support circuitry, like current sources: cascoding usually does not add loop stability issues, but almost always gives higher PSRR. This is important in meatspace, where less than ideal conditions exist. Even if in a differential circuit, where one could presume cancellation will happen, in the act of cancellation, the devices are being modulated. And, more importantly, lessens self modulation of the device(s) it is feeding, for instance Q24, 42, 45, if cascoded will not modulate slightly as the output node swings with signal. Q9 could also use a cascode, not for signal self modulation, but for increased PSRR.
Q34 may not be nesc, as the folded cascode holds the first stage in CV. But, a cascode of Q23 would be a very good idea. (and other half). For the orig Haiku, Q34 is needed, as the signal swings the load above it.
Running the devices "hot" up to a point is a good thing. Frinstance TO92 packages generally will not crack through thermal cycling if dissipating less than say 40 mW each. Electron/hole density can be surprisingly low, ie rough texture, in low power bipolar transistor circuits, and you get a higher idle power to swamp out the delta power of the brain devices. Subjectively, more liquid.
I think of the servo bandwidth like a Yacht, if you need to ask, don't. The circuit without audio band servo correction is quite linear, and unless Q5,6,7,8 are supported with brawn devices and made into "load dot" devices, all of the usual stuff will be injected into the mix. If the servo BW is made subsonic, then the tails/modulations of Q5,6,7,8 will be less if not relevant, and they won't need brawn support.
Once one gets below one ppm, minus 120dB steady state specs, why not take into account the subtle dynamic phenomena...as it will enhance the specs *and* the sonics. Otherwise, one ends up with something that measures good, meets "ob specs" but just doesn't quite sound or feel right.
Think of the Hermes Archetype, the communicator who is also the trickster: measurements will not specifically lie to you, but will not tell you whole story either, and will not tell what they are not telling you.
Hey, how about calling this the "Manx"...no (thermal) tail...?
Terry, if what you are doing with folded cascodes is not proprietary or NDA'd to some entity, please do share. It's so easy to overlook the obvious, till someone points it out...and we are here to point that out to each other. Probably something really important I'm overlooking, but will catch that next cycle... |
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| Russ White |
Hi WMS,
Thank you very much for your valuable insight. I have reflected on your post and modified my circuit.
I also figured out how to make it start up stably (at least in simulation) without having to tie the load resistors to GND. :)
As for the servo, It is very very similar to the approach TI used in the THS4131, though I am not sure how much bandwidth theirs has.
Here is the current state of the work in progress. :)
Thanks again, I really appreciate the chance to think critically.
The 1.65V input common mode VREF for the ESS DAC would probably be an LM4041 or similar. Suggestions welcome.
Cheers!
Russ |
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| Russ White |
WMS, here is a version with Q23/Q12(themselves cascodes) cascoded.
Is this what you meant? |
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| wildmonkeysects |
Yes, that's it. Leds for voltage. You could make R40 the voltage reference.
Thinking about the ESS Sabre: it's good news bad news about the lowish output impedance of the chip, around 200 ohms. Good for voltage out with minimal external parts. Good for passive filtering in that mode. Bad news that any modulation/shift of the input current sensing node of the i/v will be proportionally more sensitive than compared to a current out DAC with a higher intrinsic impedance. So, a quiet device to raise V3 to 1.65V is a good idea. Maybe a current source for VR1 for higher PSRR?
How about the final cascode, for Q24,42,45...?
Something is squirrely about the OCM circuit. Do you mean to derive a CM signal that could be made wide or low bandwidth with a cap change?
It is likely that the TI chip uses a wide BW correction loop. Either way, with this discrete circuit, one could add a series R and up C1 to use a low BW subsonic offset loop.
How does removing the (now redundant) cascode from Q11 effect input impedance? Does Q11's dissipation stay low enough with a higher Vce sans cascode? I didn't think of that last cycle...
This is a very promising project! |
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| Russ White |
| quote: | Originally posted by wildmonkeysects
How about the final cascode, for Q24,42,45...?
This is a very promising project! |
Yes the cct simulates better with higher impedance sources.
But I think it should do fine with the ESS Sabre.
I added the final cascode. :)
And I took out the cascode of the cascode. :D Because it only seemed to harm the THD very badly and made the cct hard to stabilize. I am not sure its worth the trouble to add it and its reference voltage.
Now here is what is really cool. The cct simulates much better at each output now (with the new cascode at Q24 et al)
In fact THD comes out virtaully the same at each output to GND or the differential output!!! Thats just amazing to me. :) But this only occurs if I keep the servo at high BW. When I make it sub sonic the THD at each output goes up an order of magnitude.
I also add the CSS for the current into the thermal compensation Qs.
I agree it is promising, and its been a lot of fun too! :)
Here it is: |
|
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| Russ White |
Simulated THD20 at very sane bias currents:
The first is differential, the second two are each output to GND.
| code: |
Fourier components of V(out+,out-)
DC component:3.40477e-011
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 2.801e+00 1.000e+00 -5.96° 0.00°
2 4.000e+04 8.285e-11 2.958e-11 24.48° 30.44°
3 6.000e+04 1.698e-06 6.061e-07 14.84° 20.80°
4 8.000e+04 7.864e-11 2.808e-11 -22.20° -16.24°
5 1.000e+05 1.345e-08 4.802e-09 -172.09° -166.13°
6 1.200e+05 7.786e-11 2.780e-11 -74.09° -68.13°
7 1.400e+05 6.899e-09 2.463e-09 -16.98° -11.02°
8 1.600e+05 7.738e-11 2.763e-11 -127.03° -121.07°
9 1.800e+05 8.275e-09 2.955e-09 142.91° 148.87°
Total Harmonic Distortion: 0.000061%
Fourier components of V(out-)
DC component:0.000959188
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 1.400e+00 1.000e+00 174.04° 0.00°
2 4.000e+04 4.640e-09 3.313e-09 86.70° -87.34°
3 6.000e+04 8.489e-07 6.061e-07 -165.16° -339.20°
4 8.000e+04 2.047e-09 1.462e-09 118.46° -55.58°
5 1.000e+05 6.722e-09 4.800e-09 7.92° -166.12°
6 1.200e+05 2.007e-09 1.433e-09 -69.91° -243.95°
7 1.400e+05 3.451e-09 2.464e-09 162.99° -11.05°
8 1.600e+05 1.115e-09 7.963e-10 -174.33° -348.37°
9 1.800e+05 4.138e-09 2.955e-09 -37.07° -211.11°
Total Harmonic Distortion: 0.000061%
Fourier components of V(out+)
DC component:0.000959188
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 1.400e+00 1.000e+00 -5.96° 0.00°
2 4.000e+04 4.679e-09 3.341e-09 85.80° 91.76°
3 6.000e+04 8.489e-07 6.061e-07 14.84° 20.80°
4 8.000e+04 1.987e-09 1.419e-09 117.02° 122.98°
5 1.000e+05 6.727e-09 4.804e-09 -172.10° -166.14°
6 1.200e+05 2.085e-09 1.489e-09 -70.07° -64.11°
7 1.400e+05 3.449e-09 2.462e-09 -16.95° -10.99°
8 1.600e+05 1.169e-09 8.348e-10 -171.54° -165.58°
9 1.800e+05 4.137e-09 2.954e-09 142.89° 148.85°
Total Harmonic Distortion: 0.000061%
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| Russ White |
| quote: | Originally posted by matejS
Since Sabre is a voltage out w/ 195ohm output resistance, I say it should be referenced to 0V (you will get a little less than 9mA of bias current). Sabre output is really quite good and can handle output input impedance w/o problems (there is a little THD loss due to internal resistors' temperature coefficient).
But I might be wrong ;)
Cheers,
Matej |
| quote: | Originally posted by analog_sa
It is? |
Matej,
You are quite right actually.
I have been conversing with Dustin about the Sabre output.
The Sabre is indeed truly a voltage output DAC.
For the Buffalo DAC it just happens to work like this:
The output impedance is 50K/64/4 = ~195R. The bias voltage is exactly AVCC/2 and the voltage swing is 0.924 * AVCC.
So it is quite correct to simulate it as a voltage in series with a resistance, and we have the exact value extents to use. :)
Cheers!
Russ |
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| fierce_freak |
Thanks for getting the answer to that mystery out, Russ. I know I'm in over my head, but I kept thinking it had to actually be voltage out.
When you guys get to this circuit, do you plan to release it in your standard form factor or have you decided on possibly using a different one, maybe to fit more parts on? |
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| Russ White |
The whole voltage/current thing gets really murky and grey sometimes.
You can basically argue that any amplifier is a current source, because it has an *some* output impedance. But you can also say any current with a low enough impedance is a voltage....
195R by most standard is smack in the middle. Not low, but not really high either. The thing that settles it for me, is the way in which the current/voltage is generated. :)) OK that's clear as mud...
I think it more critical to look at the performance of the DAC into a given load.
The Sabre likes a low impedance for best results. Into a high impedance the results are still good, but not as good. :)
Yes, I won't argue there may be thermal effects for 0Vbias VS AVCC/2 bias. But I think IVY is a case study which proves its not that big a deal. :) Purely aesthetically, it rocks.
We are talking 256 50K resistors. How much difference does 1.65V make to a 50K resistor?
Cheers!
Russ |
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| Terry Demol |
| quote: | Originally posted by Russ White
The whole voltage/current thing gets really murky and grey sometimes.
We are talking 256 50K resistors. How much difference does 1.65V make to a 50K resistor?
Cheers!
Russ |
The white paper indicates 6 unity weighted bits per OP, each 4k7,
4k7/6 = 783 ohms. Stereo mode = 783 / 4 = 195 ohms.
Same result, different no of bits?
Or is there actually 64 bits per dac phase as you are alluding, that
sounds like a lot of internal R's??
T |
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| Russ White |
| quote: | Originally posted by Terry Demol
Or is there actually 64 bits per dac phase as you are alluding, that
sounds like a lot of internal R's??
T |
It is a lot of Rs. Which would be a good thing I suppose. :)
50K/64/4 is precisely the figure Dustin gave me. So I am taking his word for it. :) |
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| Terry Demol |
| quote: | Originally posted by Russ White
It is a lot of Rs. Which would be a good thing I suppose. :)
50K/64/4 is precisely the figure Dustin gave me. So I am taking his word for it. :) |
Yes, more bits = better resolution, all other things being equal.
I'll check it out on the other thread. In the end, the 195R is the
important value.
T |
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| Russ White |
Undoubtedly, the 195R value is critical, but knowing how you get that value can make a big difference too. :)
Also the number of bits does not have to equal the number of resistors. :) They could be paralleled. |
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