| ratmayor |
Hello! I have nothing to say that my English is not good.
I have some small doubts, always caught my attention Class D amplifiers, however, the few diagrams eh found on the Internet that require the IC IR2110, IR2111, and so are my doubts: Is there any alternative to this IC? Will there be a way to make a more simple design with common components?
I thank in advance all the help I can give |
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| Eva |
| A discrete high side driver would be more complex. IR2xxx actually result in simple drive circuits with very low part count. |
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| lumanauw |
Every major semiconductor has their own high/low side driver. Like UCC27200 from TI.
If you want to skip these driver IC's, make class D with common source Pch/Nch mosfet, you don't need these drivers. |
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| Eva |
There are no high-performance P-channel MOSFET with Vds ratings above 100V, and the ones rated at 100V or less exhibit too high Rds-on and charges/capacitances in comparison with N-channel devices.
You get increased performance and efficiency in return for the complexity of high side drive. |
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| lumanauw |
| I'm blowing high/low mosfet driver like popcorn here. They seems so fragile. What's the secret to work with these IC's during development/experiment stage? |
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| Workhorse |
I have used IR2110 with success, not even a single failure with mosfet upto 230nC of Qg.
For higher voltage and Qg mosfets, TC4420 + 6N137 is very good |
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| Eva |
| quote: | Originally posted by lumanauw
I'm blowing high/low mosfet driver like popcorn here. They seems so fragile. What's the secret to work with these IC's during development/experiment stage? |
Could you show us the PCB layout and the schematic of the circuit that is so prone to blowing IR2xxx? |
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| lumanauw |
| I'm not using IRxxxx, but UCC27200. Here's the PCB layout, I have to draw the schematic later. |
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| Eva |
And where is the ground plane? :confused:
The bootstrap capacitor is by far too small for audio class-D :hot:
The low-side current sense resistor is in the gate drive loop and in the HB/HS clamping loop :hot: :hot: :hot:
You clearly have some good keys for success :D
I place all my gate driver ICs and modulators in daughter boards and I use continous ground planes. I would never sense the current in that way, too. All this is for good reasons...
BTW: My methods may seem crazy, but I've just measured over 94% efficiency on a two-stage 120V 60Hz sinewave inverter at 2000W output. It uses IR2113 and I have not blew a single one during the whole development. |
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| lumanauw |
Hi, EVA,
Why is when I blow the output mosfet, the driver always broken too? In experimental stage, how to preserve the UCC27200 whenever the output mosfet is blown away?
| quote: | | The low-side current sense resistor is in the gate drive loop and in the HB/HS clamping loop |
Do you mean the Vss for the UCC27200 should be taken after the current sensing resistor? |
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| ratmayor |
| hello! ask for the IC and thought that they spoke in Japanese or in another language rare, there is no alternative use common components such as BJT's or CMOS? |
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| Eva |
| quote: | Originally posted by lumanauw
Hi, EVA,
Why is when I blow the output mosfet, the driver always broken too? In experimental stage, how to preserve the UCC27200 whenever the output mosfet is blown away?
Do you mean the Vss for the UCC27200 should be taken after the current sensing resistor? |
The driver is probably blowing up first. Then the MOSFET fail too. You don't need such a fast driver for 300Khz class D, it's completely overkill.
Concerning the Vss connection point, isn't the reply obvious enough? ;) Think abut the disadvantages of connecting it before the resistor (many!) Remember to move the ground of the level shifter too, and you could also move the sense resistors to the output side of the inductor too...
| quote: | Originally posted by ratmayor
hello! ask for the IC and thought that they spoke in Japanese or in another language rare, there is no alternative use common components such as BJT's or CMOS? |
Consider things from a different point of view: You won't be able to produce class D stuff until you understand our dialogs. When you don't understand the circuits in detail, you are likely to blow dozens of ICs and MOSFET without going anywhere. |
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| lumanauw |
Hi, EVA,
Thanks for the tips :D
I'm using floating 12V to make -VCC+12V (supply for gate driver). If the level shifting point, gate driver gnd, all placed after current sensing resistor, then this floating 12V also should be connected after this current sensing resistor too? What happens if this resistor fails?
Current sensing after inductor? Nice idea. Then the feedback point should be moved after this resistor, I think. Needs bidirectional current sensing? |
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| lumanauw |
| This is the schematic that inspires me to take the VSS point before current sensing resistor. |
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| phase_accurate |
But here the current-sensing is done outside the gate-drive current-loop if you have a close look.
Regards
Charles |
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| ChocoHolic |
Hi Lumanau,
parasitic resonances tend to kill the drivers.
You can have killed drivers even with surviving Fets...
Do you have screen shots of your gate signals at hard switching conditions? Please note these resonances are fast (typically 10MHz...100MHz), so you need a fast scope.
Ratmayor,
how about IRS20955.
IR is basically a good adress for high side drivers.
For higher voltages there is something with reasonable accuracy coming from Infineon:
http://www.infineon.com/cms/de/prod...112ab6a547004ac
Hey Workhorse, Fredos,...
where are you? The Infineon driver should match to your normal voltage needs... ;-) |
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| ChocoHolic |
| quote: | Originally posted by Eva
You don't need such a fast driver for 300Khz class D, it's completely overkill.
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I do not fully agree.
As long as one is just struggling to get a D amp running, you are right.
But when you want really low THD, suddenly the ns-precision for gatesbecomes quite helpful. (And of course a reasonable modulator and low THD output filter...)
The UCC27200 seems to be a nice device, except missing shut down functions and quite low voltage ratings. |
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| lumanauw |
Until today I blow almost 20pcs of this UCC27200 and 20FDP3652. I feel tired with this experiment.
They are not blown by themselves, but my mistake. Sometime I touch something, sometime a cable snap, sometime I solder something when there is still voltage in the PCB, sometime the through-hole/track ruined (too many soldering+desoldering), etc. All resulted in blown UCC and FDP. Very fragile for experiment, unlike the discrete design. I'm relaxing for now :D
I agree with Chocoholic. Even if the switching frequency is only 400khz (max), better parts make better audible sound. I try to use TL3116+UCC27200+FDP3652, with very narrow dead time, the sound is very good.
My finding : UCC27200 is very hot. Better use the thermal pad one. Funny, the high-side gate resistor is much hotter than the low side gate resistor (I use 10ohm). Why is this? |
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| phase_accurate |
| quote: | | parasitic resonances tend to kill the drivers |
Yes and there is one more possibility to kill them:
If you feed the drivers with input signals having "dirty transitions" i.e. ones that look similar to contact bouncing.
This signal degradation might not even be visible at the driver's outputs but they will lead to increased losses. I don't know by what degree a 2110 is prone to this (some drivers have protection logic against this) but I once definitely killed some TSC44xx this way.
Regards
Charles |
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| Eva |
If high side gate resistor gets hotter than low side one while the amplifier is idle, there is something really wrong with the circuit. Either:
- High side drive signal is bouncing
- Low side series inductance is much higher
- High side supply voltage is higher
Are you using an UcD style modulator? |
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| lumanauw |
Hi, EVA,
I also think there is something wrong that makes the high-side gate resistor is much hotter than the low side gate resistor.
Since there are some suspects, how to know which one is making this?
I'm using a mix of forced clock and UCD feedback. When clock is removed, auto-oscillating about 350khz, while the clock is 375khz. |
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| lumanauw |
Hi, Charles,
How to cure parasitic resonances? Is it looks like jitter (blurry, multiple shadow trace)? |
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| phase_accurate |
The four most important things to look at are:
1.) Layout
2.) Layout
3.) Layout
4.) Decoupling
Make sure that your layout uses the smallest possible areas within current loops and make sure to have a proper groundplane.
Regards
Charles |
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| Tahmid |
hi,
You could try to use IR2181. |
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| Tahmid |
hi,
Better alternatives for the older IR2010-2113 are the IR2181, IR2184 from International Rectifier.
ST Microelectronics also provides high quality high low side MOSFET driver - L 6384 to L 6388. These internally contain the bootstrap diode. |
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| lumanauw |
Hi, Charles,
Comparing groundplane and layout with care of current loop (like fig7 and fig8 of IR's AN-1135). Which is more important? Can I make good PCB only caring the currentloop, without groundplane? The problem with groundplane is that while the tracks have to be as wide as possible (to make low parasitic inductance), putting groundplane below wide tracks equal to make parasitic capacitance. |
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| Eva |
| Don't worry about a few dozen pf of distributed capacitance in high current paths. |
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| lumanauw |
Hi, EVA,
After reading that appnote, a little question pop up in my mind. Ground plane (-rail plane for a design using high/low driver), besides give parasitic capacitance (can do both positive and negative effect (like parasitic capacitance to inverting input) to a different cct), they also give low inductance+low resistance path for current loop, say for Vgs loop.
Could it be that the positive effect of ground plane is actualy this good loop path itself? For example, many designs make good Vgs drive (track width, track length), but forgetting about the return current (like nF cap from source of the mosfet back to the+ supply of the high/low driver)? This is helped much by groundplane. Ordinary track is inferior to groundplane if we look at this aspect. |
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| Pafi |
| quote: | | Ground plane [...] also give low inductance |
| quote: | | Could it be that the positive effect of ground plane is actualy this good loop path itself? |
(I'm not Eva, but) Yes, most of the times! |
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| phase_accurate |
| quote: | | Could it be that the positive effect of ground plane is actualy this good loop path itself? |
Yes and it is making your reference "rail" the least inductive that is possible.
Regards
Charles |
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| lumanauw |
OK.
I might be wrong here. Anyway, here's an example for this discussion. If we are tracing the Vgs-loop, shouldn't the left side of C9 connected to +9V (instead to gnd), and left side of C8 connected to gnd (instead to +9V) to complete the shortest Vgs loop? And add another 100nF cap from +9V to gnd? |
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| phase_accurate |
Since the gate driver is referenced to ground (and therefore its output voltage as well) also the output device's source should be referenced to ground.
BTW I have a circuit using such a capacitive coupling for the gate-drive signal but with a high impedance DC path in parallel. This one can do 0 to 100% duty cycle.
Regards
Charles |
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| lumanauw |
Hi, Phase_Accurate,
Do you mean C8 and C9 is better the original way than my suggested modification above? |
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| phase_accurate |
Don't know the original. But C9 is correct in your post. C8 I would reference to ground as well but the driver IC should have some decoupling across its supply as well.
Regards
Charles |
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| classdphile |
Hi,
Seeing as it is a level shifting complimentary driver and output stage, it kind of seems like JohnW got the bypassing right, just like it is. He does tend to know what he's doing though.
The Driver P channel is the pos. 9V rail connect to driver source, driving the Vgs of the P chan output, with it's source "referenced" to the High voltage rail. Shortest loop seems to be across the two. It's quite the backwards thing to look at though.
Do also note that the output stage is completely AC coupled to the driver, and as such likely uses bipolar supplies, where its DC references are either rail.
You should link to the thread where you found the circuit so that it can be viewed in its proper context. |
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| ChocoHolic |
Hi Lumanauw,
...I would also guess that there is a fast decoupling cap across the SI1539DL, like Charles is proposing.
You got this schematic from JohnW and did not discuss with him about the layout? He has his own philosophy, which is working pretty good. |
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| Tahmid |
Hi lumanauw,
The circuit you have shown using p-channel and n-channel MOSFETs looks rather complex. Since you are using p-channel MOSFET as high side switch, implementing the simple level shifting method, the circuit can be made much simpler than what you have shown.
The two external driver ICs could be eliminated and an NPN transistor-resistor-zener could be used for level shifting the p-channel MOSFET while the n-channel MOSFET can be driven straight from the PWM chip. If you are using chips like SG3525, gate drive current should not be a problem as the SG3525 (with its internal totem-pole stage) can provide enough current to drive the MOSFET at frequencies greater than 100kHz.
What I have just said can be easily understood if you look at the circuit I have attached here.
To everyone,
I have not used PCB but have tested the circuit on verroboard / stripboard. I have used my circuits successfully upto 132kHz with no problem. The only consideration, as what I see, is that the tracks/ traces should be kept as short as possible. Decoupling capacitors should be placed where necessary and should not be omitted.
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The strongest man in the world is one, who stands alone for achieving something good.
পৃথিবীতে সেই সবচেয়ে শক্তিশালী ব্যক্তি, যে ভাল কিছু অর্জনের জন্য একাই নিরন্তর চেষ্টা চালিয়ে যায়।
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| lumanauw |
This is what I understand from fig.7 of IR's AN-1135
The lower mosfet turn on is the pink loop. The basic thing is that everytime a current is sourced, it must come back, in this case the +/- of the capacitor.
The loop started as charge stored in the +cap (this cap is the one between pin10 and pin12). This charge goes to pin12, then sourced by pin11, goes to lower mosfet's gate.
After going to the gate, this charge has to come back, from gate it goes to lower mosfet's source, flowing in -B rail, and ends at the -cap (the one connects to pin10). This means that cap has to be a fast one (tantalum or ceramic). Many designs put electrolytic//with 100nf. I think the charge of this loop goes mainly through the 100nf, not the electrolytic cap.
This agrees with loop formula, the current goes in and out should be 0.
Usually the analysis stops at the mosfet's gate, and overlooked what happens next. This fig. helps me to understand the loop. The path from mosfet's source until -cap has the same importance as the path from +cap to mosfet's gate, since they carry the same charge. If the later one is bad, the former will be affected with the same degree. |
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| lumanauw |
| In this schematic, the charge starts as +cap of C319, to pin3(Vcc), to pin1 (LO), to mosfet gate (Q309-311), to mosfet source, to R346, ramping through -rail, then go back to -cap of C319. The problem is that C319 is only 1000pf, E309 is not used. This means, the charge has to travel a longer way to the -rail+12V generator (Q303's capacitor) E315 (on the lower left). |
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| lumanauw |
Hi, Tahmid,
That cct is not mine, it is property of JohnW, a member here. He's a good designer, but I haven't seen him post on classD forum lately. |
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| ChocoHolic |
| quote: | Originally posted by Tahmid
Hi lumanauw,
The circuit you have shown using p-channel and n-channel MOSFETs looks rather complex. Since you are using p-channel MOSFET as high side switch, implementing the simple level shifting method, the circuit can be made much simpler than what you have shown.
The two external driver ICs could be eliminated and an NPN transistor-resistor-zener could be used for level shifting the p-channel MOSFET while the n-channel MOSFET can be driven straight from the PWM chip. If you are using chips like SG3525, gate drive current should not be a problem as the SG3525 (with its internal totem-pole stage) can provide enough current to drive the MOSFET at frequencies greater than 100kHz.
What I have just said can be easily understood if you look at the circuit I have attached here.
To everyone,
I have not used PCB but have tested the circuit on verroboard / stripboard. I have used my circuits successfully upto 132kHz with no problem. The only consideration, as what I see, is that the tracks/ traces should be kept as short as possible. Decoupling capacitors should be placed where necessary and should not be omitted.
_____________________________________________________________________________
The strongest man in the world is one, who stands alone for achieving something good.
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...your circuit is introducing several hundret ns turn off delay especially for the upper MosFet... have a close look to your gate signals - you will probably not be amused.
Hi Lumanauw,
I think the loops in the application note are OK.
Also I agree that you need the SMD ceramics for the high frequency path.
Many designs add a large cap in order to ensure acceptable upper gate driver supply during clipping, because during heavy cliping you might not get the upper supply recharged for several 10ms... |
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| lumanauw |
Hi, Choco,
Thanks :D I see now that it is for clipping condition. Still, it has to be accompanied // by 100nF one, right?
Choco, my suggestion in post#31 (modification for the attachment), is it make sense? Or C8-C9 is already correct like the original attachment? |
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| ChocoHolic |
....I think your proposal is optimizing the turn on loop.
John's schematic is looking like he has optimized the turn off loop.
Yupp, the ceramic SMDs should be also used, even if there is a bigger e-cap. |
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