| darkfenriz |
Hi there
That's my early trial to build a decent self-oscillating PWM amp.
I've designed a rather straightforward PCB so far, but I am not an expert in switching applications.
Any feedback welcome!!
Regards
Adam |
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| darkfenriz |
| Top side ground |
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| darkfenriz |
| Is anybody there? |
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| e_fortier |
Hi,
This is not my cup of tea but it looks like you are missing some info like:
Schematics
Silkscreen
Without these how can someone comment of the PCB layout.
Regards,
Eric |
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| Eva |
Someone familiar with self oscillating Class D can actually make some comments ;)
- Connections and RF filtering is missing for incoming supply rails.
- Output inductor and capacitor are missing. The switching node is very prone to dV/dt radiation, don't use long wires. Note that you need a very precise sample of the carrier residual from output capacitor at the input of the comparator, so things such as ground loops or long wires are evil. Output capacitor inductance is evil too, self resonance should ideally happen above 1/( twice-the-propagation-delay).
- The inductance from the big electrolytics and the layout will resonate with the SMD ceramics unless you add some smaller electrolytics, whose ESR makes them act as RC dampers (type of capacitor should be found empirically).
- RC snubbers from D to S for damping resonance due to layout and TO-220 inductance and MOSFET die capacitance are missing.
- The inductance from the PCB track that joins the upper source with the lower drain could be reduced. The more inductance, the "stronger" the RC snubbers required and the more heat they dissipate (heat in optimum RC snubbers is directly related to the amount of energy stored in PCB and component parasitics). |
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| darkfenriz |
Thanks Eva
Great tips from you as usual!
| quote: | | - Connections and RF filtering is missing for incoming supply rails. |
Not sure what you mean by RF filtering, will really need a choke at incoming PSU ?
| quote: | | - Output inductor and capacitor are missing. |
Inductor is a air core toroid, quite bulky single layer one 40uH, 150mR.
I will connect it between two wire screw clamps as marked at the below image.
| quote: | | - The inductance from the big electrolytics and the layout will resonate with the SMD ceramics unless you add some smaller electrolytics, whose ESR makes them act as RC dampers (type of capacitor should be found empirically). |
Yes, well, I will have to experiment a bit. Big electrolytics are planned to be 1500-3300uF high ESR general purpose as an additional filtering. If they make problems I'll throw them away.
| quote: | | - RC snubbers from D to S for damping resonance due to layout and TO-220 inductance and MOSFET die capacitance are missing. |
Good comment, thanks for that. At first I was not so sure if I really need snubbers for D-S. Possibly parasitic capacitance from inductor together with output snubber to speaker ground will do:confused:
Otherwise I'll experiment with snubbers off the main board. All in all that's a prototype.
| quote: | | - The inductance from the PCB track that joins the upper source with the lower drain could be reduced. The more inductance, the "stronger" the RC snubbers required and the more heat they dissipate (heat in optimum RC snubbers is directly related to the amount of energy stored in PCB and component parasitics). |
Corrected that a bit....
Regards
Adam |
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| darkfenriz |
More about the project...
On the main board there is a IR2110 driving mosfets through ferrite bead (25R/25Mhz;50R/100MHz) and PNP transistor.
Also some positive regulators for driver and for dead time generator both referenced to minus supply.
Input comparator module (installed vertically) will be discrete BJT, basically a long tail pair loaded with current mirror (class AB style).
Comparator output referenced to -V (yes, no level shifters!) drives logic symetrizer/dead time generator (schematic below) already tested and works properly.
Third vertically installed module will be "beta", I would like to test pre and post filter feedback and possibly mixed.
I would like to hear some "good luck" from you;)
Regards
Adam |
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| EnvisionAudio |
| quote: | Originally posted by darkfenriz
Hi there
That's my early trial to build a decent self-oscillating PWM amp.
I've designed a rather straightforward PCB so far, but I am not an expert in switching applications.
Any feedback welcome!!
Regards
Adam |
You seem to not be aware of the "polygon" feature of Eagle. Use it to flood the top layer with copper (remember to change the NET name, example N$51 -> GND1).
Then, use TRestrict layer to selectively remove copper. |
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| darkfenriz |
| I've got only top and bottom in "light" edition |
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| EnvisionAudio |
| quote: | Originally posted by darkfenriz
I've got only top and bottom in "light" edition |
Unless they changed something...you have TRestrict in Light (layer 41). The polygon feature is there, too. Light only restricts you to two signal layers - you can have as many mechanical layers as you want! |
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| DJ Exprice |
May we see the EAGLE files please?
Having the EAGLE files will allow us to have a better understanding of the layout.
Thanks,
vb |
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| darkfenriz |
| Started experimenting a little bit... |
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| darkfenriz |
Waveforms after dead time generator (ir2110 inputs) driven by low level sine. Dead time set to maximum, around 120ns.
Little overshooting and jittery, but still with nice slopes, so I don't think it is much a problem.
Regards
Adam |
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| Eva |
| Remember that a good old 100Mhz CRT analog oscilloscope will tell you more truth about class D switching waveforms... |
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| zilog |
| quote: | Originally posted by Eva
Remember that a good old 100Mhz CRT analog oscilloscope will tell you more truth about class D switching waveforms... |
I have thought about upgrading myself to some kind of DSO, what are the pros and cons when it comes to class d and smps? |
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| Pafi |
darkfenriz!
It's not about PCB, but why do you use 2 RC delay network and 2 potentiometers? |
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| darkfenriz |
I was not sure about symmetry of the dead time, so I can adjust it separately for high side and low side dead time.
Probably I was over-worried about that, one RC should be OK.
Regards
Adam
P.S. another issue is I had six inverters in one package, so why not? |
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| TheMG |
| quote: | Originally posted by zilog
I have thought about upgrading myself to some kind of DSO, what are the pros and cons when it comes to class d and smps? |
Sometimes it can be easier to see issues such as overshoot on an analog scope. Nearly all DSOs employ some form of averaging, which can make overshoot appear non-existent. On many DSOs you can turn averaging off but sometimes that isn't quite enough due to the sample rate and other factor.
High quality (expensive) DSOs will be better at capturing this kind of stuff, but the less expensive kind might not be able to. |
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| gearheadgene |
why not use infinite persistence on DSO? That should capture overshoot. Some color scopes will change the colors as the number of 'hits' in a certain area occur. That gives you some statistical feel for where the overshoot occurs most of the time.
There was just an article in EDN (tales from the cube) where they debugged using analog scope, waited until it was dark out, turned off the lights, cranked up the scope intensity, and kept watching the trace looking for failures. Fun, eh? |
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| darkfenriz |
OK, I am back to experimenting.
I fed the dead time/IR2110/switching mosfets stage from a generator.
The problem is get very high switching losses, current consumption at 200kHz no load is around 130mA. Overshooting is low, around 5%.
Please help me and tell me what is the problem:
- dead time is around 120ns, should I increase it?
-MOSFETS are cheap and dirty STP22NE10L, not that bad in term of Qrr and Qgd, but the bad thing is low Vgs-th. Are they really not suitable for class D amp?
- I have no mosfet snubbers, could a RC from drain to source help? If so what should be the starting RC values?
Best regards
Adam |
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| darkfenriz |
After yet another "dead time" in my experimenting with this amp I went back.
I've noticed a strange thing, probably I've killed something:
The signal on the output is (more or less) typical switching waveform, but after around 30 seconds or so current consumption starts to rise quickly and finaly the bootstrap- charging diode 1n4007 at IR2110 smokes.
Experts, please give me a tip on what could be dead: capacitor (tried 220uF, 47uF, same results), upper side mosfet, driver, ...?
Thanks in advance!
Adam |
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| darkfenriz |
continued.
I swapped ferrite beads at gates with 18R, now MOSFETs cross-conduct like silly, idle consumption around 250mA or so, rising with time. Are logic-level MOSFETs reall so damn unsuitable for class-D half bridge? |
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| Eva |
I have never worked with logic level MOSFET but they are likely to require some negative bias at turn off (ferrite bead on gate and slight resonance) and some delay at turn on. A low gate supply voltage like 10V should work better as it results in faster turn-off. Gate resistors result on poor switching performance, adding an inductive component results in a 2nd order system with more square-wave like gate waveforms. Then series resistance can provide the right amount of damping.
You have to ensure that proper switching timing is always taking place, not only when the amplifier is idle but at all duty cycles and particularly near the rails, where pulses become narrower, noise margin smaller and comparator bouncing may arise resulting in unexpected disasters. You may find useful to get the trigger signal to the oscilloscope from the output of the comparator (if it isn't too weak). |
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| lumanauw |
Hi, Darkfenriz,
I found the datasheet of UCC27200 and MP7720 has some important points for PCB layout. Like page 22 from UCC27200 datasheet.
The tracks from driver IC to mosfet gate and it's return path (mosfet source) to the IC should be short and wide (>1.5mm if possible). The position of bootstrapp C and supply C should be as close as possible to the IC. Input+feedback components connected to +in and -in of the main comparator should be as close as possible to the pins.
Another good paper is AN1135 from IR.
You use many logic gates in series? I found that to get better sound, the propagation delay (open loop) should be as minimal as possible, mean advoid too many logic gates when possible, cause each gate has quite some delay.
I tried many permutation with 2 side PCB. My conclusion is that a proper PCB layout need at least 4 layer. Cannot do it perfectly with only 2 layer. |
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