| pooge |
As many readers of Doug Self's articles and books are aware, the editing of Self's publications leaves a little to be desired...Ok, it sucks!
I thought I would start a thread as a common base to list these errors for Self and his publishers, in the oft chance that they would actually DO something about them, as many of the errors are carried over from his articles and prior editions.
This may also be a home base for gaining some clarity about some of his topics.
I hope that this can be a constructive dialog for the purposes expressed above, instead of yet another drawn out subjectivist bashing. |
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| pooge |
I noticed inconsistencies between the "Thermal Dynamics in Audio Power" article in 10/96 issue of Electronics World, and the "Audio Power Amplifier Design Handbook", 4th ed.
First, I noticed the same editing errors in each. Table 1 of the article and Table 13.4 of the 4th edition of the book show inconsistent values from the Figures. The values of R1 and R2 appear reversed for the EF, and R3 appears to be reversed between the EF and CFP. I assume the figures are correct.
But what is more important is that in the article, the output of the Vbe in the article is taken at the lower end of R3, as shown in (A) of the attached figure, while in the book, it is taken at the upper end of R3, as shown in (B) of the attachment. I am not sure which one is correct.
I'm guessing that the book is the correct one, because he says that the intent of R3 is to subtract a correction voltage due to current changes.
However, in (C) of the attachment, Self shows a two transistor version of Figure 13.32 of his book, where the Vbe output is again taken at the top of the resistor.
Can anyone shed any light on this issue?
Does anyone have any practical experience with this two transistor circuit regarding oscillation problems or other consequences? Would R3 also be 1k for an EF output stage? |
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| pooge |
Another question I have about Self's book is his two-pole compensation diagram of Figure 7.1d on page 188 of the 4th ed.
It is reproduced in (A) of the attached figure.
He shows one end of Rp attached to the negative rail. He also states "at HF, Cp2 has low impedance and allows Pr to directly load the VAS collector to ground..." on page 193.
Thus, it would appear that Rp should be attached to ground as shown in (B) of the attachment, rather than the voltage rail as shown in (A).
Moreover, one of Self's references to two-pole compensation here shows the resistor connected to ground.
So am I correct that (B) is the correct way to do this?
This would appear to be a good way to extend the open-loop bandwidth. Does anyone have any experience with this as far as stability issues or other disadvantages? It there a way of damping the rise in open-loop at high frequencies? |
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| teemuk |
Pooge,
Regarding your first question (VBE-multipliers), B is the correct configuration. That VBE-multiplier topology has three connection nodes in oppose to two. You can simulate all three configurations (conventional and the ones without extra resistor and transistor) and see how they differ from each other if you feed the collectors with a steadily rising current. The two-transistor version, with the added resistor, stays very linear after a certain point but is in my experience just too unstable. |
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| pooge |
Thanks.
If (B) is correct, and is used in a complimentary VAS, what would be the effect of R4 on the signal? R4 is between the output of the upper VAS and the upper bias voltage. There is no corresponding resistor between the lower bias voltage and the lower VAS output.
Does this matter to the signals, or should another like resistor be placed in the lower half? |
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| teemuk |
No need for another resistor. The whole VBE-multiplier as is can safely be in between the complementary VAS stages - it's the injection points to drivers/output transistors you need to worry about. You want to create a steady bias voltage between the bases of the drivers/output transistors - not in between the VAS stages. The schematic diagrams of Self's book show pretty clearly the take-off points for the bias voltage. I think this is pretty self-explanatory once you think it for a moment.
The effects of using both VBE-multiplier circuit variations are explained quite well in Chapter 12 of Self's Audio Power Amplifier Design Handbook, Third Edition. See "Current compensation", pages 362 - 364. Especially examine the figure 12.33 of the concerned book. Also, you can run the SPICE simulation I mentioned and see the effects yourself. IMO, you can visualize how the circuits work much better if you simulate them. Self's book just tells why they do what they do. |
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| G.Kleinschmidt |
| quote: | Originally posted by pooge
Another question I have about Self's book is his two-pole compensation diagram of Figure 7.1d on page 188 of the 4th ed.
It is reproduced in (A) of the attached figure.
He shows one end of Rp attached to the negative rail. He also states "at HF, Cp2 has low impedance and allows Pr to directly load the VAS collector to ground..." on page 193.
Thus, it would appear that Rp should be attached to ground as shown in (B) of the attachment, rather than the voltage rail as shown in (A).
Moreover, one of Self's references to two-pole compensation here shows the resistor connected to ground.
So am I correct that (B) is the correct way to do this?
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Either way would work. By "ground" he would mean "AC ground". The supply rails are at "AC ground" beacause they are bypassed.
Cheers,
Glen |
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| pooge |
| quote: | Originally posted by G.Kleinschmidt
Either way would work. By "ground" he would mean "AC ground". The supply rails are at "AC ground" beacause they are bypassed.
Cheers,
Glen |
Thanks. I was thinking he should have said signal common when connecting to the rail, since it is a common emitter. But your analysis makes sense. |
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| sam9 |
Regarding the Vbe configurations:
I've used both B and C as opposed to just simulating them with an EF output section. Both function. My instrumentation isn't sufficient (hobby budget) to unambiguously say one or the other results in lower THD or better thermal tracking. C is harder to set but not impossible; you just need patience.
This is not a definitive evaluation but rather a recounting of practical experience of a hobbyist with limit resources. |
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| sam9 |
Regarding two pole compensation:
I believe A is correct. Maybe B will work as well. The affect of A was within my means to detect and it definitely reduces THD at higher frequencies. Choosing the wrong value of Rp can cause some oscillation problems but I found you have quite a bit of latitude which may depend on the rest of the amp. |
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| pooge |
| Thanks. Did you hear a sound difference between the 2-pole and single pole that you could describe? |
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| Bonsai |
Pooge,
I've ended up using the two transistor Vbe multiplier in 'C', but the main pass transistor Q4 is a PNP and not an NPN as shown in your diagram. The R7 load on Q3 is 1k.
I have a 0.1uF connected from the collector to base of the Q3 and a 10uF across the emmiter and base Q4. I have had no instability problems - this Vbe multiplier is very stable and the output resistance is low. This is important in fully symmetrical designs where the VAS current is not neccessarily constant, as opposed to current source loaded VAS topologies.
Its important that the sense transistor is correctly positioned for best thermal compensation. Self seems to make a meal out of the mechanical and thermal coupling of the Vbe multiplier. I used an SMD transistor for Q3 and I've mounted it close to the collector lead of the main output transistor so the response is quick and it s pretty stable (c. 20% total Iq variation from cold to full warm-up after playing loud music). My amp runs with high Iq of 80 - 100mA per pass transistor. |
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| janneman |
| quote: | Originally posted by pooge
I noticed inconsistencies between the "Thermal Dynamics in Audio Power" article in 10/96 issue of Electronics World, and the "Audio Power Amplifier Design Handbook", 4th ed.
First, I noticed the same editing errors in each. Table 1 of the article and Table 13.4 of the 4th edition of the book show inconsistent values from the Figures. The values of R1 and R2 appear reversed for the EF, and R3 appears to be reversed between the EF and CFP. I assume the figures are correct.
But what is more important is that in the article, the output of the Vbe in the article is taken at the lower end of R3, as shown in (A) of the attached figure, while in the book, it is taken at the upper end of R3, as shown in (B) of the attachment. I am not sure which one is correct.
I'm guessing that the book is the correct one, because he says that the intent of R3 is to subtract a correction voltage due to current changes.
However, in (C) of the attachment, Self shows a two transistor version of Figure 13.32 of his book, where the Vbe output is again taken at the top of the resistor.
Can anyone shed any light on this issue?
Does anyone have any practical experience with this two transistor circuit regarding oscillation problems or other consequences? Would R3 also be 1k for an EF output stage? |
| quote: | Originally posted by pooge
Thanks.
If (B) is correct, and is used in a complimentary VAS, what would be the effect of R4 on the signal? R4 is between the output of the upper VAS and the upper bias voltage. There is no corresponding resistor between the lower bias voltage and the lower VAS output.
Does this matter to the signals, or should another like resistor be placed in the lower half? |
You really need to read the text to get the context. R4 is there to modify the temp tracking of the Vbe multiplier. Figs a, b and c are different ways to take care of the temp tracking.
Jan Didden |
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| AndrewT |
| quote: | | This is important in fully symmetrical designs where the VAS current is not neccessarily constant, as opposed to current source loaded VAS topologies. |
The VAS is a single ended ClassA stage. It's current varies with signal.
That is probably why Self went looking for a more constant voltage across the Vbe multiplier.
The multiplier is supposed to be a constant DC voltage. It is very easily tested to prove variation in output voltage with current. A little more work and temp compensation can also be measured.
The bypass cap very effectively takes the multiplier out of circuit with respect to AC signals provided the cap is large enough to cope with low frequencies. |
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| Bonsai |
Andrew,
in a constanstant current loaded VAS, the current should not vary (discounting the small bias current flowing out to the output stage) - it should be stable.
Cap is important to take VAS voltage out of circuit for AC signals as you state, but at low frequencies you require a big enough value to do the job. |
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| AndrewT |
Hi,
the VAS does vary it's pass current. That's the way it achieves the voltage swing on the load. The load can be a resistor, or CCS (bootstrapped or active) or another complementary VAS transistor.
Take the simple case:- VAS feeding a resistor.
At quiescent the VAS feeds just enough current to bring the resistor voltage up to the DC output level required.
On positive half cycles the LTP (or other front end) increases the VAS Vbe and forces more current to flow to the resistor. The resistor voltage rises above the output level and drives the output stage.
On negative half cycles the LTP reduces the VAS Vbe and the resistor voltage falls etc.
The LTP uses the VAS to vary the current into the VAS load. That variable current allows the load to generate a variable voltage that drives the output.
It's a classic single ended ClassA stage with the usual variable current that varies with the signal voltage.
Replace the resistor with an active load and the same physics applies. |
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| sam9 |
| quote: | | Thanks. Did you hear a sound difference between the 2-pole and single pole that you could describe? |
I cannot say that I could hear a difference with the 2-pole. I didn't try very hard since to do it right one would need two nearly identical amplifiers and an A/B switch box. I don't have time or patience for that. The measurements (RMAA) I made were with the same unit and I compared the screen captures.
I suspect what you could hear would depend one you sensitivity to upper mid-range and higher distortion. This varies by person of course. |
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| Bonsai |
Andrew,
ignoring the bias currents that flow into the output stage, the VAS current cannot vary if it is fed with a constant current source. The output voltage changes because the gm changes in the VAS amplifier transistor as the input signal changes. It has nothing to do with the current changing in the VAS - it cannot change - its fixed by the current source load.
In a symmetrical design, the VAS current can vary since it is not set with a constant current source (there are ways of minimizing this by sizing the transistors correctly around the VAS). This is what I was refering to when I discussed the use of the 2 transistor VAS. Also, at high frequencies, bipolar output stages can suffer from cross conduction. A two transistor VAS helps to minimize the effects of this. |
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| AndrewT |
| quote: | | ignoring the bias currents that flow into the output stage, |
Hi,
I don't believe it is reasonable to ignore the load.
If there was no load there would be no point in assembling the circuit.
In push pull topology there are effectively three loads on the VAS:-
1.) the tail current into CCS or another VAS, or a resistor.
2.) the upper half of the output stage.
3.) the lower half of the output stage.
I agree that the CCS if working well has a very high impedance to AC signals. That leaves loads 2. & 3. as the dominant loads.
I can never agree to ignore the dominant load in this discussion.
There is a fourth load but it is fairly small, the feedback from the VAS collector to where ever the designer chooses to take it.
If I recall correctly, this "load" is why many criticise the direct connection of output FETs to the VAS. Most designers are agreed that even with a FET output stage that there should be an intervening driver stage. But even this "rule" has an exception or two. |
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| estuart |
| quote: | Originally posted by pooge
Another question I have about Self's book is his two-pole compensation diagram of Figure 7.1d on page 188 of the 4th ed.
It is reproduced in (A) of the attached figure.
He shows one end of Rp attached to the negative rail. He also states "at HF, Cp2 has low impedance and allows Pr to directly load the VAS collector to ground..." on page 193.
Thus, it would appear that Rp should be attached to ground as shown in (B) of the attachment, rather than the voltage rail as shown in (A).
Moreover, one of Self's references to two-pole compensation here shows the resistor connected to ground.
So am I correct that (B) is the correct way to do this?
This would appear to be a good way to extend the open-loop bandwidth. Does anyone have any experience with this as far as stability issues or other disadvantages? It there a way of damping the rise in open-loop at high frequencies? |
Hi Pooge,
Glen is right IF the supply rails are really at "AC ground". In real life they are not. So the preferred way is method B, resulting in a far better PSRR.
Regards, Edmond. |
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| pooge |
| And I assume the quiet signal ground would be preferred to the noisy ground. Could this be why ground is preferrable to the AC ground at the rails? |
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| estuart |
| quote: | Originally posted by pooge
And I assume the quiet signal ground would be preferred to the noisy ground. Could this be why ground is preferrable to the AC ground at the rails? |
:yes::yes:
For more info on this topic see also:
http://www.diyaudio.com/forums/show...5&pagenumber=18
starting at post #450, in particular the controverse between TPC and TMC.
Regards, Edmond. |
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| G.Kleinschmidt |
| quote: | Originally posted by estuart
Hi Pooge,
Glen is right IF the supply rails are really at "AC ground". In real life they are not. So the preferred way is method B, resulting in a far better PSRR.
Regards, Edmond. |
I wouldn't make the blanket statement that they are not at "AC ground". I would say that they are an inferior "AC ground". Although this would depend on the design somewhat.
Also, the base of the VAS transistor is referenced to the supply rail too (you can't avoid that), so I can see some merit in the choice of method A in some situations.
Cheers,
Glen |
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| pooge |
| quote: | Originally posted by G.Kleinschmidt
Also, the base of the VAS transistor is referenced to the supply rail too (you can't avoid that), so I can see some merit in the choice of method A in some situations.
Cheers,
Glen |
I was thinking about that, as a common emitter the output would also be referenced to the same. It would seem that referencing the resistor to the common reference couldn't be a bad thing. So we have a vote for A, a vote for B, and a vote for either. |
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| estuart |
| quote: | Originally posted by G.Kleinschmidt
I wouldn't make the blanket statement that they are not at "AC ground". I would say that they are an inferior "AC ground". Although this would depend on the design somewhat.
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That's exactly what I mean, "an inferior AC ground"
| quote: | Originally posted by G.Kleinschmidt
Also, the base of the VAS transistor is referenced to the supply rail too (you can't avoid that), so I can see some merit in the choice of method A in some situations.
Cheers,
Glen |
Hi Glen,
Indeed, the base of the VAS transistor is referenced to the supply rail. That's bad enough (because of a poor PSRR). But this is no reason to ty Rp also to the same supply rail, that is, an equally bad reference point. Doing things two times wrong doesn't make it better, only worse.
Cheers, Edmond.
PS: My apologies for not looking any further at your 500W amp. All my time is going to design a fully symmetrical amp with NDFL, EC, and a common control loop for stabilizing the VAS currents, something like the schematic I have dumped on the forum a couple of month ago, but that thing is far from optimal, actually wrong. So forget my first attempt (if not already done). It's a joint project with syn08, who is building the amp. Not an easy job, because it is getting an extreme complicated design. |
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| G.Kleinschmidt |
| quote: | Originally posted by estuart
Hi Glen,
Indeed, the base of the VAS transistor is referenced to the supply rail. That's bad enough (because of a poor PSRR). But this is no reason to ty Rp also to the same supply rail, that is, an equally bad reference point. Doing things two times wrong doesn't make it better, only worse.
PS: My apologies for not looking any further at your 500W amp. All my time is going to design a fully symmetrical amp with NDFL, EC, and a common control loop for stabilizing the VAS currents, something like the schematic I have dumped on the forum a couple of month ago, but that thing is far from optimal, actually wrong. So forget my first attempt (if not already done). It's a joint project with syn08, who is building the amp. Not an easy job, because it is getting an extreme complicated design. |
G'day Edmond.
Hmmm...... I can see some potential benefit in having Rp tied to the same reference point as the VAS base. For instance, with the end of Rp tied directly to ground, the AC current induced in Rp due to rail fluctuations will modulate the base current of the VAS just the same.
I haven't looked into it much deeper than this, but I reckon a comparison between the two connection methods would make for a worthwhile investigation in SPICE.
No worries about the 500W amp – it’s since been completely redesigned, with the power output spec raised to 1kW. Some of the schematics are on my webpage under “1000W Class A+ amp”, but a major update is planned very soon (the Class A output stage schematic is obsolete). I’m building this thing ATM, as well as trying to finish off my 12 watter (tone control board, reg. PSU) and another design.
Good luck with your NDFL super amp – sounds good!
Cheers,
Glen |
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| estuart |
| quote: | Originally posted by G.Kleinschmidt
G'day Edmond.
Hmmm...... I can see some potential benefit in having Rp tied to the same reference point as the VAS base. For instance, with the end of Rp tied directly to ground, the AC current induced in Rp due to rail fluctuations will modulate the base current of the VAS just the same.
I haven't looked into it much deeper than this, but I reckon a comparison between the two connection methods would make for a worthwhile investigation in SPICE.
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Hi Glen and Pooge,
You are right and I was 100% wrong. I spiced it a second time and method A is the clear winner. If Cp1 = 330pF, Cp2 = 120pF and Rp = 3k3, method A shows a PSRR of -57dB at 10kHz, while method B shows only -35dB (the same without TPC).
Apparently, I made a really stupid error during the first simulation by exchanging the results, sorry.
| quote: | Originally posted by G.Kleinschmidt
No worries about the 500W amp – it’s since been completely redesigned, with the power output spec raised to 1kW. Some of the schematics are on my webpage under “1000W Class A+ amp”, but a major update is planned very soon (the Class A output stage schematic is obsolete). I’m building this thing ATM, as well as trying to finish off my 12 watter (tone control board, reg. PSU) and another design.
Good luck with your NDFL super amp – sounds good!
Cheers,
Glen |
Thanks, good luck too with your super amp!
Cheers, Edmond. |
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| john_ellis |
Hi all
the bias stabiliser circuit C is best I think.
It should have a PNP in the second stage.
If anyone has Self's book did he point out the most important aspect of (c) which was that the ratio of the multiplication which is set by R9, R8 can be exactly set for the number of Vbe's you have in the driver /output stage (usu. 4). The bias voltage should be set by adjusting the current in Q3 (use adjustable resistor for R7).
I've had very good results with b but the bias transistor has to match the drivers etc. For example BD139 bias, BD139/140 output pair and 2N3055/MJ2955 = good stability; BD139 bias, BD139/140 driver; MJ15003/4 output = not good use circuit C to fix.
cheers
John |
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| john_ellis |
Hi all
I don't think two pole solves the performance problem of an amp.
First point (I've made before) is that the additional loading increases distortion/drive requirements of the VAS. Think Self briefly mentioned this?
It doesn't affect the transient response, so the two-pole might improve the sound for any of you who prefer to listen to continuous sinewaves instead of music...
cheers
John |
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| pooge |
| quote: | Originally posted by john_ellis
Hi all
I don't think two pole solves the performance problem of an amp.
First point (I've made before) is that the additional loading increases distortion/drive requirements of the VAS. Think Self briefly mentioned this?
cheers
John |
Self did mention the disadavantage of loading the VAS, but stated unequivically that there was a significant net gain in distortion reduction. He seemed rather enamered with it, but concerned about the OL FR peak at the pole. It would seem that there would be a way to eliminate this peak with proper component selection, though. I have a paper I'm still studying that seems to show the proper component selection. Further in this or another paper, it shows that the error voltage is always lower for the two-pole. |
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| estuart |
| quote: | Originally posted by john_ellis
Hi all
I don't think two pole solves the performance problem of an amp.
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Hi John,
Care to specify what kind of "performance problem"
| quote: | Originally posted by john_ellis
First point (I've made before) is that the additional loading increases distortion/drive requirements of the VAS.
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Sure. One more reason to use TMC in stead of TPC.
| quote: | Originally posted by john_ellis
It doesn't affect the transient response, so the two-pole might improve the sound for any of you who prefer to listen to continuous sinewaves instead of music...
cheers
John |
I'm sorry to say so, but this doesn't make any sense to me whatsoever.
First, TPC does affect the transient response, see: http://www.diyaudio.com/forums/show...5&pagenumber=19 post #466.
Second, what the heck has the transient response to do with continuous sine waves?
Third, nobody prefers to listen to continuous sine waves, with or without TPC, although they are very useful for (objective!) THD and IMD measurements.
So, what's your point?
Regards, Edmond. |
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| Bonsai |
Andrew,
I think we are talking cross purposes here. I agree, the load does vary with frequency. I am talking about a steady state situation at a single frequency. |
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| john_ellis |
Hi Edmond
"Performance problem" is to do with transient performance!
What I was thinking of when I wrote that was that at very high frequencies, the two capacitors in series appear to be a singleton. This is where the 12 db slope roll-off falls back into the 6 db roll-off, but of course you are right in that there will be a difference in response because the 12 db (two-pole advantage) region is different from the standard singleton.
The 6db point is seen in the very first stages (sub-200 nS) of a response to a transient, in that the delay times are comparable between a singleton and TPC.
But the "performance problem" arises if, say, the VAS stage cuts off in the transient response because it is being driven harder i.e. faster.
You can see the effects of this "hard" slew rate induced cut-off if you hit a TPC amplifier with a fast transient and compare it with an identical amp where the roll-off is a singleton. In the circuits I have simulated, the loading of the VAS occurs in the fast response period even for an amplifier which has had input degeneration designed so that the input stages don't cut off under normal use.
Here's my illustration:
standard amp: input resistors 330 ohm, current 3 mA each side
compensation capacitor 47 pF. VAS current 12 mA.
TPC: 150 pF on VAS, shunted with 470 ohm (puts the 12dB to 6 dB join at around 3 MHz) and 68 pF to base, the 470 ohm is a pretty heavy load. Needs VAS current to be around 20-25 mA to prevent cut-off. But you can make a critically-damped TPC amp work under these conditions. To damp the response peak I used a 4.7 k in series with 30 pF across the 10k feedback resistor. The 30 pF is critical to obtain accurate damping, (at least in simulation, probably means this in practice too, but at least you can use two 15 pF's) but maybe this is cheating to "tailor" the response to solve a problem arising from internal phase shifts.
Yes the slew rate is faster, but the performance problem isn't just slew rate.
But I hope you can see my concerns with VAS's running around 6 mA, and just "bunging in" a TPC.
cheers
John |
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| john_ellis |
Hi Edmond
And another (very subtle) point...
that TPC design I mentioned has an extremely advantageous (IMHO) design advantage over the Miller ... the differential input stage signals remain completely flat to over the audio band at 20 kHz.
Now if single-polers can give rise to audible effects (if?) because the differential signal increases at around 1 kHz or lower (depends on open loop gain, transition frequency etc) then this particular TPC MIGHT be free from the effects ...
(ifs and mights don't prove anything but the simulation shows no differential quirks until > 20 kHz. That at least has to be worth something.)
might be worth repeating this recipe for a TPC amp:
the only mods from the standard Miller are:
input degen to avoid transient cut off in the input stage
330 ohms, 3 mA/side
68 pF, 150 pF TPC with 470 ohm to ground
VAS current raised to 20 mA (think this is enough for 50W amp).
cheers
John |
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| john_ellis |
oops ...
and the damper components across the feedback.
Simulation says 30 pF (exactly) + 4.7 k
Bet real life is different, but maybe whether the characteristics are flat or not at ~600 kHz might not be too much of an issue.
cheers
John |
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