This thread is intended for discussions about the new D-Clock.
If you have any questions ... please bring'em on 🙂
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If you have any questions ... please bring'em on 🙂

Read More ....
Lars Clausen said:This thread is intended for discussions about the new D-Clock.
If you have any questions ... please bring'em on 🙂
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Read More ....
I like the transformer isolated OP and integrated reg, very good
idea. This should provide much more consistent results across a
wider range of retrofit situations.
Question WRT transformer OP, since it swings +- about gnd
terminal do you need a 1/2 supply reference on other side of
coupling cap?
Is transformer part of filter circuit?
What type of oscillator is it?
Do you have phase noise graph. Plenty of commercial clocks
acheive 1.5ps, but i think low phase noise close to carrier freq is
important and difficult to get.
Cheers
Terry
As a user of LC Audio XO3, I am very insteresting in D-clock.
Since the spec both look the same from web(exclude the price...😀 ), I wonder if D-clock can beat XO3 a lot or.....
Since the spec both look the same from web(exclude the price...😀 ), I wonder if D-clock can beat XO3 a lot or.....

Terry: Thanks for your questions ....
Your CD circuit already has the 1/2 VCC circuit, so no need to worry about that.
The transformer is not part of a filter circuit, it transmits fully to the other side.
It's a Collpitts oscillator.
At this point i don't have noise graphs, so the jitter level is only calculated from the potential noise sources in the signal chain.
However much of the benefit of a clock comes from the fact that it is totally decoupled from the signal modulated noise of the CD player. The question however is always, how good is it decoupled?
Best regards
Lars C
Your CD circuit already has the 1/2 VCC circuit, so no need to worry about that.
The transformer is not part of a filter circuit, it transmits fully to the other side.
It's a Collpitts oscillator.
At this point i don't have noise graphs, so the jitter level is only calculated from the potential noise sources in the signal chain.
However much of the benefit of a clock comes from the fact that it is totally decoupled from the signal modulated noise of the CD player. The question however is always, how good is it decoupled?
Best regards
Lars C
Lars Clausen said:Terry: Thanks for your questions ....
Your CD circuit already has the 1/2 VCC circuit, so no need to worry about that.
The transformer is not part of a filter circuit, it transmits fully to the other side.
It's a Collpitts oscillator.
At this point i don't have noise graphs, so the jitter level is only calculated from the potential noise sources in the signal chain.
However much of the benefit of a clock comes from the fact that it is totally decoupled from the signal modulated noise of the CD player. The question however is always, how good is it decoupled?
Best regards
Lars C
Lars,
Thanks for answers.
Yes, I did assume you had very high PS rejection from CD supply.
Cheers
Terry
Lars Clausen said:1 Hz from 9 to 24V that comes to some 0,003 ppm/V of PSR.
Lars,
I have heard from a friend, Joe Rasmussen, that even way below
1Hz is a benefit. I usually go a factor of 10 (0.1Hz) just to be
safe but I can't say for sure it is a definitive improvement (as Joe
did).
I am using shunt regs on XO currently but have found the actual
XO topology more important than the PS.
0.003ppm = 170dB PSRR. That is a whole lot - do you care to
disclose anything about the PS?
Thanks,
Terry
Terry: Of course 🙂
It consist first of a dual HF filter with Q damped chokes. They work from 2 MHz up. Then there is the holding caps, and in the beginning of the regulator a two stage pre regulator for ripple removal.
After that a constant current source and a LM329DZ low noise reference. I found that one to be the lowest noise of any reference on the market. This way it doesn't have to be post filtered very much.
Later the 3V / 5V regulators, and post filtering with OSCON's.
I hope this description is fulfilling.
Best regards
Lars Clausen
It consist first of a dual HF filter with Q damped chokes. They work from 2 MHz up. Then there is the holding caps, and in the beginning of the regulator a two stage pre regulator for ripple removal.
After that a constant current source and a LM329DZ low noise reference. I found that one to be the lowest noise of any reference on the market. This way it doesn't have to be post filtered very much.
Later the 3V / 5V regulators, and post filtering with OSCON's.
I hope this description is fulfilling.
Best regards
Lars Clausen
Terry Demol said:
Lars,
I have heard from a friend, Joe Rasmussen, that even way below
1Hz is a benefit. I usually go a factor of 10 (0.1Hz) just to be
safe but I can't say for sure it is a definitive improvement (as Joe
did).
I am using shunt regs on XO currently but have found the actual
XO topology more important than the PS.
0.003ppm = 170dB PSRR. That is a whole lot - do you care to
disclose anything about the PS?
Thanks,
Terry
170dB is the "0 Hz" rejection, at higher frequencies 170 dB is something to dream about only 🙂
Lars Clausen said:At this point i don't have noise graphs, so the jitter level is only calculated from the potential noise sources in the signal chain.Best regards
Lars C [/B]
Hi Lars
What is the low frequency corner you included in your calculations ?
best
Guido Tent said:
170dB is the "0 Hz" rejection, at higher frequencies 170 dB is something to dream about only 🙂
Hi Guido
Thank You for your questions, and comments.
Very true, you can't filter out low frequency noise very effectively, however you can filter out HF noise. A double HF filter with low-Q inductors as used in the D-Clock does help quite a lot. And the GND loop isolator effectively prevents any GND carried noise to play a part.
About low frequency corner, i consider the LM329DZ to be the main contributor of low frequency noise. From the datasheet found
Here
it can be seen that the low frequency corner in the nV/sr(Hz) corner is something like 12Hz. When compared to the industry standard TL431A reference, the LM329 has almost 5 times lower noise figure, and compared with most voltage regulators, about 70-100 times lower noise.
Of course you can filter out much of the Zener noise using huge capacitor banks, but i think there are other factors speaking against that. One is that you never get a straight frequency/ noise reading, and thus the sound will be affected.
All the best from
Lars
Lars Clausen said:
Hi Guido
Thank You for your questions, and comments.
Very true, you can't filter out low frequency noise very effectively, however you can filter out HF noise. A double HF filter with low-Q inductors as used in the D-Clock does help quite a lot. And the GND loop isolator effectively prevents any GND carried noise to play a part.
About low frequency corner, i consider the LM329DZ to be the main contributor of low frequency noise. From the datasheet found
Here
it can be seen that the low frequency corner in the nV/sr(Hz) corner is something like 12Hz. When compared to the industry standard TL431A reference, the LM329 has almost 5 times lower noise figure, and compared with most voltage regulators, about 70-100 times lower noise.
Of course you can filter out much of the Zener noise using huge capacitor banks, but i think there are other factors speaking against that. One is that you never get a straight frequency/ noise reading, and thus the sound will be affected.
All the best from
Lars
Hello Lars,
Thanks for feedback. The 329 is about 75 nV/SqrrtHz, that is about 11 nV/SqrrtHz/V
The "ordinary" LM7805 is something between 120 to 200nV/SqrrtHz, that is 24 to 40nV/SqrrtHz/V, which is a bit different from 70 to 100 times lower.
I agree on the filtering, I don't like that either.
Still curious how you calculate the jitter..........
best
Hi Guido: You are right, i checked up on the 7808, and it has typ 52 uV rms noise, while the LM329DZ has 7 uV rms. So it's only 7-8 times worse.
If we are talking LM317 (see Datasheet) it has like 150 uV rms at 5V, so that's 21 times higher than LM329DZ. But ok you are right 70-100 times was a little exaggerated, sorry.
I calculate jitter by adding the noise sources together, and finding the signal to noise ratio.
Then i transform it into S/N in the time domain, by dividing the full transition time at 16.9 MHz (30nS) with the S/N ratio.
So in this case the 7uV rms will contribute with:
(Only half of the 7uV is transferred as comparator input equivalent noise).
(500 mV rms is the input voltage for the comparator).
3,5uV/500mV = 0,00007
Jitter contribution: 30 nS * 0,00007 = 0,00021 nS or 0,21 pS.
I hope this answers your question.
Best regards
Lars
If we are talking LM317 (see Datasheet) it has like 150 uV rms at 5V, so that's 21 times higher than LM329DZ. But ok you are right 70-100 times was a little exaggerated, sorry.
I calculate jitter by adding the noise sources together, and finding the signal to noise ratio.
Then i transform it into S/N in the time domain, by dividing the full transition time at 16.9 MHz (30nS) with the S/N ratio.
So in this case the 7uV rms will contribute with:
(Only half of the 7uV is transferred as comparator input equivalent noise).
(500 mV rms is the input voltage for the comparator).
3,5uV/500mV = 0,00007
Jitter contribution: 30 nS * 0,00007 = 0,00021 nS or 0,21 pS.
I hope this answers your question.
Best regards
Lars
Lars Clausen said:Hi Guido: You are right, i checked up on the 7808, and it has typ 52 uV rms noise, while the LM329DZ has 7 uV rms. So it's only 7-8 times worse.
If we are talking LM317 (see Datasheet) it has like 150 uV rms at 5V, so that's 21 times higher than LM329DZ. But ok you are right 70-100 times was a little exaggerated, sorry.
I calculate jitter by adding the noise sources together, and finding the signal to noise ratio.
Then i transform it into S/N in the time domain, by dividing the full transition time at 16.9 MHz (30nS) with the S/N ratio.
So in this case the 7uV rms will contribute with:
(Only half of the 7uV is transferred as comparator input equivalent noise).
(500 mV rms is the input voltage for the comparator).
3,5uV/500mV = 0,00007
Jitter contribution: 30 nS * 0,00007 = 0,00021 nS or 0,21 pS.
I hope this answers your question.
Best regards
Lars
Hi Lars,
OK, we agree on the noise of regulators, and indeed, stay away from 317 or 431 based regs.
I am afraid you are a bit too optmistic in calculating the jitter figure, there are more noise source than only the power supply........
best
Guido: Indeed you are right, that is why i wrote 'Jitter contribution:' for the regulator noise figure.
But thanks for staying alert on this warm summer day 😉
Most clocks will perform quite nicely in a laboratory environment, and have many times lower jitter than the built-in clock of the CD player. Even using standard power supply regulators.
But when you mount it in a CD player, the jitter performance is destroyed by GND loop noise. You take the power source from the CD player one place, and connect the GND another place. Most probably in the most jitter sensitive spot of the CD player.
So all the current you draw and also the HF noise you connect from the PSU takeoff point to the GND insertion point, is added to the jitter of the system. Probably many times bigger than what even the noisiest power regulator will contribute with. If you use GND connection for both power supplly and clock signal injection, it makes matters even worse.
That is why battery operation or external power supply will always have such a positive effect on a clock's performance. So now there is a new and even better way of solving that problem, namely GND loop isolation. One of the main leaps forward in the design of D-Clock.
It removes GND loop noise, and it has another positive side effect, now you can HF filter both the positive and GND supply rails, which would otherwise be impossible.
Try it, i think you will find it has a tremendous effect on cleaning up the sound.
All the best
But thanks for staying alert on this warm summer day 😉
Most clocks will perform quite nicely in a laboratory environment, and have many times lower jitter than the built-in clock of the CD player. Even using standard power supply regulators.
But when you mount it in a CD player, the jitter performance is destroyed by GND loop noise. You take the power source from the CD player one place, and connect the GND another place. Most probably in the most jitter sensitive spot of the CD player.
So all the current you draw and also the HF noise you connect from the PSU takeoff point to the GND insertion point, is added to the jitter of the system. Probably many times bigger than what even the noisiest power regulator will contribute with. If you use GND connection for both power supplly and clock signal injection, it makes matters even worse.
That is why battery operation or external power supply will always have such a positive effect on a clock's performance. So now there is a new and even better way of solving that problem, namely GND loop isolation. One of the main leaps forward in the design of D-Clock.
It removes GND loop noise, and it has another positive side effect, now you can HF filter both the positive and GND supply rails, which would otherwise be impossible.
Try it, i think you will find it has a tremendous effect on cleaning up the sound.
All the best
Lars Clausen said:Guido: Indeed you are right, that is why i wrote 'Jitter contribution:' for the regulator noise figure.
But thanks for staying alert on this warm summer day 😉
It removes GND loop noise, and it has another positive side effect, now you can HF filter both the positive and GND supply rails, which would otherwise be impossible.
Try it, i think you will find it has a tremendous effect on cleaning up the sound.
All the best
Hi Lars,
There's airco in Tents's lab 🙂
I know about the groundloop, reason why I advise to only connect the + of the supply. My regs have quite a high input impedance.
Nevertheless I'll give it a try.
On the jitter spec: You claim 1.5ps at your website - which low frequency corner is used there ?
cheers
PHEONIX said:Hello Guido
What do you mean by "There's airco in Tents's lab 🙂"
Regards
Arthur Rappos
Hi Arthur
Airconditioning, we use many abreviations here, lots of technical ones stem from Philips
variac
elco
varicap
cheers
I'll be making an integrated CDP soon, with two DAC chips in dual mono and most likely a CD-Pro2 transport (tips on cheaper transports at a decent quality are welcome). I've been adviced to put a multi-output clock buffer as close to the D-Clock as possible and run separate wires to the transport and each of the DACs, but how will that work with the GND loop isolation? I'll have a separate power supply for the D-Clock, and the buffer chip would most likely take its power from the clock's 3.3V regulator.
What type of output does the D-Clock have? Is it 50 Ohm or TTL? That might be a totally wrong question, as I have no idea what I'm talking about, but you probably do 😉
What type of output does the D-Clock have? Is it 50 Ohm or TTL? That might be a totally wrong question, as I have no idea what I'm talking about, but you probably do 😉
Hi there, this is a question for Lars Clausen. I recently acquired your clock as an upgrade to the a3.24 musical fidelity upsampling dac. I followed the instructions replacing the dip8 oscillator with the output from the d-clock, as explained on your web page, but it is just not working. I checked the output of the d-clock with a scope and it looks ok. As the original oscillator was driving two chips, could it be that the d-clock output is too low in that case ? Also, how crucial is the lenght of the connecting cable (i did not cut mine and left it full length) ? Do you have other suggestions as to what might be wrong ? The a3.24 dac schematics is provided by georgehifi under another thread.Thank you in advance for any help!
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