modify D1 stage for 0.1mA DAC?

Hi freaks,

One special question, maybe you have an idea or even a solution!

I want to take advantage of the genius simple output stage principle of the Pass D1 DAC. It needs two parallel working DAC-IC´s, one inverted, with 2mA current output to be capable to do so. Just one DAC would also work - but no benefit of real symmetrical signal usage. The D1 circuit is biased to 10mA using the IRF610. So far easy, but…

My Consumer DAC uses the 1bit-DAC TDA1547 http://www.semiconductors.philips.com/acrobat/datasheets/TDA1547_CNV_2.pdf . It has symmetrical voltage outputs – so no way for D1 stage. BUT (for feedback function of the internal OPA output stage) the symmetrical internal current source outputs of the switched cap network are also connected to pins. Lucky, not at all – 1V created on 13kOhm load equals just 0,07mA available output current! And the datasheet leaves unclear how an internal circuit of the current output could look like and if it would disturb.

So the first question: do you think this pins of the V-DAC could be used as current output like on "real" I-DACs?

The consequence would be to adapt Nelson´s D1 output stage to a current of just 0,1mA signal. As far as I understand this is possible by "just" changing the bias to e.g. 1mA – so increase upper R 1.5k to 15k and lower R 3.3k to 33k? So 0.07mA would cause 1V output voltage, enough for one branch. So coming to the second question: is this idea right and which FET would be appropriate and good sounding biased at just 1mA?

If all my explanations are bull sh*t and I have just shown not to be an electronics designer, do you know any really good symmetrical output stage for the V-outputs? Actually I us an OPA637 (with tricky RC-protection circuit not to oscillate) as I/U converter. Behind this just a passive RC filter with f_o~55kHz. Sounds almost perfect – but the inner silence of music achievable just by symmetrical signal transport is not given. A noisy floor disturbs a bit the joy of music, if you know, what I mean. Also even the OPA637 leaves a rest of OP sound, but small compared to standard OPA´s.

Tweaky regards and thanks for your hints!

Klaus

tiroth said:

Klaus,

I don't know if this will work with your DAC, but I have done some playing with the D1 stage. The bias current is not really related to the I/V functioning of the circuit, although it certainly must be high enough not to "clip" at full signal. You set the load resistor based upon how much voltage you want out for a given current. Unfortunately changing the load resistors can mean a lot of playing around with values, so you may consider CCS on these FETs...it makes the circuit a lot easier to play with. More linear too, although I know this may not be considered ideal by its designers.

Alternatively, you could always just use the BLS diff pair for voltage buffering/gain. Even if your plan works it may not sound great since the DAC IC was not designed for it. In fact I would suggest you use a simple opamp I/V stage to evaluate whether it is worth going to a more complex circuit...at least that way you won't doubt the I/V if something isn't working.

Good luck.

Click to expand...

Thanks for your answer. Seems that no one has a clear opinion about that. Hopefully more feedback will come reflecting possible failures in thoughts…

I agree on your explanations. The D1-value of the 1,5k resistor was set by the aim to get 3V signal peak at 2mA current peak from the DAC. Then the supply voltage was set "high enough" to get a bias current "with safety" = 10mA and the required drain voltage = 17V offset for the output buffer FET. With my available TDA1547 current of just 0,07mA the 1mA of bias would principally give almost the equal situation with 15k resistor. I see no playing around – as far as I understand the circuit , after adjusting the current sink resistor (= 3.3k to -30V in D1) to 33k for 33V, the balance should by given again for 1mA. Am I right, CCS means capacity values of the FET? Of cause a very low capacity FET should be used. Do you know any proposal for an appropriate FET which works at 1mA in a point of "good sound" performance? Thanks for advice, guys! It will take just some minutes to test the circuit, so I will do.

Alternatives are difficulty – one OPA will stay, however. I will first test how the DAC internal symmetrical I/U OPAs sound driving via 100Ohm output R the cable load directly to Aleph P. Maybe they do not really need the output buffer of a second, external OPA. Or, as you proposed, external BLS could replace this external OPAs – but the sound of the internal I/U OPA is still in…

Regards

Klaus

amendment CCS

Now I found what CCS means...

Of cause, if a solution would be found for my DAC and sonically wise testet positive I would go to improove the performance by CCS. Thanks for the hint!

tschrama said:

Hi KLaus,
Your idea to modify the D1 IV-stage for 0.1mA seems OK to me. Increase the upper resistor that actually converts I to V to get some voltage out, and adjust the lower bias resistor accordingly.

I don't know if a JFET is the optimal choise here, a BJT could maybe result in a lower input impedance. Further more, you could use Jocko's simple IVstage design so that you would need such high supply voltages.

Regards,
Thijs

Click to expand...

Hi Thijs,

thanks for feedback!

I anyhow need a new PSU for this output stage, the consumer DAC has just 12V available. So the high voltage of D1 design is no problem - it even gives a good feeling to have reserve...

For the output buffer stage I will go with IRF610 biased @ 10mA - to have almost everywere in my Pass chain the same sound. For the converter stage you are right, a BJT could offer benefit. I will check out.

I think first I will start with a 2SK389 test @ 1mA bias. CCS will be applied. Let´s tweak!

Regards

Klaus

Hi William,

I can not see any problem?! Your device is much better – the designers spend two DAC chips to improve performance. I guess they use on one DAC just the right and on the other just the left channel. Or they paralleled somehow the two channel outputs of one DAC. By checking the layout or schematics if given you will find it out easily.

Then you do the same like I did: connect the D1 clone stage current input and ground to the appropriate pin of the DAC (by this open the external 13k I/U resistor). Two times for two channels = four D1 stages. Any supply etc. does totally not matter – the current flows out of the DAC pin and back to its ground.

You will be surprised about the sound this simple TDA1547 is performing! But you have to tweak the caps for U_ref and U_analog. Best elko (Pana FC), BG NX0,1uF bypass and Vishay MKP1837 do best job at my DAC.

Regards

Klaus

wuffwaff said:

Hi Klaus,

they use one DAC per channel together with on double opamp to change the 4 output signals (double symmetrical) to a normal symmetrical output and after that follow two further opamps for further filtering and finally a single ended output comes out.

I know that I can use 4 D1 stages but what should I do with two symmetrical outputs per channel? Not much I´m affraid.

Adding the current outputs of the DAC would be a possibility (for a total 1.4mA) but I don´t know if this can be done without damaging or changing the DAC or output signal.


william

Click to expand...

Hi Wlliam,

I totally agree. We do not know how the TDA1547 would react by adding the current outputs. I guess it will work with benefit and destroy nothing like at 1541 towers, but who guarantees…

I see no disadvantage. I guess your original device uses the summing OPAs just to offer also unsymmetrical outputs which are given by symmetrical DAC outputs to cancel DAC symmetry failures. If you use a full symmetrical chain this first step is no longer required, the D1 stage kills this failures.

Were do you find your total of 1,4mA? I guess the DAC gives 1V into 13k = 0,075mA per output, not 0,7mA!?

Regards

Klaus

wuffwaff said:

Arne,

I will go balanced but this DAC gives four current outputs PER CHANNEL!

Klaus,

just a sliding decimal point (2x0,07 = 0,14 not 1,4)

The disadvantage is that the original design uses two summing opamps per channel to perform the transformation double balanced to balanced.
I would like to keep the two halves of the DAC but must find a way to get a normal symmetrical current output to feed the D1 output stage. One possibility is to use only one half of the DAC but this would throw away the advantages of using two da convertors per channel.

william

Click to expand...

Hi again,

But what is the real value of this balanced to balanced? That must be asked. Theoretically it´s nice, of course. But for the price of four OPAs. I am quite sure: use two outputs parallel and feed one D1 stage. Its is "just" one time balanced, but enough. I can just tell you, the sound increase from the old solution "DAC internal symmetrical OPAs + OPA637 sum via cinch" to "full symmetrical with D1 clone" is hard to be described in words. Symmetrical transport will benefit, but most increase is coming from the D1-solution. I would not care to much about the lost second time of balancing – you replace it by parallel DACs!

Regards

Klaus