S/PDIF and PLL

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Hello! First, I apologize for spelling, English is not my native.

I wonder how PLL work with S/PDIF signal. What I mean? Assume that we have 44.1kHz sampling, then actual clock frequency is 44.1 x 32 x 2 = 2.82MHz

Yes but the signal is modulated, and those 2.82MHz would be true if the signal contains only "1". The zeros determine the frequency in half, and preamble 1/3 from the clock. I.e. we can assume that we have random content in the signal, so frequency is constantly changing.

So how PLL in the receiver work with this mess?

Regards!
 
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The Digital Input Receiver's PLL locks onto the S/PDIF signal's preamble pattern, which is not data dependent. So, while the biphase-mark encoded data still has to be decoded, the recovered clock is not jittered by it. This idea was patented by Ed Meitner back in the nineties, but that patent has now expired. I recall that Cirrus DIR chips have long utilized the idea.
 
Since the preamble is synchronous with the received sample rate, once the reciever PLL is locked it can easily generate any master clock frequency that's an integer multiple of that sample rate. Common receiver generated master clock ratios are x128, x256, x384 or x512. Fractional N divider ratio PLL's aren't commonly utilized (the Wolfsen WM880x receivers may, I'm uncertain) in audio DAC input receivers unless that reciever employs an NCO based custom PLL.
 
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TNT

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The clock is coded into the signal. From wiki: https://en.wikipedia.org/wiki/S/PDIF:: "S/PDIF is used to transmit digital signals of a number of formats, the most common being the 48 kHz sample rate format (used in DAT) and the 44.1 kHz format, used in CD audio. In order to support both systems, as well as others that might be needed, the format has no defined data rate. Instead, the data is sent using biphase mark code, which has either one or two transitions for every bit, allowing the original word clock to be extracted from the signal itself."

The signal is also coded with a NRZ (none return to zero) scheme making it's DC component being zero. https://en.wikipedia.org/wiki/Differential_Manchester_encoding

It's a bit more to it than one might think. A shame that the interface wasn't made with one physical link carrying data downstream and one for the clock sent the other direction. But hey, its a consumer standard and need to be cheap.

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...The clock is coded into the signal...the data is sent using biphase mark code, which has either one or two transitions for every bit, allowing the original word clock to be extracted from the signal itself."

Unfortunately, that process also generates significant amounts of data dependent jitter of the recovered clock signal. The preamble based method in Meitner's patent solves that problem.

A shame that the interface wasn't made with one physical link carrying data downstream and one for the clock sent the other direction. But hey, its a consumer standard and need to be cheap.

S/PDIF use has evolved to transmit digital audio signals between separated transport and DAC in the home, but it wasn't the originally intended use. I recollect reading that it was originally intended simply as a diagnostic port in integrated CD player manufacturing/repair. As such, jitter on the recovered clock isn't of concern, so long as it isn't so severe as to provoke actual bit errors. I believe it was Arcam who first utilized the port to connect an external DAC, back in the late eighties.
 
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Is it possible to construct preamble detector from logic gates (discrete) ?

I do something similar to oversampling S/PDIF signal and it works on simulator, but create significant jitter, i presume classical PLL topology is better?

Yes, it's possible, but, as I mentioned earlier, I believe most DIR chips utilize the preamble for clock recovery reference, I recall that the Cirrus chips long have. So, no need to custom build this from the gate level.
 
How many logic gates will be needed?

I predict they will use a lot of space, which is contrary to high frequency operation, and a lot of lag in the wires.

No one would build such a thing today with standard logic chips, such as the 74HC family for example. They would build it in an FPGA. As I recall, pre-designed S/PDIF reciever block FPGA intellectual property (IP) modules are available for license. If you are determined to design your own receiver from scratch you are in for a good deal of needless effort I should think. Perhaps, you are simply after the educational experience?
 
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alexandar88 said:
Will be universal or will only work for a strict sample rate.
That depends on how you design it. You are asking us questions like "how many logic gates?" which can only be answered once you have decided exactly what you are going to build and done part of the initial design (e.g. what PLL technique am I going to use? Do I want to cope with different data rates? Which logic family shall I use?).

You need to do a lot of reading on SPDIF format, jitter specification, PLL design, logic design etc. If you knew enough now to do the design you would not need to ask us these questions - in fact you would know more than most of us!
 
This is because I'm still not decided whether to follow the path already established or yet to discover the wheel. In fact, I already have working in the simulator circuit, as I said earlier - oversampling S/PDIF, completely eliminates the need for PLL, and the remainder of the pattern is child's play. But this option has too much jitter in my judgment, so look for ideas and hints on the front part and the use of PLL. If you know of useful links on the subject would be great.
 
We know master clock on the receiver in any cases. Any phase / frequency shift in the input must not disturb the scheme work.

In my scheme the master clock is used to detect preamble. On the other hand, Ken Newton says that master clock are generated from preamble, that is what make me confused. And I was expected to discuss this more in deep - how to detect preamble / sample rate, of the line of using logic gates.
 
...In my scheme the master clock is used to detect preamble...And I was expected to discuss this more in deep - how to detect preamble / sample rate, of the line of using logic gates.

I suggest that you begin by reading Meitner's patent; 'Very Low Jitter Clock Rocovery...', #5,404,362, granted in 1995. The Patent is not a gate-by-gate circuit description, but it should help to orient you. A google search on the subject should turn up additional relevant information.

As for me, I can tell you that I have absolutely no interest in guiding anyone further in this. What you propose to do is not a trivial endeavor. If you are determined to reinvent a wheel invented decades ago it's your prerogative, but I will only give my best wishes for success.
 
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