I have started a project where I am going to build an analog-to-digital converter for my record player and amplifier. The ADC will be based on around Texas Instruments PCM4202 24-bit ADC and DIT4192 or CS8406 digital transmitter. I have made a simplified overview of the ADC and will quite soon start with the design and drawing the schematic.
I will certainly have some questions during the design and layout phase, and I start easy with my first one regarding master/slave operation of DIT4192/CS8406. I will set the PCM4202 in Master Mode and I then assume it is right to set DIT4192/CS8406 in Slave Mode. SYNC and SCLK at the DIT4192/CS8406 will then be inputs and receive clock information from PCM4202. I am right in my assumption? Or should DIT4192/CS8406 be put in Slave Mode only when multiple DIT4192/CS8406 are working in parallel where one of them is the master and the rest are slaves.
I will certainly have some questions during the design and layout phase, and I start easy with my first one regarding master/slave operation of DIT4192/CS8406. I will set the PCM4202 in Master Mode and I then assume it is right to set DIT4192/CS8406 in Slave Mode. SYNC and SCLK at the DIT4192/CS8406 will then be inputs and receive clock information from PCM4202. I am right in my assumption? Or should DIT4192/CS8406 be put in Slave Mode only when multiple DIT4192/CS8406 are working in parallel where one of them is the master and the rest are slaves.
All that really matters is only one device on the I2S link drives the net; otherwise they contend (and probably eventually one device fries). As you're not locked on a SPDIF transmitter it may be worth considering parts, such as the WM8804 and 8805, which include crystal drivers and some MCLK distribution.
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