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mcd99 2nd July 2013 08:33 AM

Creating / Obtaining LTspice PCB Style symbols?
I have conceived an idea (probably not new at all). Would like to create some transistor (TOxxx) style symbols for LTspice. Where these match the real life pin outs of the transistors and have the same outlines as a PCB silkscreen would be.

These symbols would function just the same as a normal transistor LTSpice symbol.

Have had a look around and can't find any and to be honest can't believe that this hasn't been done before. I think it would be good to allow better modelling of a PCB layout before prototype. It would also allow better visualisation between pcb layout and parasitic modelling.

Does anybody know of anything in existence already? Also, is there an idiots guide that anybody knows of for doing this? Can find stuff relating to sub circuits but not to this.

Please remember I'm simple of mind.


Johno 2nd July 2013 09:50 AM

Bad idea. No one else would be able to read your diagrams. After a week away from it, you would not be able to read your own diagrams.

The symbol used to represent a bipolar transistor in a circuit diagram has 2 alternatives, NPN and PNP which are called according to the part number in a 1 to 1 relationship. The circuit diagram is specifically about understanding the electrical characteristics and communicating these precisely in a predictable "language". It does not care (generally) about physical variations.

The pcb on the other hand is about physical variations and one transistor may have many different package outlines (formed leads, straight leads, vertical mount, horizontal mount etc).

Some people do include the name of the package outline and other information on a circuit diagram but they always use the same transistor symbol.

mcd99 2nd July 2013 10:03 AM

This is the process I'm starting at present.

I have an LTspice schematic less the parasistics, I also have a potential PCB layout. Looking for an easy way of representing this in LTspice to allow parasitics to be added in. My thinking was that if I had the different packages for the transistors in a PCB layout form I could copy the layout back from the PCB to LTspice exactly. Then any changes required in LTspice could then be transferred to the PCB layout accurately / exactly.

My first attempt at this ended up as a mass of lines crossing each other and was becoming a confusing mess.

I understand what you are saying about other people not understanding it but I would have the advantage of having the PCB layout.

It would also provide a good double checking process.

Johno 2nd July 2013 10:29 AM

Most people represent parasitic elements in LTSpice as lumped components.

mcd99 2nd July 2013 10:37 AM

As in making sub circuits up?

Johno 2nd July 2013 11:19 AM

No, simple resistor/capacitor/inductor elements. Harder to model electromagnetic coupling. Point to note is that spice modelling is a simplistic partial solution most of the time. All designs should be bread-boarded.

There are also conventions that should be followed in pcb design that minimise parasitic effects. Star grounds, fat traces, appropriate separation, decoupling caps, thermal isolation and the list goes on. Most of this comes with experience, not Spice.

There are some good threads here on pcb layout that you should be reading too.

mcd99 2nd July 2013 11:31 AM

Decoupling caps is one thing that my first attempt at parasistics taught me about. Learnt that the standard values you see like the 100nF films don't necessarily work as you expect and that snubbers are required. Also, that the positioning of the caps is critical. I recall doing the output stage and found that the rails were ringing massively. I know that LTspice is limited but some parsitics is better than none. A simulation with no parasistics with perfect conductors is much further away from reality than one with an attempt at parasistics.

But I know you're right reality trumps simulation everytime and that real life experience is essential. Something I am sadly lacking in.

Have found a few decent threads on PCB layout and have read about loop area / length as well. Electromagnetic coupling... I think I'll discover about that during prototyping.

dchisholm 3rd July 2013 08:40 AM


Originally Posted by mcd99uk (
. . . I know that LTspice is limited but some parsitics is better than none. . . .

The LTSpice "capacitor" and "inductor" components are actually generalized impedances. They include provisions for first-order, linear, parasitic elements such as series inductance, leakage resistance, etc. Look up "capacitor" and "inductor" the LTSpice "Help" file. (Note that the LTSpice capacitor component includes enough optional parasitic elements that it can stand-in as a reasonable first-order model for a quartz crystal!)

Some manufacturers publish Data Sheets with enough information that you can make reasonable guesses at the values of component parasitics. Including the effective parasitic elements arising from physical PWB layouts is at least an order of magnitude more difficult - not because SPICE can't model them, but because the designer is very hard pressed to determine reasonable values.

This parasitic element feature is seldom used when you draw a schematic diagram and simply assign values, but if you use the "Select Capacitor" dialog rather than just entering numbers, you will find a library of commercial parts with at least a typical ESR specified.


Krisfr 3rd July 2013 07:18 PM

Has anyone ever seen a rectangle used in place of the saw edge for representing the resistor? I would like to use that instead of the saw edge in my diagrams.


jcx 3rd July 2013 07:27 PM

LTspice component selection window: click [MISC] select EuropeanResistor

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