I'm new to this forum, be gentle.
Attached is a design I'm currently working on, in simulation at the moment. I have built a number of amps in the past, each building up on things I've learned along the way. This is the first time I have really tried to simulate first, using Multisim 10.1, but I don't have many of the devices I'd like to use in the database. I'm curious to get some input regarding 'best fit' devices for this design and what ones to use during simulation. The devices listed on the schematic aren't likely the final device choices. Also, the design will also get at least another pair of outputs.
This is one I'm looking for any constructive critique for tweaks, layout tips and so forth on. Thanks.
View attachment Amplifier-CE.pdf
Attached is a design I'm currently working on, in simulation at the moment. I have built a number of amps in the past, each building up on things I've learned along the way. This is the first time I have really tried to simulate first, using Multisim 10.1, but I don't have many of the devices I'd like to use in the database. I'm curious to get some input regarding 'best fit' devices for this design and what ones to use during simulation. The devices listed on the schematic aren't likely the final device choices. Also, the design will also get at least another pair of outputs.
This is one I'm looking for any constructive critique for tweaks, layout tips and so forth on. Thanks.
View attachment Amplifier-CE.pdf
Emitter to Base resistors for output CFP pair are missing.
I've seen CFP's arranged a few different ways. I'm not sure where you are suggesting to place these resistors, base and emitter of which transistors? Are you suggesting the emitter of Q5 and Q16 to their respective rails? Q17, Q5, and Q6 are the upper 'pair', and Q18, Q16 and Q14 the lower 'pair'. I chose to make my outputs darlington pairs mainly because I've never tried it and it actually seems more stable in simulation (of course the 'real world' hasn't had a kick at the can yet). A recommended value and placement?
Complimentary Feedback Pair, as per AndrewT, or Sziklai Pair, thanks.
Base to rail junction of output transistors, 22R is good starting point, these resistor helps in turning OFF the transistors fast during high frequency signals and eliminating cross-conduction effect.
Hi,
I prefer the input filters to be set to ~100ms and 0.7us
you don't have a low pass to attenuate RF and the high pass is set quite high at 235ms
try replacing c4+5 with a 10uF film cap.
R8 looks a bit low. Have you tested the bd139 with the 8r2 to see if you get a near constant voltage?
Q17 & 18 only have ~1.2mA of collector current. This seems very low for BD139/140
R24 seems very high in value. Try 750r or 1k0 and increase VR16 to 1k0
I agree the extra resistors feeding Q5 & 16. 27mA, as suggested by Workhorse, seems about right.
add emitter resistors to Q6 and 14. 0r1 will do.
r22 is quite high in value. investigate advantages of a lower value.
You can add an R+C across the speaker terminals to create a Pi filter for the amp output. It works even when the speaker leads are disconnected. It also offers a bit of RF attenuation that otherwise feeds back through c9 to the inverting input.
Might be worth adding pads for base stoppers to each of the six output devices.
+-50Vdc for supply is risking the 80V devices in the output stage.
I prefer the input filters to be set to ~100ms and 0.7us
you don't have a low pass to attenuate RF and the high pass is set quite high at 235ms
try replacing c4+5 with a 10uF film cap.
R8 looks a bit low. Have you tested the bd139 with the 8r2 to see if you get a near constant voltage?
Q17 & 18 only have ~1.2mA of collector current. This seems very low for BD139/140
R24 seems very high in value. Try 750r or 1k0 and increase VR16 to 1k0
I agree the extra resistors feeding Q5 & 16. 27mA, as suggested by Workhorse, seems about right.
add emitter resistors to Q6 and 14. 0r1 will do.
r22 is quite high in value. investigate advantages of a lower value.
You can add an R+C across the speaker terminals to create a Pi filter for the amp output. It works even when the speaker leads are disconnected. It also offers a bit of RF attenuation that otherwise feeds back through c9 to the inverting input.
Might be worth adding pads for base stoppers to each of the six output devices.
+-50Vdc for supply is risking the 80V devices in the output stage.
Looks pretty much like my AX or Bob Cordell's textbook amp. Drop the CFP , in N. america (Digikey or Mouser) , a pair MJE15032/33 and 2 pair NJW21193/4 or NJW0281/0302 in a EF2 are only $8 USD and will give the most power/lowest THD/reliability for 45-55V rails.
Increase IPS degeneration to 68-100R , CM degen. to 220-270R ... then you may be able to drop the 18pF !!! lead compensation. Also TMC is WAY better than the 2 pole comp you have illustrated. Input stage R/C filter ??? Perhaps an oversight.
With a tail current of about 4 mA and the VAS running at 10+mA ,all looks well besides.
OS
Increase IPS degeneration to 68-100R , CM degen. to 220-270R ... then you may be able to drop the 18pF !!! lead compensation. Also TMC is WAY better than the 2 pole comp you have illustrated. Input stage R/C filter ??? Perhaps an oversight.
With a tail current of about 4 mA and the VAS running at 10+mA ,all looks well besides.
OS
Using BD139/140 on 50V supplies is a bit close to the limits. Look for some better parts such as KSA1381/KSC3503 from Fairchild, or 2SA1290/2SC2911 from Sanyo. For driver duty, use the MJE15032/33 as ostripper recommends.
Really, you need more than one pair of output transistors with 50V supplies.
The split pole compensation does actually work quite well if tuned right.
Really, you need more than one pair of output transistors with 50V supplies.
The split pole compensation does actually work quite well if tuned right.
Thanks for the input thus far.
Everything I have done to this point has been an EF output configuration. This design was started out with a conventional EF output stage, I just thought this OPS looked interesting. I do realize it is a type of 'Output Triple' and that there can be local instability in the OPS. Having just had look in Self's book I see this arrangement as similar to figure 5.6(c) in the section discussing triples. Wasn't my intent to copy, but then again just about every possible permutation has likely been tried by someone along the way.
I don't have in my component database all the devices I'd like to have, so I just picked some I recognize, so I understand some aren't a good fit for the real build. There will be paralleled output pairs in the final design. Many of the values listed were arrived upon during simulation, while others, like my input stage degeneration resistances were calculated based on my chosen CCS value.
With respect to helping the turn-off of the output devices, one could run the driver and preceding circuitry off slightly higher rails than the outputs, this is correct?
AndrewT, you have provided many points to look at. In general would I be better served reverting back to the initial EF design? Some seem to love one or the other with respect to EF or CFP. I have always done EF OPS for some reason, I suppose one becomes comfortable with certain things.
Time to update the schematic for further review. Again, thanks to all for the input so far. Will update and repost.
Jason
Everything I have done to this point has been an EF output configuration. This design was started out with a conventional EF output stage, I just thought this OPS looked interesting. I do realize it is a type of 'Output Triple' and that there can be local instability in the OPS. Having just had look in Self's book I see this arrangement as similar to figure 5.6(c) in the section discussing triples. Wasn't my intent to copy, but then again just about every possible permutation has likely been tried by someone along the way.
I don't have in my component database all the devices I'd like to have, so I just picked some I recognize, so I understand some aren't a good fit for the real build. There will be paralleled output pairs in the final design. Many of the values listed were arrived upon during simulation, while others, like my input stage degeneration resistances were calculated based on my chosen CCS value.
With respect to helping the turn-off of the output devices, one could run the driver and preceding circuitry off slightly higher rails than the outputs, this is correct?
AndrewT, you have provided many points to look at. In general would I be better served reverting back to the initial EF design? Some seem to love one or the other with respect to EF or CFP. I have always done EF OPS for some reason, I suppose one becomes comfortable with certain things.
Time to update the schematic for further review. Again, thanks to all for the input so far. Will update and repost.
Jason
New iteration...
After considering some comments this is the latest iteration. I have left the BD139/BD140's just for convenience, but changed my choices for the outputs in simulation. I'll see what's available in the simulator database that might be better for the VAS and drivers. Seems to simulate nicely, though the Fourier analysis never seems to finish. Perhaps I just need to reboot.
View attachment Amplifier-Triple OPS.pdf
After considering some comments this is the latest iteration. I have left the BD139/BD140's just for convenience, but changed my choices for the outputs in simulation. I'll see what's available in the simulator database that might be better for the VAS and drivers. Seems to simulate nicely, though the Fourier analysis never seems to finish. Perhaps I just need to reboot.
View attachment Amplifier-Triple OPS.pdf
I'm just tossing some ideas around here.
This isn't a typical arrangement and I'm aware of this. I probably wouldn't have bothered to post it if it were a garden variety EF or CFP, those are comfortable and familiar. Of course one will look at a triple with suspicion towards stability, but that doesn't mean it isn't possible to build a good one.
Remember, this is something 'in the works' so to speak and isn't likely the final design before construction. Like I had mentioned, most of the circuit was designed with an EF output, I changed it to 'see what happens' and get some feedback since it looked interesting to me. Thanks for the input, if something like this makes it into real life I'll certainly approach with caution.
This isn't a typical arrangement and I'm aware of this. I probably wouldn't have bothered to post it if it were a garden variety EF or CFP, those are comfortable and familiar. Of course one will look at a triple with suspicion towards stability, but that doesn't mean it isn't possible to build a good one.
Remember, this is something 'in the works' so to speak and isn't likely the final design before construction. Like I had mentioned, most of the circuit was designed with an EF output, I changed it to 'see what happens' and get some feedback since it looked interesting to me. Thanks for the input, if something like this makes it into real life I'll certainly approach with caution.
My 0.99 cents
IMHO: You can try one more approach in triple OS, configure pre-driver + driver in CFP fashion and output stage as EF, it will give you best of both worlds.
IMHO: You can try one more approach in triple OS, configure pre-driver + driver in CFP fashion and output stage as EF, it will give you best of both worlds.
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