Class A headphone amplifier

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As my power amp has no headphone outlet I decided to build a little Class A discrete headphone amplifier, just to see (hear) what it would sound like.

The circuit design is attached. It's quite rudimentary, based on classic op-amp topology: mildly degenerated differential input with current mirror loading; cascode voltage gain stage, and emitter follower output biased into enough class A for driving headphones. The input diff amp current source is controlled by a green LED - I read (about twenty years ago) that green LEDs sound better than red ones. The small signal transistors are Toshiba 2SA1015/2SC2547 complementaries which I had lying around. The output transistors are BD139/140 running at 100 mA bias, so dissipating about 2W apiece. This is OK for driving hi-Z 'phones to very loud - I have a pair of Sennheiser HD600 which are 300 ohms load - without leaving Class A. The supplies are regulated with LM317/337 at 20V. No safety circuitry employed at this low power.

The amp. has open loop gain of about 80 with -3dB at about 40 kHz so I used dominant pole compensation and feeback for stability. The domininant pole cap I used is 1000 pF, with 47 pF across the feedback resistor of 22k for a gain of about 19 and a phase margin of 40 degrees according to the simulator. I used dominant pole compensation for its simplicity, I haven't tried any lead-lag compensation methods.

I built this on some cheap commercial prototyping board, which I would probably not do again as it was a pain getting all the connections sorted out. The grounds were tedious too: I made a few errors which were identifiable on test. The layout is quite compact, though. Most of the components I had laying around and are not especially 'hi-fi'. Resistors are regular metal-film, caps a mixture of electrolytic and ceramic, with mica and polystrene in feedback and signal paths.

Simulated performance looks OK: bandwidth to about 70 kHz, harmonics below 100 dBc, intermods at around -98 dBc. Sounds fine to me.

The circuit could probably be 'beefed up' to give a higher output power: the VAS could be uprated, or the output followers made into 2 stages: you could use a BD135/136 follower pair to drive the 139/140. In fact the BD135/136 were my original choice of output transistors, but I couldn't get them anywhere so used the 139/140 combo. Being lazy, you could probably use the BD139/140 biased at 100 mA to drive another BD139/140 biased at higher collector current, though I haven't tried this out.


-- John
 

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and finally, what it looks like

here's a picture of the amplifier. Sorry the picture's so small, I'm not such a wiz with the digital camera (borrowed).

The toroid is a 120VA 20-0-20 I had lying around and is far too big for this job. Now that I know the amp sounds OK I suppose I should rebuild it properly.

If anyone wants to lay out a PCB, be my guest.


-- John
 

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Simulation software.

Hi John,
That's quite a bit of work you did. Hope the circuit sounds fine.
Did you consider using a power boosted opamp ? Some Opamps could possibly drive the 300 ohm phones to ear bleeding levels even without a power bosting output stage.

What software did you use for your simulation? It looks interesting.
Cheers.
 
Hi Ashok,

I did consider an op-amp based circuit - there are several on the 'Headwize' web-site that look very good, and an elegant one in a recent issue of Audioexpress. I just felt like trying to design a transistor amp, and see what it turned out like.

It sounds real enough to me, but I haven't compared other headphone amps with my cans, so the things I appreciate like detail, reasonable freedom from coloration and a lifelike (lively) sound may be due to the headhones themselves. The sound is similar in tone and tune to my amp/speakers (Linn LK100/Keilidh) but with more detail.

The software is Agilent-EEsof 'Advanced Design System', which for me is freeware (otherwise $25k/year/license). It is an RF/microwave design software, and includes a nonlinear frequency-domain simulator called harmonic balance: this takes all the harmonics and intermod products present in the circuit and 'balances' the contributions of each frequency in the total signal, so it's great for distortion predictions. Surprisingly, it comes with all these libraries of low frequency transistors - the BD139/140 and the Toshiba txs were already in the library, so I just plugged them in and watched the result.

I didn't simulate the regulators, so the power supplies are ideal (zero ohms DC to daylight) and in reality will have an influence on the sound, though using a Calss A circuit should ameliorate practical non-idealities in this respect.

-- John
 
have you tested to connect the compensation capacitor directly to signal ground instead? Maybe you get a little bit smaller load of the current mirror of the input staget?

An interesting suggestion, P-A. I guess I was thinking the C_dom acted like a Miller cap around the voltage amp stage, augmenting the Cbc of the transistor and hence providing the dominant roll-off in the amplifier.

I'll check your suggestion out in simulator-land: I don't have a PC sound card, but it seems like that should be my next audio purchase (darn, I was hoping for a new cartridge).

-- John
 
Classic design, classic arguments; since the topology is basically the same as most power amps many threads elsewhere in solid state cover many of the design choices

Some quick “armchair” engineering comments (which will probably all have vociferous opponents)

BD139/140 seem to be “don’t ask, don’t tell” with regard to speed, if you really have only 40 degrees phase margin with such a heavy dominant pole compensation then they must be < 10 MHz Ft – I would look for 50-100MHz Ft output devices which are readily available at your power/voltage level (MJE171/181)

Faster output devices should let you reduce Ccomp, which with your input stage current, gives a frighteningly low slew rate/power bandwidth limit – this slew rate limit also could be helped somewhat by increasing diff pair bias current (more than ~2X requires reconsidering current noise and input bias)

Ed Cherry continues to advocate moving Ccomp to the output, enclosing the output transistors in the VAS/Ccomp feedback loop; easy to try in sim, may have problems with separately mounted power transistor wiring parasitics

Slew rate/power bandwidth may be helped by 2-pole compensation, your low dominant pole frequency (from the slow output devices) doesn’t leave much room but I think a 2nd pole @~100-200KHz could help – reducing Ccomp or using 2 pole compensation also increases loop gain, reducing distortion

Following Cherry and Self’s analysis, i guess the output stage is still probably limiting gain/linearity due to the nonlinear load on the VAS; an intermediate buffer stage with AC bootstrapping should hugely reduce VAS loading/increase linearity – many power amps use “triple” Darlington/Sziklai ouputs but 2 stages should be enough for a 300 Ohm load

Baxendall’s Super Pair trick lets you have VAS input buffering and cascode output linearity with the same # of components as your cascode – if you add a buffer between the output stage and the VAS then you could consider using the super pair on the VAS current source as well (my reply in: http://www.diyaudio.com/forums/showthread.php?s=&threadid=13335&goto=nextoldest )

Your sim data looks too good to be true with the high Ccomp’s low selw rate limit, what is the reference level for your dB plots? What does a 40 KHz 30 Vpp out waveform look like? (yes you don’t want to listen to it but it should show that your slew limit is too low)

I am in favor of filtering but a single pole @70KHz is arguably audible with ~0.1 dB droop @7KHz, increasing above; I believe DBT advocates claim 0.1 dB level differences over an octave or more are detectable
 
jcx, you are a little bit too pessimistic. Much of the values you mention are higher (better) in real life. If PGW feels a little bit unsure, check my monster headphone amp for suitable currents. My amp works like clockwork. PGW, you don't have to make it symmetrical, just check the values of currents.

0.5-2 mA first stage, 5-10 mA in the VAS stage and a good and fast emitter follower at the end. This _will_ work!

As emitter follower you could use 3-5 pairs of BCxxx transistors. No problems with parallel connection if you have a small emitter resistor at each emitter.
 
jcx,

Thanks for your critique of this circuit. You make some interesting and helpful suggestions.

The stage currents in the amp are similar to those suggested by Per_Anders:

1.5 mA per side for the diff pair, 13 mA (target 15) for the VAS, and the BD139/140 are running @ 100mA.

I hadn't given slew rate _much_ consideration. From the above currents and C_comp, the slew rate of the loaded diff-pair is about 3V/microsec. Is this way too small?
A back-of-envelope estimate of rate of change of input voltage at 20 kHz for a "typical" input signal of 0.2V amplitude is about 30mV/microsec, so I thought this would be fine.

I tried your suggestion of a 40 kHz signal at 30 Vpp (1.5Vpp in) and this does indeed show significant slew rate limiting for this signal. But a signal of ~10Vpp (220mVpp in) at 20 kHz looks fine*. I think this should be OK? if not, why not?

Re: the BD139/140: not much in the way of fT info on datasheets - only Philips quote a figure -
190 MHz at Ic=50mA and Vce=5V.
I am using ONSemi (Motorola) parts. I have seen these devices used in short-wave power amplifier applications so I figured they would be OK.
A quick simulation of beta vs frequency for a 300 ohm load at Ic=300mA and Vce=20V (i.e. amp conditions) yields fT of 20 MHz.
Replacing with the MJE181 improves fT only to 26 MHz under these conditions (at least using the library model in my simulator).
*This SR result using MJE171/181 in simulator.

(Again in simulator-land) I increased the input pair current to 2.5mA/side and obtained good slew performance under your test condition. The bandwidth is also increased - about doubled, with 470pF C-comp, and I remove the feedback cap altogether.

I shall try these changes in hardware (probably not for a week or two unfortunately - I seem to have alot going on) and let you know what differences I hear.

Regards,

-- John
 
The case for more slew rate is largely an argument for more gain*bandwidth in a single pole amplifier. Looking into slew rate limiting in a single pole miller compensated amp like this is another way of thinking about loop gain/distortion issues, to slew at any rate the input diff pair is unbalanced to provide delta_i into Ccomp, the nonlinear part of the resulting delta_Vbe in the input diff pair is a distortion in the feedback error measurement that isn’t reduced by global loop gain.

(Output signal slew rate)/(Slew rate limit) is a way to view loop gain and estimate the input stage distortion in a single pole amp – certainly 3V/us is adequate to prevent hard limiting in this amp for reasonable signals but distortion begins long before the hard slew limit with the small input degeneration used.

To reduce this distortion you can increase slew rate (= increase gain*bandwidth for single pole comp), increase the high audio frequency gain with 2 pole compensation (keeping gain intercept and hard slew limit the same but reducing delta_Vin at the input for audio frequency signals) or increase the input linearity (increasing emitter resistors while making up the lost gain in the VAS, or by increasing bias current) – the “optimum” solution depends on the performance measures and component/topology restrictions chosen leading to different solutions from every designer.

I guess that <~2 mVpp at the diff pair input with the 100 Ohm emitter resistors would keep input stage delta_Vbe distortion < -120 dB. Driving the HD600s to rated power requires ~ 14 Vpp (80 mW into 300 Ohms, ~ 110 dB SPL) giving a required open loop gain of 7K, assuming a favorably low 3 KHz as the power bandwidth of music requires 20 MHz gain*bandwidth with a single pole amplifier ~ 10X more than the current circuit; sufficient justification in my mind to explore 2 pole compensation and higher bandwidth.

2 pole compensation makes added VAS gain visible to the global feedback loop; the upside is potentially reducing total distortion to the noise floor– only 3 small signal transistors and a pair of resistors extra implement all of my suggestions (super pair both the VAS Q and the current source Q, eliminating the cascode; Sziklai compound output followers; steal r,c from cascode bias for 2 pole comp around output); why not see how much further these get you?(at least in sim)

Simulation is valuable to explore options, better than simulated/modeled performance in hardware is welcome, but I don’t rely on it happening often.
 
I suppose you could say it sims a little better than just ok, the attached harmonic distortion plot shows intermod/harmonic components just peeking over –120 dBV with the output peaking at +23 dBV (30 Vpp), the distortion is ~ -140 dB down from the output at nearly the max voltage swing – not bad for 3 extra transistors!

I would call this VAS+Output “blameless” in Doug Self’s sense; he had a recent EW article pointing out diff input stage common mode distortion limits which is the most likely limiting factor in an amplifier adopting these output modifications

I changed the gain to +10 for the plot (with 2 Vrms digital source I don’t need more gain for my HD600) so you probably should add 6 dB to my distortion to compare to your higher gain

A real diff input with current mirror out is likely to give somewhat lower open loop voltage gain due to its own output resistance – I can’t sim a full front end in orcad demo due to limited # of Qs allowed
 

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jcx,

Thanks for the circuit and the demo of its performance.

Are you still advocating the use of MJE171/181 output followers? As simple followers or as the output half of the compound follower that you have shown. Your OL gain is 7K (~77 dB) and BW is 10 MHz with the transistors shown?

Any problems with stability with this 2-pole compensation?

-- John
 
Baxendall super pair VAS driving the high impedance of the Sziklai compound output followers moves the goalposts on open loop gain

2 pole comp allows a lot more loop gain in the compensated circuit as well, pspice sim and 2 pole compensation math show open loop gain 32K from diff input to output at 20KHz, while the math suggests 2KHz gain should be 3.2 million at 2 KHz pspsice shows 5 million possibly due to a peaking where the VAS open loop gain intersects the 2 pole compensation feedback curve – real diff input may drop the low frequency open loop gain by 10-20 dB, still giving >>100K gain before reaching the region controlled by the compensation

I have shown rather aggressive 2nd pole placement, only a factor of 2 below the closed loop gain intercept with the ~16 MHz gm/C1 gain curve (input diff pair modeled as G1, gm = 1/(100 ohm), C1 = 100pF; closed loop gain intercept with Acl = 10 at ~ 1.6 MHz; 2nd pole at ~200 Ohms * 1 nF = 800 KHz), this depends on how much phase margin you need; my scheme should give ~ 60 degrees less any unmodeled input stage or ouput phase shift. The 2nd compensation pole can be moved further away from the closed loop gain corner by increasing R12 – with the output stage inside the compensation feedback loop there should be little effect on output stage distortion, just less global gain for reducing input differential voltage (reducing differential input voltage level is the only way loop gain can reduce input Vbe distortion)

2 pole compensation may slow recovery from output clipping, I haven’t tried Cload on the output or banging the output with a current source per Bob Pease’ hands on stability evaluation procedure which I would recommend in both sim and hardware

I don’t have a strong opinion on actual power output devices to use in the compound follower for Q1&3, if the BD139/140 are fast you might as well stick with them, I’ve discovered a cache of D44/45H amongst our prototyping stock at work…

Note: C4 isn’t intentionally playing any role in the compensation, I just included it for testing and figured a 1 pF value pretty much took it out of the circuit (same with C3)
 

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> I hadn't given slew rate _much_ consideration. From the above currents and C_comp, the slew rate of the loaded diff-pair is about 3V/microsec. Is this way too small?

Tolerable.

Jung's rule is still a good guide. 1V/µS per peak volt of audio. If you use +/-15V supplies because you need to (to avoid bass-mid clipping), then you want 10 or 20V/µS so the treble won't come out all triangles. In hi-fi we often stick to 2.8V peak signal, so 2 to 5V/µS is enough.

> a "typical" input signal of 0.2V amplitude

Never mind "typical". What is the MAX treble you ever listen to? If you really need those +/-20V supplies to avoid voltage-clipping, then Jung says you should probably aim for 20V/µS to avoid slew limiting with normal music at that level. His methodology was tough, I would not say that 10V/µS was "too little". But 3V/µS is appropriate for peaks close to 5V. You say the 20V is for "headroom", I say the treble slew needs headroom too.

And yes, there are phones, ears, and listening situations where 20V peak is just about right. And in those situations, you probably don't want to be wondering if the smeared highs is in the original or just in your amplifier.

To improve slew: you can reduce Miller, but not when you have slow output devices. For a bipolar input pair, slew, GBW, and output stage speed all go together. Alternatively you can add emitter resistors to the input pair, though you already have substantial resistance there.
 
jcx

Hi

re your headphone amp cct, could explain the function of the little box labled G1. there seems to be a current source in it. the i/p & feedback signals goes to it but they don't seem to be connected to anything in particular. am I missing something here ?

many thanks

mike
 
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