In a non-os design it gets 44.1 kHz periodicity latch enable signal. This signal may be reclocked (i. e. the leading edge de-jittered) by a low-jitter clock of any frequency that is integer multiple of 44.1 kHz and runs synchronously with the original latch signal.
The data and clock signal can be up to 6.4 MHz according to the data sheet.
The data and clock signal can be up to 6.4 MHz according to the data sheet.
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