I've been exploring (via simulation only, so far) the effect on THD that I get by employing a differential vs a non-differential symmetrical voltage amp. I'm using the 50W MOSFET amplifier that I've been playing with of late. Basically, I've simply removed one side of the VAS, then tweaked the bias to ensure the output MOSFETs are running the same quiescent current (70mA).
Performance at 1KHz was much as I expected. The non-differential circuit is slightly worse. When putting a 1KHz 50W sinewave into an 8 Ohm load, I measure 0.00014% THD for the differential VAS, and 0.00028% for the non-differential one. This is, BTW, a design optimised at 1KHz)
However at 10KHz it's a very different story. I'm seeing a dramatic improvement in THD performance with the non-differential VAS.
In a nutshell, putting a 10KHz, 50W sinewave into an 8 Ohm load, the THD for the differential VAS measures at 0.046%, whereas the non-differential VAS measures 0.0050%. At 25W (in case it's a headroom issue) it's 0.034% and 0.0044% respectively.
I guess the reduced capacitive loading being placed on the single-ended-to-differential stage that precedes it, along with running the remaining VAS transistors at close to twice the Ic, are responsible for the improvement.
Of course in real life the performance may be very different.
Anyway, I've attached a screen grab of the differential circuit. I'll put the non-differential one in the next post.
I'd appreciate people's thoughts on the mechanisms at work here, as I don't think I have a full understanding of what's happening.
Performance at 1KHz was much as I expected. The non-differential circuit is slightly worse. When putting a 1KHz 50W sinewave into an 8 Ohm load, I measure 0.00014% THD for the differential VAS, and 0.00028% for the non-differential one. This is, BTW, a design optimised at 1KHz)
However at 10KHz it's a very different story. I'm seeing a dramatic improvement in THD performance with the non-differential VAS.
In a nutshell, putting a 10KHz, 50W sinewave into an 8 Ohm load, the THD for the differential VAS measures at 0.046%, whereas the non-differential VAS measures 0.0050%. At 25W (in case it's a headroom issue) it's 0.034% and 0.0044% respectively.
I guess the reduced capacitive loading being placed on the single-ended-to-differential stage that precedes it, along with running the remaining VAS transistors at close to twice the Ic, are responsible for the improvement.
Of course in real life the performance may be very different.
Anyway, I've attached a screen grab of the differential circuit. I'll put the non-differential one in the next post.
I'd appreciate people's thoughts on the mechanisms at work here, as I don't think I have a full understanding of what's happening.
Attachments
suzyj said:
Hi Suzy.
Your single ended VAS has a quiescent current of approximately 9.3mA. Your differential VAS has a tail current of approximately 10.8mA, giving 5.4mA (contrasted with 9.3mA) per leg.
You need a high quiescent VAS current to drive the MOSFET input capacitance at high frequencies with low distortion.
Try increasing the differential VAS tail current to at least double the single ended VAS quiescent current (~20mA), but don't go too far with lowering the emitter degeneration.
Cheers,
Glen
suzyj said:
Hi Suzy,
It seems to me that in order to maintain balance in the diff pair VAS, you should float the collectors that are currently grounded, or actually load them with a resistor to ground so that they produce about the same signal level as the side driving the output stage. This should help to maintain balance at HF with regard to Miller capacitance in the devices. Seems it would make sense to use the same Cdom caps on both sides of the pairs, again to maintain HF symmetry.
I would then try looking at it open loop to see what's happening to the gain and bandwidth between the two cases, and of course the open loop distortion if the above suggestion doesn't work.
I prefer to run the VAS closer to 5 or 10 mA when possible since most of the popular devices have their best performance in this range. I also want there to be enough available current to swamp the non-linear parasitic capacitances. I always found that high bias current worked best in low complexity video amps that I've designed.
The diff pair VAS was starting to grow on me since it provides a source for a balanced output which is something I've been thinking about for some time now.
Once again, nice work.
Pete B.
G.Kleinschmidt said:
This is the core of what's confusing me. When I double the current in the differential VAS, such that the current in each side is equal to the current in the non-differential case, I'd expect the distortion figures to be better than the single ended case. That doesn't happen though. Instead I only get marginal improvement in THD (to 0.032%).
It's a little frustrating, as it's just not behaving as I think it ought to do.
I might try replicating more of the load on the other side (as per Pete B's suggestion) and see what effect that has.
suzyj said:
I think your differential VAS problems would go away if you were to simply cascode all four VAS transistors.
Replicating the voltage swing on the currently grounded side would be quite difficult, as the MOSFET input capacitance and the miller compensation capacitors will demand higher drive current at HF.
This means that, for example, if you resistively loaded the idle side to match the voltage swing at 1kHz, at 20kHz the idle side will well and truly saturate.
Cheers,
Glen
G.Kleinschmidt said:
Glen, that would probably work, but it is complex and reduces the swing of the VAS.
I suggest a resistive load to match the diff VAS outputs at say 10 Hz, and a capacitor to match at 10 kHz, and then see if this is a good enough approximation. I'd say that this has to be the problem since it is obviously frequency dependent. Might be a model problem also with the VAS transistors.
You could also remove the output devices and just put a resistive load on the VAS to try the different test cases. This way you could have perfect symmetry on the two sides of the diff pair.
Pete B.
suzyj said:
Suzy,
It is possible the distortion is originating somewhere else and the
VAS component is only part of the picture.
The basic topology goes to heroic lengths to linearise the VAS
with 2 cascaded / degenerated approach and then attempts
to drive the highly non linear capacitance of the OP MOS devices
with a high Z current drive.
It could be well worth to simplify the VAS and insert a small sig
high, BW (ie; very low c) bjt follower in front of the OP MOS
devices.
This will effectively isolate them and provide a much more linear &
frequency independant load to VAS.
Greg Ball did this in his SKA to such good effect with the addition
of some clever bootstrapping that he did away with VAS all
together and still retained VG linearity.
cheers
Terry
PB2 said:
I think that could be made to work to an extent in simulation, but in real life you also have the MOSFET input capacitance to compensate for as well, and that varies wildly with load current.
I agree that cascoding would limit the output swing though, which is already limited due to the high Vgs of the lateral MOSFETs. On the other hand though, a design of this complexity probably deserves seperate, higher voltage rails to the low-level circuitry to compensate.
I agree. In fact, just simulating the different VAS stages by themselves would probably be better than simulating the entire amplifier.
Cheers,
Glen
G.Kleinschmidt said:
Some voltage swing on the side that was grounded is much better than zero if you know what I mean, and often close enough works very well when you're trying to keep things simple. If this approximate load produces a diff VAS with half the distortion, or less, than the single ended version then we might say close enough and go with it. Design is a compromise as I'm sure you know, the distortion is already low just trying to make it a bit better. Obviously, design involves compromises and choosing among the many options is part of the art as I'm sure most here know.
Pete B.
Terry Demol said:
I certainly follow your points here, Terry but I thought I'd offer another perspective. I don't believe that VAS buffering is always required as many suggest, running the VAS hot is fine and let me throw out the idea of nested feedback to lower the output impedance of the VAS. I believe that Suzy added more degeneration to each stage, she could perhaps give some forward gain back, and use feedback directly from the VAS to lower the output impedance of the voltage gain stages. And of course retain the main loop for the output stage. Seems to me that it is simpler and there is plenty of forward gain to support the idea.
Pete B.
Some success
Matching the load on both sides of the VAS is the key.
I started with the original differential circuit, as shown in the first post in this thread. It did 0.046% THD (10KHz, 50W, 8 Ohm).
The first thing I did was remove the ground connection on the collectors of the VAS transistors that aren't connected to the FET gates. That had a dramatic effect, dropping the THD to 0.015%.
Next, I put a 220 Ohm resistor between the collectors. This gave a very modest improvement to 0.014%.
Adding some miller caps (10p) to this side reduced the THD to 0.013%
Finally, I did a crude replication of the FET gate capacitance and resistance, by putting 220 Ohms in series with 22p across the original 220 Ohm load resistor. Now the THD dropped considerably, to 0.0040%.
The 1KHz THD is degraded marginally, to 0.00022%.
So I guess the lesson is that, for a given current, a fully differential VAS is only really useful if you go all-out in replicating the load on both sides. If you're not prepared to do that, you're probably better off sticking with the non-differential topology. Even then it's debatable whether it's worth the added complexity.
Matching the load on both sides of the VAS is the key.
I started with the original differential circuit, as shown in the first post in this thread. It did 0.046% THD (10KHz, 50W, 8 Ohm).
The first thing I did was remove the ground connection on the collectors of the VAS transistors that aren't connected to the FET gates. That had a dramatic effect, dropping the THD to 0.015%.
Next, I put a 220 Ohm resistor between the collectors. This gave a very modest improvement to 0.014%.
Adding some miller caps (10p) to this side reduced the THD to 0.013%
Finally, I did a crude replication of the FET gate capacitance and resistance, by putting 220 Ohms in series with 22p across the original 220 Ohm load resistor. Now the THD dropped considerably, to 0.0040%.
The 1KHz THD is degraded marginally, to 0.00022%.
So I guess the lesson is that, for a given current, a fully differential VAS is only really useful if you go all-out in replicating the load on both sides. If you're not prepared to do that, you're probably better off sticking with the non-differential topology. Even then it's debatable whether it's worth the added complexity.
Re: Some success
Nice to see your refinement of the design being driven by well thought out decisions.
As I understand it, you've placed the load between the collectors? I'd expect the best results with the load going to ground, something to approximate the highly capacitive FET load impedance. I was speaking in the general case earlier not concerned with FET or BJT. Most likely that what you did above worked well because any signal on the collectors is better than none.
I don't recall all your distortion measurements, however I'm wondering how this all ties in with the measured performance of your 100 and 50 W amps. It would be interesting to see what lifting the ground on your 50W amp, with a reasonable load added, does to the measured distortion. Then going to a single ended VAS would be easy as a test to see if that might be a solution for the 50W amp. Thinking that you're probably having similar thoughts.
Pete B.
suzyj said:
Nice to see your refinement of the design being driven by well thought out decisions.
As I understand it, you've placed the load between the collectors? I'd expect the best results with the load going to ground, something to approximate the highly capacitive FET load impedance. I was speaking in the general case earlier not concerned with FET or BJT. Most likely that what you did above worked well because any signal on the collectors is better than none.
I don't recall all your distortion measurements, however I'm wondering how this all ties in with the measured performance of your 100 and 50 W amps. It would be interesting to see what lifting the ground on your 50W amp, with a reasonable load added, does to the measured distortion. Then going to a single ended VAS would be easy as a test to see if that might be a solution for the 50W amp. Thinking that you're probably having similar thoughts.
Pete B.
Re: Re: Some success
Nothing on the FET side is connected (in a DC sense) to ground though. The FET gates are very high impedance at DC.
I guess I could separate the capacitance of each side, by collecting series RC from each VAS collector to ground, rather than across the 220 Ohm load, such that the different gate capacitance of each FET is accounted for...
That's an interesting question. My webpage describing the design of the 100W amp shows simulations with less gain than the final amplifier had (due to some stability issues). When I simulate the amp as builtt at 10KHz/100W/8 Ohms, I get 0.0092% THD (+/-56V supplies). Measurements of the real thing are a little better than that, at 0.0048%.
I'm currently constructing the 50W circuit on a spare 100W amp board, so that I can test out some of this stuff in reality. The 100W board uses all TO-126 transistors in the VAS, rather than the mix of SOT-23 and TO-126s that my original 50W board used. I've also ordered some 2SA1209, 2SC2911, KSC3503, and KSA1381 transistors, so I can get a handle on what effect the different VAS transistors have.
The 100W board is easily modifiable, so it's a good test-bed for trying different VAS configurations.
PB2 said:
Nothing on the FET side is connected (in a DC sense) to ground though. The FET gates are very high impedance at DC.
I guess I could separate the capacitance of each side, by collecting series RC from each VAS collector to ground, rather than across the 220 Ohm load, such that the different gate capacitance of each FET is accounted for...
PB2 said:
That's an interesting question. My webpage describing the design of the 100W amp shows simulations with less gain than the final amplifier had (due to some stability issues). When I simulate the amp as builtt at 10KHz/100W/8 Ohms, I get 0.0092% THD (+/-56V supplies). Measurements of the real thing are a little better than that, at 0.0048%.
I'm currently constructing the 50W circuit on a spare 100W amp board, so that I can test out some of this stuff in reality. The 100W board uses all TO-126 transistors in the VAS, rather than the mix of SOT-23 and TO-126s that my original 50W board used. I've also ordered some 2SA1209, 2SC2911, KSC3503, and KSA1381 transistors, so I can get a handle on what effect the different VAS transistors have.
The 100W board is easily modifiable, so it's a good test-bed for trying different VAS configurations.
Re: Re: Re: Some success
I was simply thinking from a loading perspective, that the VAS will see some equivalent impedance to ground. Sure the FETs are a high impedance DC load, and whatever the equivalent approximate capacitive load to ground. All I had in mind was to better match the other side and maintain HF balance.
I saw in your other thread that you solved the 50 W distortion mystery, good to hear, it just didn't make sense when you had such excellent performance in the 100W version. We all get bit by those nasty details from time to time.
Those transistors do look interesting, I might try some of them myself.
Still curious to know if the diff or single ended VAS provides lower distortion in real life.
Pete B.
suzyj said:
I was simply thinking from a loading perspective, that the VAS will see some equivalent impedance to ground. Sure the FETs are a high impedance DC load, and whatever the equivalent approximate capacitive load to ground. All I had in mind was to better match the other side and maintain HF balance.
I saw in your other thread that you solved the 50 W distortion mystery, good to hear, it just didn't make sense when you had such excellent performance in the 100W version. We all get bit by those nasty details from time to time.
Those transistors do look interesting, I might try some of them myself.
Still curious to know if the diff or single ended VAS provides lower distortion in real life.
Pete B.
PB2 said:
Yes, I don't think that I disputed any of this. The point that I am trying to get across is that matching the load on the other side of the VAS could only be done very crudely; due to the wildly variable (with Id and Vds) MOSFET input capacitance.
This would be inferior to cascoding, which removes the large signal voltage swing from each differential VAS transistor altogether.
One benefit of the differential (over the single ended) VAS that hasn’t been mentioned yet is the ease with which it’s clipping / overload characteristics can be governed by its emitter degeneration and diode clamping the input voltage swing.
Cheers,
Glen
G.Kleinschmidt said:
And I did not dispute you, I just prefer the simpler solution as long as it provides the improvement in performance that is desired. You do nice work Glen, and it is clear that you like complex designs. I prefer designs that meet requirements with the lowest part count possible, in fact, I see it as part of the challenge. I certainly understand that a diff amp has advantages, especially where large signal swings are required. I simply suggested single ended to get a baseline for comparision and as a solution to what we thought was a thermal problem. As I mentioned earlier, I was not certain that it was positively a thermal problem.
Suzy's work has made for interesting discussion, and it is nice to see the simulations and prototype work in support of the comparisions.
Pete B.
G.Kleinschmidt said:
Glen, you are riight on here.
Mosfet capacitances:
Ciss=Cgs+Cgd.
Coss=Cds+Cgd
Crss= Cgd
The capacitances are quite significant, load dependant - IOW
if the OP stage drives 8R effective Ciss as seen by VAS will be
different compared to 4R as there will be more voltage swing
between g-s. Add to this the fact that they are also voltage
dependant and non linear.
Main reason why I suggested a bjt small sig driver in front of
them.
Also it is worth mentioning here that lifting the 'opposite side'
VAS collectors off ground has little chance of working in reality. It
consitutes two CCS balancing each other. They will most
likely clip or simply drift way off nominal.
Geez - I'm starting to sound like a grumpy old fart.... must be
over training / undersleeping.
Terry
PB2 said:
Thanks Pete. I've found DIYaudio really useful for improving my understanding of this stuff. I enjoy the discussions too.
I've been trying to work out what my optimisation goals are. I've got no fear of complexity, certainly, but I only add complexity when I can see a reason for doing so.
On reflection, I think my goal is to get the perfect performance/efficiency compromise. I'm a bit of a greenie at heart, and don't like the idea of dissipating piles of power unless there's a clear payoff. Hence the move to lower power amps, running with lower bias currents.
suzyj said:
Makes sense, yes. I too like the performance of Class A but not the heat, size, weight, etc. More of a challenge to get it with a lower power design. Yes, discussions here have me thinking of finally going to a FET input stage, perhaps diff amp VAS, and thinking about EC output stages, all nice food for thought.
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.