Need help with half bridge : problem with gate driver transformer

[alexclaire]

hi everyone,

Let me explain my project:

230Vac----->+/- 40 VDC
350-400W

230V AC mains---->320VDC rectified
2*660uF/200V capacitors
Half bridge SMPS topology
SG3525 oscillator and modulator (fosc=200kHz;fsw=100kHz)
12V auxiliary power supply
No feedback
ETD39 core
Bmax=100mT
N1=32 turns
N2=16 turns center tap
capacitor 1uF in serie with primary connected to +160V (middle point of capacitors)
2*IRF840 driven by gate transformer (3C90 core 13.5mmOD, 12:12:12 between pin 11&14 with 10 ohms in serie)
gate transformer driven by transistors mounted in push pull topology (2N3906 and 2N4401)

my problem is:
signal fed to fet gates is not clean (see the pics)

could anyone tell me more ?

Thanks

[alexclaire]

and the complete prototype board (without ETD39 core)

[Eva]

It does not look so bad, most of the distortion comes from the fact that the primary is driven from one or more cascoded class B buffers with 1V dead band, that produce heavy crossover distortion. Try a 1K load in each secondary and a 1uF DC blocking capacitor in the primary side. Try also to simulate a MOSFET gate load on the secondaries.

[alexclaire]

Hi Eva,

I've followed your advices and no changes here are some pics

gate driver secondary

do U think such a signal can drive fets correctly ?

Thanks for your reply !

[alexclaire]

and gate transformer primary (with 1uF DC blocking cap)

no change because mean value of this signal was already 0...

[Eva]

Oh, then the problem is in the primary side. You are driving the transformer directly from SG3525A outputs, aren't you? Then you have to add clamping diodes (1N4148, or better 1A ultrafast, or better 1A schottkys) between each output of the SG3525A and Vcc and ground.

[alexclaire]

Hi,
Clamp diodes UF4004 have been implemented but no change at all.
the problem is from SG3525
I've checked pin11 & 14 potential and it's no so clean...with no load...
maybe the need of some decoupling caps...to be continued ;-)

[N-Channel]

Hi Alex,

Is your driver buffer on the primary side or secondary side of the driver transformer? Since the drive for the SG3525's output is only 100mA (steady-state), and 400mA (peak), your distortion is probably from being at or near the drive limit of its totem-pole outputs.

Like Eva suggested, try a UF4002 at each output, and follow this by an NPN-PNP buffer driver in between each of the '3525's outouts and the primary of the drvr xfmr.
Steve

[alexclaire]

finally i decided to connect the main transformer ETD 39 with only primary (32 turns) and to check the waveforms.
Signal is perfect on the primary side.
gonna add the secondary windings and check the secondary waveforms...
Thanks.

[alexclaire]

the control circuitry absorbs 70mA@ 12V so no problem for the SG3525.