I am trying to design a voltage regulator for high current and high voltage (up to say 80V output).
The basic idea is to be able to use an opamp which will like need a positive supply lower then the positive rail, so I include a simple shunt regulator to feed the opamp. The opamp drives the two transistor drivers (two to get the polarity correct) which drive the FET. Feedback from the load is sent to the inverting input on the opamp with a voltage divider to set the gain/output voltage. The non-inverting input is connected to a simple zener voltage reference.
Attached is my first attempt at the circuit. I would appreciate any feedback I could get. Funny thing is the circuit looks a lot like an amplifier to me.
Cheers!
Russ
The basic idea is to be able to use an opamp which will like need a positive supply lower then the positive rail, so I include a simple shunt regulator to feed the opamp. The opamp drives the two transistor drivers (two to get the polarity correct) which drive the FET. Feedback from the load is sent to the inverting input on the opamp with a voltage divider to set the gain/output voltage. The non-inverting input is connected to a simple zener voltage reference.
Attached is my first attempt at the circuit. I would appreciate any feedback I could get. Funny thing is the circuit looks a lot like an amplifier to me.
Cheers!
Russ
I would feed the reference off the same rail that feeds the op-amp as it will be subject to less disturbance.
Have you considered driving a PNP transistor then MOSFET, instead of the double NPN arrangement which may be harder to stabilise?
Also consider using a BJT as the pass element to gain less loss, although if the current is pretty high the drive could be a problem.
edit: looking at the op-amp supply chain again, I would employ a shunt regulator not simple wholesale voltage dropping. Connect the cathode of the zener to ground and feed the op-amp off the resistor-zener node. This would give you a much cleaner feed for your op-amp.
Have you considered driving a PNP transistor then MOSFET, instead of the double NPN arrangement which may be harder to stabilise?
Also consider using a BJT as the pass element to gain less loss, although if the current is pretty high the drive could be a problem.
edit: looking at the op-amp supply chain again, I would employ a shunt regulator not simple wholesale voltage dropping. Connect the cathode of the zener to ground and feed the op-amp off the resistor-zener node. This would give you a much cleaner feed for your op-amp.
The N-MOS pass element implies a minimum drop of some 5 V or so depending on type (Vgs for desired Id). You'd need an auxiliary supply above Vin or a P-channel MOSFET (to reduce that, or accept it as a limitation.
Why do you include C1? I'd reconsider the opamp supply, parallel zener or zener+transistor will be safer; I'd also protect the MOSFET gate externally (unless yours has built-in zeners).
And finally, it's likely to need some compensation, don't turn it on without a 'scope. R3 in particular shouldn't be too large since it has to charge Q1's gate.
Why do you include C1? I'd reconsider the opamp supply, parallel zener or zener+transistor will be safer; I'd also protect the MOSFET gate externally (unless yours has built-in zeners).
And finally, it's likely to need some compensation, don't turn it on without a 'scope. R3 in particular shouldn't be too large since it has to charge Q1's gate.
You're right Jan. He needs to reverse the transistor orientation and add an emitter resistor.
The other mentioned gate protection zener is also advised - connect it between source and left of the gate resistor, with a normal diode in series to prevent reverse spikes travelling back into the regulator and frying the gate..
The other mentioned gate protection zener is also advised - connect it between source and left of the gate resistor, with a normal diode in series to prevent reverse spikes travelling back into the regulator and frying the gate..
The end of R7 should be to 0V but as I have made a mistake on the orientation of the PNP 
it's irrelevant. I think you might have to go back to the two NPNs to get the level shifting, or use one NPN and swap the op-amp inputs round as Jan suggested.
Not sure what's going on with D1 and D4, you only need one.
Seems I didn't explain very well what you need to do with the gate protection zener, or maybe you misunderstood me. By source I meant the MOSFET source. The normal diode is in series with the zener not the gate.
it's irrelevant. I think you might have to go back to the two NPNs to get the level shifting, or use one NPN and swap the op-amp inputs round as Jan suggested.Not sure what's going on with D1 and D4, you only need one.
Seems I didn't explain very well what you need to do with the gate protection zener, or maybe you misunderstood me. By source I meant the MOSFET source. The normal diode is in series with the zener not the gate.
Indeed.
Now the interesting thing is how to set up that transistor. Let us start by assuming the opamp output is in the middle of the opamp supply for max dynamic range. Then take, say, 10mA standing current in the transistor so that it will be able to quickly charge/discharge the gate and still work in class A. From that the emitter resistor can be calculated.
The collector resistor than can be calculated from the collector current (same as emitter current, sort of) and the Vin-Vgate.
And oh yes, a gate stopper 20 ohms or so....
Jan Didden
Now the interesting thing is how to set up that transistor. Let us start by assuming the opamp output is in the middle of the opamp supply for max dynamic range. Then take, say, 10mA standing current in the transistor so that it will be able to quickly charge/discharge the gate and still work in class A. From that the emitter resistor can be calculated.
The collector resistor than can be calculated from the collector current (same as emitter current, sort of) and the Vin-Vgate.
And oh yes, a gate stopper 20 ohms or so....
Jan Didden
That's the fella
If you make C4 quite big it will give you a time delay characteristic in conjunction with R2, this can be used to give you a measure of soft-start of the output voltage But be wary of making C3 big, really it only needs to provide decoupling for the op-amp, and IMO the parallel cap C2 is not really needed. I'm sure you could leave a space for it for tweakers though.
If you make C4 quite big it will give you a time delay characteristic in conjunction with R2, this can be used to give you a measure of soft-start of the output voltage
But be wary of making C3 big, really it only needs to provide decoupling for the op-amp, and IMO the parallel cap C2 is not really needed. I'm sure you could leave a space for it for tweakers though.
Nice to have helped.
If you use a dual secondary transformer and separate bridge for each winding pair, then you don't need a negative regulator. Because the windings are isolated you can put one of these positive regulators on each winding, then the upper reg 0V connects to the lower reg +ve and there you have your +0- dual supply
This saves you hassle of finding a suitable p-channel MOSFET.
If you use a dual secondary transformer and separate bridge for each winding pair, then you don't need a negative regulator. Because the windings are isolated you can put one of these positive regulators on each winding, then the upper reg 0V connects to the lower reg +ve and there you have your +0- dual supply
This saves you hassle of finding a suitable p-channel MOSFET.
richie00boy said:Nice to have helped.
If you use a dual secondary transformer and separate bridge for each winding pair, then you don't need a negative regulator. Because the windings are isolated you can put one of these positive regulators on each winding, then the upper reg 0V connects to the lower reg +ve and there you have your +0- dual supply
This saves you hassle of finding a suitable p-channel MOSFET.
Hmmm, would that also work with a center tapped trafo?
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