Hello all,
I designed a regulated push pull SMPS using PWM Controller SG3525 and 2x MOSFET IRFB41N15D connected via 10R.
Input voltage is +36VDC, output voltage is +32V/1A.
Loads are audioamplifiers and some relais logic used in an
intercom system.
The SMPS works several days and suddenly one or both
MOSFETs are destroyed. Who has any idea, what could happened?
I used SG3525, IRFB41N15D, the same transformer and other same parts in several application in SMPS up to 200W with no problems. I am absolutely sure, that there is no problem with overvoltage, undervoltage, transients, overheating.
Charging current is limited by softstart function of SG3525.
I use a common shunt for both MOSFETs to detect short and
overload. The shutdown pin of SG3525 is connected to the shunt via a 470R resistor, so pulse by pulse current limiting is sure.
IRFB41N15D is overdesigned for this low output power, so
i assume, that all parameters are within limits.
Measurements at gates and drains show clean signals.
Is it possible, that under special conditions the FETs are destroyed by shoot through? How could this occure?
Has anyone experience with layout problems? I use a 4 layer board with power planes and think that the gates of MOSFETs are connected short.
I designed a regulated push pull SMPS using PWM Controller SG3525 and 2x MOSFET IRFB41N15D connected via 10R.
Input voltage is +36VDC, output voltage is +32V/1A.
Loads are audioamplifiers and some relais logic used in an
intercom system.
The SMPS works several days and suddenly one or both
MOSFETs are destroyed. Who has any idea, what could happened?
I used SG3525, IRFB41N15D, the same transformer and other same parts in several application in SMPS up to 200W with no problems. I am absolutely sure, that there is no problem with overvoltage, undervoltage, transients, overheating.
Charging current is limited by softstart function of SG3525.
I use a common shunt for both MOSFETs to detect short and
overload. The shutdown pin of SG3525 is connected to the shunt via a 470R resistor, so pulse by pulse current limiting is sure.
IRFB41N15D is overdesigned for this low output power, so
i assume, that all parameters are within limits.
Measurements at gates and drains show clean signals.
Is it possible, that under special conditions the FETs are destroyed by shoot through? How could this occure?
Has anyone experience with layout problems? I use a 4 layer board with power planes and think that the gates of MOSFETs are connected short.
SMPS Minimum Load
SMPS3525 (I like that name);
What is your minimum load? I seem to recall that without a minimum load on such a supply, the pulses to the MOSFETs becone very narrow, causing spikes on the transformer primary, possibly in excess of the MOSFETs' 150V(dss) rating. Is the amplifier connected all the time, or did the you run the supply no-load?
Steve
SMPS3525 (I like that name);
What is your minimum load? I seem to recall that without a minimum load on such a supply, the pulses to the MOSFETs becone very narrow, causing spikes on the transformer primary, possibly in excess of the MOSFETs' 150V(dss) rating. Is the amplifier connected all the time, or did the you run the supply no-load?
Steve
The minimum load is about 200mA, the quiescent current of the audio amplifiers. Maximum current is only 1.5A.
First i though about problems with transients.
So i added suppressor diodes P6KE100A from Drain to Source
of both MOSFETs. At the output there is a 1.5KE33A.
There are Zenerdiodes 13V from gate to ground.
There is bypass capacitor placed very close to the FETs.
The lines to the Transformer are very short.
I tested surge pulses of 4kV (5/50us) to the input and to the
output. I could not destroy the MOSFETs.
But after several days or weeks one or both FETs are short.
thanks for your replies
First i though about problems with transients.
So i added suppressor diodes P6KE100A from Drain to Source
of both MOSFETs. At the output there is a 1.5KE33A.
There are Zenerdiodes 13V from gate to ground.
There is bypass capacitor placed very close to the FETs.
The lines to the Transformer are very short.
I tested surge pulses of 4kV (5/50us) to the input and to the
output. I could not destroy the MOSFETs.
But after several days or weeks one or both FETs are short.
thanks for your replies
The whole stuff is built in railway cars. At the same input voltage
there is another Poweramplifier. In this Poweramp i used nearly
the circuit for the powersupply. The main difference is the +/- output voltage for the amp.
The other difference is that in this case i did not use zenerdiodes at the gates. I never had a problem with hundreds of these units.
So i cannot understand the problem in my new design.
I measured gate voltages at all worse case conditions as rapidly
changing load, short circuit, overheat, over/under voltage, start up under all conditions.
OK, one difference are the added zenerdiodes, but how could this be a problem? How can clamping diodes cause ringing?
I have never seen ringing at the gates. Is it difficult to measure this effect? does this effect occure only under special conditions?
Do you have further informations about this manner?
there is another Poweramplifier. In this Poweramp i used nearly
the circuit for the powersupply. The main difference is the +/- output voltage for the amp.
The other difference is that in this case i did not use zenerdiodes at the gates. I never had a problem with hundreds of these units.
So i cannot understand the problem in my new design.
I measured gate voltages at all worse case conditions as rapidly
changing load, short circuit, overheat, over/under voltage, start up under all conditions.
OK, one difference are the added zenerdiodes, but how could this be a problem? How can clamping diodes cause ringing?
I have never seen ringing at the gates. Is it difficult to measure this effect? does this effect occure only under special conditions?
Do you have further informations about this manner?
Back when I was beginning to experiment with USMPS circuits, I blew over a hundred MOSFETs because I determined that I would not simply reproduce other people's work. I wanted to start with no preconceptions and no ideas of what was possible or not. I was able to see problems and discover why each was occurring. I then added research as needed when progress became too slow. I just threw in that story; it is not meant to be disparaging of the more classic approach to leaning, but to just indicate how I like to do things.
So several years ago, I decided to find out what peoples' experiences were with MOSFET failures when trying to solve my MOSFET-blowing problems. The problem with zener diodes was one of the things I read about. Also, I have other instances where MOSFETs were blowing. Once was a linear power supply circuit I built and another was a computer monitor which kept blowing its power supply MOSFET after a while--like your case it seems. Unfortunately, I did not have the opportunity in either case to solve the problem. However, in each case, adding zener diodes across the gates did not help.
One other failure mode I discovered is due to excessive dv/dt on the body diode of the MOSFET. Back when I had that problem, instead of using a new design, I placed a resistor in series with the primary of the transformer. In your case, you could place one in series with each primary leg, or try it in series with the center tap and the + power source.
However, that dv/dt failure problem was on a half-bridge circuit, not push-pull, which may not matter. You may have some other options to address the problem, too. You may be able to redo the transformer with more turns to slow down the switching transients. Then, you can separate your drive circuit so that the gate turn-on goes through a 100ohm resistor while the turn-off goes through a diode junction.
Really, the dv/dt problem is rather a type of shoot-through. So your suspicion may be pretty close.
So several years ago, I decided to find out what peoples' experiences were with MOSFET failures when trying to solve my MOSFET-blowing problems. The problem with zener diodes was one of the things I read about. Also, I have other instances where MOSFETs were blowing. Once was a linear power supply circuit I built and another was a computer monitor which kept blowing its power supply MOSFET after a while--like your case it seems. Unfortunately, I did not have the opportunity in either case to solve the problem. However, in each case, adding zener diodes across the gates did not help.
One other failure mode I discovered is due to excessive dv/dt on the body diode of the MOSFET. Back when I had that problem, instead of using a new design, I placed a resistor in series with the primary of the transformer. In your case, you could place one in series with each primary leg, or try it in series with the center tap and the + power source.
However, that dv/dt failure problem was on a half-bridge circuit, not push-pull, which may not matter. You may have some other options to address the problem, too. You may be able to redo the transformer with more turns to slow down the switching transients. Then, you can separate your drive circuit so that the gate turn-on goes through a 100ohm resistor while the turn-off goes through a diode junction.
Really, the dv/dt problem is rather a type of shoot-through. So your suspicion may be pretty close.
Something else came to me with regard to dv/dt problems. I mentioned the body diode playing a role, which is with regard to its reverse recovery time. But I recall reading that too much dv/dt on the drain of a MOSFET even with its gate held low can turn it on. The reason is that the parasitic inductance inside the MOSFET impedes the connection of the MOSFET junctions to the external circuit. A very fast transient on the drain can couple to the gate through the intrinsic drain-gate capacitance. But, I must admit, I am not sure how destructive the problem can be with the push-pull topology since the MOSFETs are buffered from each other by means of the primary winding.
As a good measure for reliability, I recommend winding the primary of the transformer with as many turns as possible that will still permit the full amount of power needed. When needing only a little over 30watts from of a 36v power source, the primary can probably be something like 24ga wire, too.
You may be able to consider just increasing the gate resistors to see if that reduces the rise times enough to prevent parasitic gate turn-on if some extra power dissipation in the MOSFETs is OK. Maybe that is all you really need to do.
As a good measure for reliability, I recommend winding the primary of the transformer with as many turns as possible that will still permit the full amount of power needed. When needing only a little over 30watts from of a 36v power source, the primary can probably be something like 24ga wire, too.
You may be able to consider just increasing the gate resistors to see if that reduces the rise times enough to prevent parasitic gate turn-on if some extra power dissipation in the MOSFETs is OK. Maybe that is all you really need to do.
Shoot-through. Your Ciss is over 3kpF at 12V, almost double what a standard IRFZ44N would be.
Why such a high voltage FET? Use the lowest voltage FET you can for the application or add speed-up circuitry (totem pole) to the outputs of the 3525. Watch your dead time and send a big load dump to the input for a few dozen milliseconds. I'll bet the FETs pop like a toy cap gun.
Why such a high voltage FET? Use the lowest voltage FET you can for the application or add speed-up circuitry (totem pole) to the outputs of the 3525. Watch your dead time and send a big load dump to the input for a few dozen milliseconds. I'll bet the FETs pop like a toy cap gun.
I found the solution of my problem.
The toroid transformer caused the destruction of the FETs.
For along time i assumed that there is no thermal problem.
I tested with open housing and heated the heatsink up to
150°C without any effect.
Then i heated only the transformer and i was suprised.
The FETs get destroyed!
Increasing the toroid core temperatur to 105°C caused a high
current in the FETs because the core gets saturated.
I used an EPCOS core with 34mm diameter. I don't know what
material. I changed the switching frequency from 70kHz to
140kHz. Now i can heat up the core to 125°C until i measure
a higher current in the FETs.
I tried another core from Philips, same size, same inductance.
I heated up this core to 200°C with no negative effect.
So i will call the supplier of my transformers.
Up to now, i measured with an open housing. So the core never
reached a high temperatur.
I found out, that the power-supplies sometimes work in an ambient temperatur of more than 60°C. So i don't wonder why
the core temperatur can rise above 105°C.
Thank you all for your help.
The toroid transformer caused the destruction of the FETs.
For along time i assumed that there is no thermal problem.
I tested with open housing and heated the heatsink up to
150°C without any effect.
Then i heated only the transformer and i was suprised.
The FETs get destroyed!
Increasing the toroid core temperatur to 105°C caused a high
current in the FETs because the core gets saturated.
I used an EPCOS core with 34mm diameter. I don't know what
material. I changed the switching frequency from 70kHz to
140kHz. Now i can heat up the core to 125°C until i measure
a higher current in the FETs.
I tried another core from Philips, same size, same inductance.
I heated up this core to 200°C with no negative effect.
So i will call the supplier of my transformers.
Up to now, i measured with an open housing. So the core never
reached a high temperatur.
I found out, that the power-supplies sometimes work in an ambient temperatur of more than 60°C. So i don't wonder why
the core temperatur can rise above 105°C.
Thank you all for your help.
Are you sure you found your problem???
If this is truly Peak Current Mode....being in Sat wouldn't blow the FET.... There are plenty of designs that put the core into Sat for valid reasons and run just fine....
I was starting to think that you may need to increase the amount of SLOPE COMPENSATION you present to the current ramp....
The ramp rate of the current sense would be very steep when in saturation, therefore increasing the loop gain, thus instability and pop!!!
Chris
If this is truly Peak Current Mode....being in Sat wouldn't blow the FET.... There are plenty of designs that put the core into Sat for valid reasons and run just fine....
I was starting to think that you may need to increase the amount of SLOPE COMPENSATION you present to the current ramp....
The ramp rate of the current sense would be very steep when in saturation, therefore increasing the loop gain, thus instability and pop!!!
Chris
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