Capacitor (filter) phase question (pic attached)

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Hi Eva - thanks for the reply - I am keen to see this for myself - I might yet be converted !

I propose to set up a CMOS 555 astable with supply-rail decoupling consisting of paralleled caps of 22u and 100n ceramic. I will try initially without any other load on the supply, but might add a cmos gate or two, perhaps with some capacitive loading on the outputs, which would count as severe provocation. I will use birds-nest construction (no board). You have not said what freq the 555 goes at, but I imagine 10kHz might be ok.

Do you think this is the right approach ? Would you like to predict what I will see ?

I should say this is all a lot more severe than what I originally had in mind - I thought we were talking about decoupling audio amps, and what I am now describing is hardly that. I expect that your point is that this refers to smps. Does the ringing you have seen compromise the performance of the psu ? Is it measurable in the amp to which the psu is connected ?

Anyway, I shall let you know what I find. The real point is whether electrolytics can form an oscillatory circuit with a ceramic at this freq, and if you have actually seen it happen it is possible that I will also.

Bye for now
 
My circuit had a CMOS 555 producing a 120Hz clock. Among other things, that clock was feeding one of the gates of a CD4013 flip-flop configured to invert its output on each clock falling edge. The outputs of that CD4013 were driving more NOR and NAND gates, four of which had their outputs loaded with 220pF and toggled in each clock cycle (actually the capacitors are in series with RC networks, in such a way that two of them only appear as a load for the negative going transients while the other two load the positive going transients).

The circuit was somewhat more complex than that, but these were the major sources of supply rail current glitches.

I recommend you playing with capacitor lead length in your tests, as this is a critical parameter. Sometimes, the only way to tame the ringing is to solder both capacitors together just where the legs come out of the case (not practical), as any lead length or PCB track length will cause the ringing to appear or to increase.

Also, when there is some lead length, you will obtain different results depending on the exact measurement point (demonstrating that there is enough current flowing between one capacitor and the other to cause measurable voltage drop in the leads).
 
Hi Eva - thanks for your latest. I have had my soldering iron out and have done some tests. Interestingly I have included the points you make although I have only just read your posting. I expect you will find my experiments cover them.

Click here for the latest ; the overall conclusion is a diplomatic miracle.... (for me).

http://g4oep.atspace.com/caps/supposed_oscillatory_response_of.htm

I have noticed that some people in remote parts of the world have difficulty accessing atspace.com. I can move the page to another server if necessary....
 
g4oep said:


I propose to set up a CMOS 555 astable with supply-rail decoupling consisting of paralleled caps of 22u and 100n ceramic. I will try initially without any other load on the supply, but might add a cmos gate or two,

I think 555-timer is the key to ringing in here. Its famous for draving high peaks from supply because of some sort of cross-conduction inside the chip. Behaviour may wary depending on make and model of 555.

AC-series logic circuits would be also good canditate to drive supply nuts. Try something like 74AC08 all outputs paralleid and you should have plenty of current and 2ns risetimes.
 
We are using CMOS 555 timers whose datasheet claims that the peak current is two orders of magnitude lower than for the classic bipolar 555.

See the datasheet for ICM7555.

Anyway, a conventional 555 would be an even better source of excitation for any possible PSU resonance :D
 
Hi all - I was so pleased with my result (although I proved myself wrong) that I beefed up the web-page and publicised it on another forum which I visit, so the page might have changed since you last saw it.

http://g4oep.atspace.com/caps/caps.htm

The low-esr + ceramic combination reduces the amplitude of the transient by 1/3 compared with the ordinary 22uF cap, so it is not clear that this is a bad thing despite the ringing. You can choose !

I expect that the ringing can be further damped by adding a small resistor in series with either cap, but the point of that seems marginal, since the net impedance (and therefore the amplitude of the transient ) will go up again. Where have I seen references to 'snubbers' - on this site ?

The 555 I used was actually not a CMOS type. It is an ordinary NE555N - it was what was on the existing board when I picked it up. I assume that the transient is caused by the discharge of the timing cap, but I might be wrong.

Cheers - Andy
 
Then you are wrong and me too :D

The good old NE555 draws 400mA peaks during output transients (may be in only one of the transients as you state). The IC design is quite ancient, I suppose that it achieves its very fast rise and fall times at the output pin by hard-switching over the other half of the totem-pole that has not stopped conducting yet, thus cross-conducting for a hundred nanoseconds.

I never thought that we could build a nice capacitor combination tester around a simple NE555.

Note that not all capacitors are fully high-ESR or fully low-ESR, and also your 100nF ceramic disk might be less prone to ringing that my multilayer one.
 
Eva, g4oep,
in the light of your experiments what do you think would happen when using two low-esr capacitors of half value (but same type) in parallel rather one low-esr of twice the value.
i.e. use two 10-11uf caps of the same type(to make sure esr, inductance, etc..remains same) in parrallel, intead of one 22uf of the same type.

I am curious to know what be the behaviour (better or worse) of the ringing in this case ?
 
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