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Old 26th February 2006, 05:16 PM   #1
zilog is offline zilog  Sweden
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Default current mode push-pull smps, how to design sense transformers?

I am trying to design a current mode controlled SMPS to transform 12V from a car battery to +-45V at a maximum approx 400W power. To accomodate the current sensing, I want to use sensing transformers in the primary side. My concern is how to design the current sensing while avoiding walking the sense transformers into saturation, is this done properly in my attached drawing? Is there any other, better way of doing this?

Second, how will this control scheme work when I have no load attached, this is a scenario that might happen.
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Old 26th February 2006, 05:37 PM   #2
testlab is offline testlab  United States
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For DC, you can use a LEM hall effect current sense device.

http://www.lem.com/

You have to make a signal conditioning circuit for it, but that is not terribly difficult. In this current range, these devices are not that expensive.

The other way to do it, is to pick the current feedback signal off of the current sense/source resistor of the main switching fet. There should be a pin on the controller chip that this signal ties to.
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Old 26th February 2006, 05:51 PM   #3
zilog is offline zilog  Sweden
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Quote:
Originally posted by testlab
The other way to do it, is to pick the current feedback signal off of the current sense/source resistor of the main switching fet. There should be a pin on the controller chip that this signal ties to. [/B]
I dont want to use sense resistors because of the high currents involved, second this design will be based on surplus IRF540:s with no sense outputs along with my surplus magnetic cores, so I think current transformers are my only option (obtaining anything from the other side of the ocean is out of my price range, I prefer to learn the proper way with transformers instead)
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Old 26th February 2006, 06:06 PM   #4
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Then what you are going to have to do, is run a wire in series with each of the fet's, through the transformer. This is your primary. The secondary of the transformer then needs to have a small load resistance, about 100 ohms or so. The signal then has to be FWB rectified and filtered. The resulting DC signal is sent into an opamp, where the gain is scaled, to accomodate the input range of the current feedback pin of your controller.

You will also probably need to have an output voltage feedback signal, isolated by an opto-coupler.

I just went through design like this at work. It can be very touchy.
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Old 26th February 2006, 06:13 PM   #5
zilog is offline zilog  Sweden
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Originally posted by testlab
Then what you are going to have to do, is run a wire in series with each of the fet's, through the transformer. This is your primary. The secondary of the transformer then needs to have a small load resistance, about 100 ohms or so. The signal then has to be FWB rectified and filtered. The resulting DC signal is sent into an opamp, where the gain is scaled, to accomodate the input range of the current feedback pin of your controller.

You will also probably need to have an output voltage feedback signal, isolated by an opto-coupler.

I just went through design like this at work. It can be very touchy.

Yeah thats pretty much the design I have in mind. What does FWB rectification mean?
Do you use one sense transformer per FET leg as in my attached schematic or do you let them share one? How do you reset the flux in the sense transformers?
I assume the transformers will reset themselves through the Rs resistor across the secondary, but I would really like to avoid having them before the diode to get rid of the diode voltage drop.

Do you have any experience regarding how many mF the capacitors on the secondary side can become without running into strange problems with feedback? I want as large as possible to avoid PSU bus pumping when feeding a switchmode amplifier.
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Old 26th February 2006, 06:30 PM   #6
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FWB=full wave bridge. This is for making a DC control signal that has a range of 0-4 volts.

As for the output capacitance, it is really going to depend on the amount of inrush current the primary can tolerate, You can put in an inrush current limiter of some kind.

Try looking through here for more ideas http://focus.ti.com/analog/docs/tech...tion=app_notes

. Most of these ideas are for the ex-Unitrode chips that are used extensively in aerospace. Look at the National Semiconductor and Linear Technology websites as well. Linear Tech has an excellent circuit designer program available for $0.
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Old 26th February 2006, 07:04 PM   #7
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Your schematic shows the current sense transformers connected in the right way.

The key for a current sense to work properly is to avoid saturation even in worst case conditions. Saturation is caused by a too high volts*pulse_time/turns product like in any other transformer, so optimum performance is achieved by choosing the right amount of secondary turns and the proper load resistance depending on the primary currents involved. In other words, excessive secondary voltage during too much time is what causes saturation. The following formula allows to calculate the magnetic flux excursion in the transformer produced by a pulse:

B = (V/N) * T / S

Where B is flux in Teslas, T is pulse time is in seconds, S is core cross-sectional area in square meters, V is secondary voltage and N is secondary turn count.

Assuming a single primary turn, secondary voltage V in your circuit would be 0.7V (diode drop) plus (I_primary/N)*R_load. So we can substitute in the previous formula:

B = (0.7+(I/N)*R)/N * T / S

You have to estimate suitable B, I, T and S worst-case values first. Then you can just play with R and N since both are closely related.


Concerning output-filter capacitors, the value by itself DOES NOT MATTER AT ALL, as it has to be considered in conjunction with inductor parameters. You have to design a second-order output filter, modelling inductor value and its DC resistance, and also capacitor value and its ESR. The filter should produce as little peaking as possible (<6dB) and should have a low enough cutoff frequency so that the response is down by 40dB or so at the switching frequency.

Finally, frequency compensation for voltage mode control is achieved by adding a zero to the error amplifier around the frequency where the output filter has its first pole. Your SMPS will oscillate randomly and will show clumsy transient response if you don't follow that design procedure. The maximum gain value allowed above the zero has to be found empirically.
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Old 26th February 2006, 08:04 PM   #8
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Hi,

sometimes a little different configuration is used for the current sense transformer. The idea is to saturate transformer in reverse direction, so when needed, double flux density can be used. See atached schematic. Second, when calculating volt second product, do not forget to add voltage drop of the secondary winding resistance. It is not insignificant due to the thin wire used (typically 0.1-0.15mm magnet wire).

Best regards,

Jaka Racman
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Old 26th February 2006, 08:54 PM   #9
Eva is offline Eva  Spain
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Among other things, the following thread shows an interesting current-sense transformer connection involving cascode transistors, whose purpose is to force the secondary to operate at 0.7 Volts despite the current level. The result is a dramatical reduction of current-transformer size while improving precision and signal to noise ratio.

http://www.diyaudio.com/forums/showt...490#post730490
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Old 26th February 2006, 10:12 PM   #10
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Hi Eva,

i looked at at the thread but could not find particular schematic. I guess it must be something like this? I have completly forgot it, it must be 20 years since I last used it. Works quite well, since it allows easy ramp compensation for peak mode control. I first saw it in an article by S. Cuk.

Best regards,

Jaka Racman
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