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PSU capacitor selection in smps fed half-bridge class d amplifier
PSU capacitor selection in smps fed half-bridge class d amplifier
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Old 16th March 2006, 12:44 AM   #31
Eva is offline Eva  Spain
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You will have a hard time injecting a step big enough into a PSU capacitor bank (such a simple circuit must have some pitfalls). Ttransformer leakage inductance will ensure limited current slopes, since in such a circuit the voltage applied to the leakage inductance in order to energize it is equal to the amount of voltage unbalance betweem rails.
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Old 16th March 2006, 07:38 AM   #32
zilog is offline zilog  Sweden
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Thanks Eva,

You dont have any nice way of synchronizing the balancer to the primary smps switcher, I am thinking about using a clock chip to generate clock for both primary side switchers for the current mode control aswell as for the balancer (controlled by some PLD stuff that generates 45%+45% waveforms) and drives the balancer using transformers.

I could have used I synchronous rectivier driver, but I want the balancer to switch even if there is no primary side switcher activity.
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Old 26th July 2008, 08:06 AM   #33
gustep12 is offline gustep12  United States
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Default Good explanation of Class D bus pumping!!

Originally posted by subwo1
I guess I'll throw in a thought. The main pumping mechanism in a class D amp would occur when a power supply rail passes enough net current through the output filter inductor for a sufficient length of time.

When a MOSFET turns off, the voltage on the inductor flies back to the opposing power rail momentarily adding charge to its filter capacitor either through the body diode if the MOSFET there has not turned on yet, or through the channel if it has already turned on. If the net voltage at the output load is zero, the cycle-by-cycle voltage increases on the power supply filter capacitors keep transferring back and forth evenly, with neither capacitor building up extra net voltage. Net current passing through output inductor for any appreciable length of time will pump up one of the power supply rails, the greater the current, the greater the pump-up. For this reason, DC output voltage offset into a low resistance produces the serious pumping.

Hello SubWo1,

Your explanation is the best I have found after searching the web for a whole day on the issue of class D bus pumping and how it affects half-bridge stages more than full bridge stages. You explain it!

The reason why bus pumping is difficult to understand is because we fail to look at the switching frequency. It's the switching frequency that causes the pumping when near-DC currents are to be generated by the stage.

For example, imagine trying to get a positive DC current out of your class D amp. A real positive DC current would not cause any apparent problems. But in reality, it's going to be pulsed, not DC: positive curent, no current, positive current, etc. And for every pulse of the class D stage, a flyback current gets pushed back into the system. For half-bridge, this flyback current charges up the negative rail capacitor, which eventually reaches overvoltage. For full-bridge, this flyback current goes back into the one and only capacitor which is providing power to the stage, so it won't reach overvoltage.

So a full bridge class D could, in theory, provide a DC current, but a half bridge class D would soon exceed the safe bus voltage on that rail which is not utilized, but which receives all the flyback energy.

Finally a complete explanation!

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Old 26th July 2008, 09:57 AM   #34
Electrone is offline Electrone  United States
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Hi Gustep12,

Thanks for expressing your appreciation!
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Old 7th June 2010, 02:50 PM   #35
Workhorse is offline Workhorse
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Use of coupled inductors in the rails will reduce the pumping effect to much less.
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