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Old 31st July 2005, 04:03 PM   #11
Danko is offline Danko  Hungary
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I think, I solved the PSU-oscillating-problem. I connected the primary side, and the sedondary side GND with a 100nF capacitor paralelled with 1MOhm resistor. After this sometimes the PSU oscillated, but I soldered some capacitors near the TL431.

Eva: Thanks a lot! I will do some calculations about the surrent-sense resistor.
I decreased the frequency about half of 280kHz. How did you calculate the current ripple in the output inductor?
Why is required the slope compensation in push-pull topology? I read, that slope-compensation is required only when the duty-cycle is higher (or will be...) higher than 50%. But in push-pull applications, the duty-cycle can be maximum 50%, becouse of the simmetry. If we take into consideration the dead-time, then the max. duty-cycle can be about 45-47%.
Why is there a slope-compensation in the original schematic?


Regarding the current-sense resistor ....
So, I have to calculate the values, to get about 700mV on the CS pin at maximum output power?
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Old 31st July 2005, 07:00 PM   #12
Eva is offline Eva  Spain
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Quote:
Originally posted by Danko
I think, I solved the PSU-oscillating-problem. I connected the primary side, and the sedondary side GND with a 100nF capacitor paralelled with 1MOhm resistor. After this sometimes the PSU oscillated, but I soldered some capacitors near the TL431.
This capacitor, placed directly across transformer pins, definitely reduces common mode EMI, but usual values are somewhat smaller than 100nF. Most off-line SMPS units use a 4.7nF 2KV capacitor and it's enough to force common-mode current due to switching transients and primary-secondary capacitance to flow back through the capacitor.


Quote:
Originally posted by Danko
Eva: Thanks a lot! I will do some calculations about the surrent-sense resistor.
I decreased the frequency about half of 280kHz. How did you calculate the current ripple in the output inductor?
When you apply a constant voltage 'V' to a inductor of 'L' henries during a time of 't' seconds you get a linear current ramp whose slope in volts/second is V/L. Multiply that slope by the time it lasts and you'll get peak to peak current ripple.

For example :
V = Vreflected-Vout-Vdiode = 125-54-1 = 70V
L = 320uH
duty_cycle= (Vout+Vdiode)/Vreflected = (55+1)/125 = 44%
osc_freq=280Khz
t = duty_cycle/osc_freq = .44/280,000 = 1.57uS
Iripple= 70V * 1.57uS / 320uH = 0.34A p-p

The inductor dicharge period may be also used:
V = Vout+Vdiode = 54+1 = 55V
L = 320uH
duty_cycle=44% so discharge time is 56%
osc_freq=280Khz
t = .56/280,000 = 2us
Iripple= 55V * 2uS / 320uH = 0.34A p-p

An usual rule of thumb is to allow current ripple to be up to 20% of the maximum output current, so you may decrease the operating frequency if you transformer allows for it. Note that 140/280Khz are insane frequencies from the switching-losses point of view and that your transformer may allow even 40/80Hz operation.


Quote:
Originally posted by Danko
Why is required the slope compensation in push-pull topology? I read, that slope-compensation is required only when the duty-cycle is higher (or will be...) higher than 50%. But in push-pull applications, the duty-cycle can be maximum 50%, becouse of the simmetry. If we take into consideration the dead-time, then the max. duty-cycle can be about 45-47%.
Why is there a slope-compensation in the original schematic?
As seen from the current-mode control loop point of view, the transformer and the push-pull action does not exist at all and operating frequency is Fosc instead of Fosc/2, so duty cycles in push pull may also approach 100%. That's why slope compensation is also required.

But note that you are using a 15:6 transformer to get only 50V output from 50V input and this means that steady state duty cycle may hardly reach 50%, so slope compensation may not be required in these circumstances. However, this 15:6 ratio also means that current flowing through the primary side is more than twice the sum of output currents and this fact is going to hurt efficiency very badly. I would use a lower ratio like 6:8 or 6:10 instead, even at the expense of having to mess with slope compensation.


Quote:
Originally posted by Danko
Regarding the current-sense resistor ....
So, I have to calculate the values, to get about 700mV on the CS pin at maximum output power?
Right, but the datasheet recommends a 0 to 500mV range for normal operation, so I would design for 500mV instead.
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Old 4th August 2005, 08:53 PM   #13
Danko is offline Danko  Hungary
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Thank you, Eva!


If I know the I_rippe, how can I calculate the Voltage_ripple?
U_ripple = outputcapacitor's-ESR * I_ripple?


This is the new layout:
http://sziget.mine.nu/~danko/aramkor/Screenshot-181.jpg
The box with green lines is the toroid output choke. Are the trafo and the output choke on good position? Or will they interfere each other's magnetic field?

If I don't need slope compensation, then can I omit the T1 transistor from the CIRCUIT ?

Why is bad, if I put 100nF instead of the 4.7nF/2kV capacitor?


Thanks in advance!
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Old 5th August 2005, 01:32 AM   #14
Eva is offline Eva  Spain
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Quote:
Originally posted by Danko
Thank you, Eva!

If I know the I_rippe, how can I calculate the Voltage_ripple?
U_ripple = outputcapacitor's-ESR * I_ripple?
This is not so simple. Use your favorite circuit simulator to check how capacitor voltage waveform looks when a current triangle wave with the same parameters as the inductor ripple current is flowing through them. Remember to model output capacitors with some ESR and maybe a slightly bit of ESL in series.


Quote:
Originally posted by Danko

This is the new layout:
http://sziget.mine.nu/~danko/aramkor/Screenshot-181.jpg
The box with green lines is the toroid output choke. Are the trafo and the output choke on good position? Or will they interfere each
other's magnetic field?
Both an ungapped transformer and a toroid inducor are not going to generate strong stray magnetic fields. Also, they are hardly going to intererfere between them. Anyway, the inductor is conveniently placed away from the control circuit (this is usually more critical).


Quote:
Originally posted by Danko

If I don't need slope compensation, then can I omit the T1 transistor from the CIRCUIT ?
With your 6+6:15+15 turn ratio slope compensation is hardly required, altough there are a lot of reasons to use it anyway. I recommend reading that paper carefully:

http://www.powerdesigners.com/InfoWe...rchive/u97.pdf

Furthermore, being able to use duty cycles above 50% will allow for a more performance-wise primary to secondary turn ratio in the transformer, thus reducing primary side currents by approx. 40%, and reducing both inductor current ripple and output voltage ripple due to the increased duty cycle.


Quote:
Originally posted by Danko

Why is bad, if I put 100nF instead of the 4.7nF/2kV capacitor?

Thanks in advance!
It causes much more AC leakage between primary and secondary than required and hurts isolation, otherwise it's fine.
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Old 26th August 2005, 09:36 PM   #15
Danko is offline Danko  Hungary
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Finally!! My SMPS is working /almost)/ perfect!!

I put an amplifier at the output of my SMPS, and there's no noise on the amp's output :-))

How "flat" should the ouput of the SMPS have to be? The output is 2x40V, and there are small spikes, about 200mV "high". Is it OK?
Could someone take a photo of a home-made SMPS's output?
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Old 22nd September 2005, 02:22 AM   #16
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Danko:
I'm glad to hear your SMPS is working well now.
I just have a personal comment, for what it's worth, on your PCB layout.

Why are the copper lands on the MOSFET Drains so large? They are much larger than current capacity would dictate them to be (about 5 mm).

"Noisy" nodes should never be given large copper areas, and this is the noisiest node in the circuit. The MOSFET Source, lifted above ground by the current sense R, is also not the quietest node around either. I would expect these two nodes to be small, short traces, well covered with ground plane on the top layer (which is conspicuously absent in your layout). I frankly don't like 2-sided PCB's for such simple circuits, because of the extra work, but if I must use double sided, then it's imperative that I paint ground plane everywhere I can. The main reason to use 2-sided in SMPS is NOT to make it easier to route your wires. It's to provide ground plane.

I see you have shortened your gate drive nodes from a previous layout--that stood out like a sore thumb initially. Wise move.

Adrian
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