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Old 9th April 2005, 06:53 PM   #11
AndrewT is offline AndrewT  Scotland
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Hi,
How could you incorporate a current limit into the PSU?
Even better if this was foldback?
Could you explain, in detail, the function of C7, it appears to be passing output ripple straight back to LTP. I've seen this in other circuits. What specs determine it's effectiveness?
Why take the CCS to the opposite Vrail? Could they be returned to ground instead?
What is the RC time constant for c5? R1//R2 *C5 or other?
Have you simulated reduced values for C1&2? What happens?
Why do I want current limit;- to avoid catastrophic failure downstream and also to slow charge downstream capacitance. I'm still thinking ClassA.
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Old 9th April 2005, 08:58 PM   #12
Mr Evil is offline Mr Evil  United Kingdom
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Quote:
Originally posted by Dark Harroth

Somehow I feel that a JFET would be better, but the only ones that can handle such a high voltage are Soviet-made (and these ones have to be properly matched, because their parameters can differ from each other for more than 20%).
So I have an another question (a stupid one I should say), can I put three JFET CCS in series to obtain a 150-volt limit?
If not, what resistor should I use for +/- 60 Volts as a replacement, a 60/0.0053=11,5K one?
AndrewT's post quoted below reminded me of something I should have mentioned before: You could connect the CCS to ground instead of the opposite rail. This is how I originally had it in the first prototype I tested, but I changed it for smoother turn-on*. This reduces the voltage requirements to only half the input voltage, bringing it back within the realm of commonly available parts.

None of the components in this circuit need to be matched, nor do the current sources need to be tightly specified or matched. Anything between, say, 1-10mA will suffice.

You could connect multiple FETs in series, but there would need to be some arrangement to ensure equal voltage sharing, which wouldn't be worth it.

For just a resistor, the value would be 90/0.0053 = 17K, since the voltage across it is one rail plus the voltage across R2, which is 60/2 (minus a couple of volts of Vgs of the MOSFETs).

*With CCS to ground, the LTP stays off until C5 is charged to a couple of volts, then it turns on suddenly, bringing the output up to a couple of volts at the same time. With the CCS to the opposite rail, the LTP turns on before C5 has charged significantly, resulting in a smooth ramp up of output voltage from 0 to fully on. It's not a big deal really, so no great loss if it's more practical to connect the CCS to ground.



Quote:
Originally posted by AndrewT
...How could you incorporate a current limit into the PSU?
Even better if this was foldback?..
I suppose the simplest method would be to place a small resistor in series with the source of the pass MOSFET, then sense the voltage across it with a transistor that shorts the top of R8 to the input. I've attached a schematic of how that would look. It would give just normal current limiting. I'm not familiar with how to implement foldback limiting, so I can't help you there.


Quote:
Originally posted by AndrewT
...Could you explain, in detail, the function of C7, it appears to be passing output ripple straight back to LTP. I've seen this in other circuits. What specs determine it's effectiveness?
It does indeed feed ripple back into the LTP, into the inverting input, i.e. negative feedback. This reduces the AC gain, thus reducing the ripple. It needs to be large enough to start rolling off the gain well below the ripple frequency (100 or 120Hz). With the given component values it is ~7Hz. Larger values will improve ripple slightly, but more than 100n gives severely diminishing returns. Type of capacitor is not critical.



Quote:
Originally posted by AndrewT
...What is the RC time constant for c5? R1//R2 *C5 or other?..
R1||R2 *C5 is 235ms, or a corner frequency of 4.3Hz. It is the voltage here that controls the output voltage, so obviously the higher the time constant the better the output ripple, but too high can cause it to take too long to turn on. These component values are the main contributors to overall performance.



Quote:
Originally posted by AndrewT
...Have you simulated reduced values for C1&2?..
I have done sims with other values of reservoir capacitor. The ripple at the output is directly proportional to the ripple here. Smaller values give more ripple. More ripple means the dropout voltage must be set higher, which reduces efficiency. Choose whatever value gives the performance you want at the required output current.


Quote:
Originally posted by AndrewT
...Why do I want current limit;- to avoid catastrophic failure downstream and also to slow charge downstream capacitance. I'm still thinking ClassA.
Ahhh. You don't need to worry about slow charging because capacitance multiplers give an inherently slow turn-on due to time constant R1||R2 *C5. You can easily have it take several seconds to approach full output voltage by increasing C5.
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Old 9th April 2005, 09:27 PM   #13
jleaman is offline jleaman  Belgium
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I like it. : O ) Got any board's ? or the pcb files ?
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Old 10th April 2005, 10:24 AM   #14
AndrewT is offline AndrewT  Scotland
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Thanks Mr Evil, that was indeed a detailed reply.
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Old 10th April 2005, 10:36 AM   #15
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Quote:
Originally posted by jleaman
I like it. : O ) Got any board's ? or the pcb files ?
See the first post (link #3). There is an image of how the board should look like.

Right now I'm planning to convert (redraw) the board image to sPrint-Layout 4 format; if you or someone else needs it, I can upload it in a couple of days here.
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Old 4th March 2013, 02:13 PM   #16
nickds1 is offline nickds1  England
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A thread back-from-the-dead !

How does this capacitor multiplier improve over the traditional one using a darlington, e.g. using 47R and 10,000uF & a TIP121, you get an effective capacitance of 10F but with a drop-out of up to 4V - its also very cheap to do.

Your version may be LDO, but what ripple rejection do you get?

Thanks
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Old 5th March 2013, 04:57 PM   #17
Mr Evil is offline Mr Evil  United Kingdom
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Quote:
Originally Posted by nickds1 View Post
A thread back-from-the-dead !

How does this capacitor multiplier improve over the traditional one using a darlington, e.g. using 47R and 10,000uF & a TIP121, you get an effective capacitance of 10F but with a drop-out of up to 4V - its also very cheap to do.

Your version may be LDO, but what ripple rejection do you get?

Thanks
I don't remember the actual ripple rejection for this circuit, but it does have better ripple rejection than the normal darlington version, due to the FET's high input impedance. Alternatively, the ripple rejection can be traded for smaller C instead (which is what I did).

The Darlington version is certainly cheaper, but on the other hand the LDO version can get away with lower power pass devices, and a lower voltage transformer or smaller reservoir capacitors.

PS. I'm still using this very PSU, and have heard from a couple of people who have successfully built their own versions.
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Old 10th July 2013, 11:16 PM   #18
PMI is offline PMI  United States
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After much delay, my version of the Improved Capacitance Multiplier. I am basically at the prototype stage, and hope to have a working version in a couple days.

Layout is complete, pics below are 3D-renderings, and circuit boards are almost in my hands.

My goal is to adapt this design for use with my through-hole version of Shaan's simplified VSSA (aka PeeCeeBee),

PeeCeeBee

as well as the original set of VSSA modules I have received from LazyCat's Group Buy offer.

The circuit is essentially the same one presented by MrEvil, only exception is that the jfets have been connected to ground, and not to the opposite rail, to make use of more commonly available parts.

My goals are to achieve controlled turn-on, low-ish dropout voltage, and moderate cost, with much lower noise and ripple than what can be expected from a pure rectifier/filter.

Oh, and last but not least,
@ Miles, a big Thank You (nanos gigantum humeris insidentes)
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File Type: jpg VSSA_PSU4_layout.jpg (261.9 KB, 1439 views)
File Type: jpg VSSA_PSU4_1.jpg (128.3 KB, 1381 views)
File Type: jpg VSSA_PSU4_2.jpg (115.0 KB, 1350 views)
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Old 11th July 2013, 07:48 AM   #19
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To continue discussion : in single layer way and to take care on short tracks from diode Gnd near DC+ and DC- could be share from AC2 and AC3 so that gnd tracks could be stopped and this point and than you have free space for diode to caps on same layer. Do you see an issue? Each Diode could be turn 90 so that you could shorten tracks from diode to diode...

Marc
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Old 11th July 2013, 10:42 AM   #20
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Quote:
Originally Posted by PMI View Post
After much delay, my version of the Improved Capacitance Multiplier. I am basically at the prototype stage, and hope to have a working version in a couple days.

Layout is complete, pics below are 3D-renderings, and circuit boards are almost in my hands.

My goal is to adapt this design for use with my through-hole version of Shaan's simplified VSSA (aka PeeCeeBee),

PeeCeeBee

as well as the original set of VSSA modules I have received from LazyCat's Group Buy offer.

The circuit is essentially the same one presented by MrEvil, only exception is that the jfets have been connected to ground, and not to the opposite rail, to make use of more commonly available parts.

My goals are to achieve controlled turn-on, low-ish dropout voltage, and moderate cost, with much lower noise and ripple than what can be expected from a pure rectifier/filter.

Oh, and last but not least,
@ Miles, a big Thank You (nanos gigantum humeris insidentes)
Big thanks to both circuit designer and to pcb designer for this useful PSU! I am really surprised that this low dropout capacitance multiplier is not more used by diy-ers. It is versatile PSU, I intend to use it for all my diy amps up to 40V rails, not just for those that have lower PSRR.

I am not competent enough to comment pcb but if Marc has some idea how to make it single layer (for those builders who want to etch their own pcbs), why not?

Last edited by ivanlukic; 11th July 2013 at 10:44 AM. Reason: correction
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