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Old 16th January 2018, 09:23 AM   #111
Rod Coleman is online now Rod Coleman  United Kingdom
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Quote:
Originally Posted by MarcelvdG View Post
I mean, your 40 to 90 degrees of phase margin is just as arbitrary a criterion as striving for less than 20 % overshoot and no ringing in the small-signal step response.
Designing for a phase margin of 40-90 is not an arbitrary target. Not at all. Ensuring that our loop does not rotate phase by 180 at the crossover is the stability criterion, with 40-90 margin as a realistic target that should usually be achievable, and it is sufficient to account for all the usual variations that affect every circuit made from disparate components.

Perhaps it would be better if I say 'Design and Test for Phase Margin' rather than 'checking for phase margin' because the design portion of the work is at least as important as the testing.

You may choose to test by examining overshoot, but what happens when the result is borderline, or if it fails? Sooner or later you are going to have to consider phase rotation, in order to apply frequency compensation.

I draw attention to this question of phase margin because otherwise, the impression given to would-be circuit designers or constructors is that it's OK to design a composite voltage-regulator and then stabilise it by swapping & adding components until the problem appears to go away. And I am certain that there are always DIYers and other visitors to the site who wish to do better than that - and learn how to design and develop properly.
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Old 16th January 2018, 04:37 PM   #112
Mark Johnson is offline Mark Johnson  United States
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Since the SPICE representation of the circuit is less than 100% accurate, I find that I seldom get exact matching between (simulated phase margin & measured phase margin). By the same token, I seldom get exact matching between (simulated risetime & measured risetime), and also (simulated transient overshoot & measured transient overshoot).

One reason for this is: my estimates (guesses!) of parasitic capacitances on the actual hardware, and installed into SPICE, are not always perfect. Another reason is: SPICE modeling of power MOSFET gm vs Ids, is not always perfect. (Whereas, BJT SPICE modeling of gm vs Ice is generally excellent). A third reason is: the ESR and ESL of real electrolytic capacitors, are not always identical to the SPICE model. A fourth reason is: the discrete compensation capacitor in a "Miller" arrangement, is connected to the same nodes as several semiconductor junctions. The capacitance of these junctions, vs bias voltage and bias current, is not always identical to the SPICE model.

For these and other reasons, I seldom get the exact measurements that I expected from SPICE simulations. So I tinker around with the compensation components, to see whether (a) I'm very close to a Cliff Of Death; (b) I can get the results that SPICE predicted; (c) I can get results better than what SPICE predicted.

As viewed by a disinterested third party, what appears to happen is: (i) bare PCBs arrive; (ii) components are stuffed and soldered; (iii) the board is connected to test equipment and measurements are made; (iv) component values are tweaked and twiddled while more measurements are made; (v) when tweaking and twiddling (during measurements) is complete, the job is done. Exactly what some people recommend NOT doing.
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Old 16th January 2018, 08:40 PM   #113
MarcelvdG is offline MarcelvdG  Netherlands
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Quote:
Originally Posted by Rod Coleman View Post
Designing for a phase margin of 40-90 is not an arbitrary target. Not at all. Ensuring that our loop does not rotate phase by 180 at the crossover is the stability criterion, with 40-90 margin as a realistic target that should usually be achievable, and it is sufficient to account for all the usual variations that affect every circuit made from disparate components.

Perhaps it would be better if I say 'Design and Test for Phase Margin' rather than 'checking for phase margin' because the design portion of the work is at least as important as the testing.

You may choose to test by examining overshoot, but what happens when the result is borderline, or if it fails? Sooner or later you are going to have to consider phase rotation, in order to apply frequency compensation.

I draw attention to this question of phase margin because otherwise, the impression given to would-be circuit designers or constructors is that it's OK to design a composite voltage-regulator and then stabilise it by swapping & adding components until the problem appears to go away. And I am certain that there are always DIYers and other visitors to the site who wish to do better than that - and learn how to design and develop properly.
If you like to use phase margins to establish how close to small-signal instability your circuits are, that's fine with me. It is a good method, especially for simulations and calculations. For measurements it adds some overhead; for example, what impact will the parasitics of your transformer have? Still, if you can keep that under control, that's all fine. If you want to advocate the use of phase margins on this forum, by all means, please go ahead.

However, your repeated use of the word "properly" annoys me in your posts. It implies that Jan, Mooly and I are doing it improperly, which in my opinion is simply not correct. I can assure you I have designed dozens of feedback amplifiers that were produced in millions without ever calculating, simulating or measuring a phase margin and without ever getting a single customer complaint about them.

What I did do is look at small- and large-signal step responses, closed-loop frequency responses and for the more complex cases, root loci and pole-zero extractions. For active filter synthesis I usually just calculate the transfer function without worrying about whether there are any feedback loops in the circuit.

To answer your question, when the overshoot of the small-signal step response is excessive or when you see excessive ringing or even oscillations, you can for example estimate or simulate where the main poles and zeros of the loop gain are, draw a root locus and see from the root locus plot what you can do to reduce the Q of the closed-loop pole pairs. Simulations of the small-signal step response (or of the closed-loop pole locations, when you have a pole-zero extractor) can then show you if the expected improvement also occurs when second-order effects are taken into account, to the extent that the simulation covers these. For cases that occur frequently, like simple second-order systems with a zero, you only have to draw the root locus once in your life, after that you know what the possible ways to reduce the Q are.

Of course all of this is equivalent to increasing the phase margin. That's just the point: there is a whole bunch of methods to analyse feedback loops that are essentially equivalent to each other, and are therefore to my opinion equally proper.

When possible, it is wise to also check recovery from large steps and weird initial conditions once the small-signal step response is OK. That may be difficult in reality, but it's easy to do in simulations.
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Old 16th January 2018, 09:40 PM   #114
Rod Coleman is online now Rod Coleman  United Kingdom
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Quote:
Originally Posted by MarcelvdG View Post

However, your repeated use of the word "properly" annoys me in your posts. It implies that Jan, Mooly and I are doing it improperly, which in my opinion is simply not correct.
Have you posted any circuits for Regulators in this thread? I don't remember seeing any. If not, I can't be suggesting you're presenting any 'improper' design work. The others can speak for themselves, if they are as easily 'annoyed' as you are.

If you are using analysis and measurement using whatever techniques you like, and arriving at solutions where the stability criterion is satisfied - meaning that a suitable phase margin is achieved, then naturally, I have no quarrel with you. If you feel that your methods to achieve this aim are more suitable for the problems of this low-voltage regulator, feel free to advocate them too.
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Old 16th January 2018, 09:52 PM   #115
MarcelvdG is offline MarcelvdG  Netherlands
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No, but I did make some comments on the stability of proposed regulators and suggested that the thread starter should measure the small-signal step response to determine stability. The reason why I suggested using the small-signal step response is a very pragmatic one: he simply doesn't have the equipment to measure phase margin.

Anyway, I'm glad we agree now.
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Old Yesterday, 03:03 PM   #116
MorbidFractal is online now MorbidFractal
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Default Let's Go Boutique.

Someone else... I'll fail to properly quote Lloyd Dixon from Unitrode but having mentioned his name I must, obviously, be correct suggested that,

For certain flavours of Switch Mode Power supplies the loop is designed to crossover, first order, at some frequency determined by the topology. The final answer is unknown, it is constrained by the circuit, but calculations can be made.

The zero frequency is set to be half of the crossover frequency. The pole frequency is set to be twice the crossover frequency. The phase margin at crossover becomes 45. Apparently this results in 'critical damping'.

The OP has suggested all these poles and zeros are confusing and the maths possibly even more so. I feel the pain and I may not be helping especially when I try presenting sums... or blithering on about poles and zeroes.

Anyway.

It seems we want to use Boutique Wide Bandwidth OpAmps and Boutique Zero ESR output capacitors and in order to do so we have to tweak our 'real life' circuits on the bench until they seem to work.

Picture 1) A Boutique Wide Bandwidth Operational Amplifier Spice Model.

I've already given that one. In this case I've just increased the input stage current by a factor of 10 to hit a 10MHz Gain Bandwidth Product.

Picture 2) The previously suggested regulator model with a Boutique Zero ESR filter capacitor.

This time I have added local feedback around the Boutique Operational Amplifier. E1 is there to isolate the feedback node.

Guess What... I, interactively with some intuition, tweaked the component values to get the final result. Nominally First Order at crossover with 'about' 45 phase margin. I am a criminal.

Picture 3) The transient response.

Picture 4) Zoom In... Critical Damping, no Over or Under Shoot. I guess, unlike me, Lloyd Dixon knows something.

Someone else can provide or introduce the opportunity to, within reason, discuss the caveats.

If you want to play start out by setting E1 to 0V.


...
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Old Today, 11:35 AM   #117
jan.didden is offline jan.didden  Europe
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OK, you seem to know what you are talking about.
Can you educate me? See attached, one of my designs. From this graph I conclude it is stable, what with sufficient phase margin. Yet, it oscillates. Why, what am I not getting?
How should I modify this bode curve to make it stable?

Jan
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