Hello everyone, I've started a new thread for PSUD usage to avoid the thread on PSUD enhancements for getting too cluttered up, hope everyone is OK with this.
I will kickstart it with the tail end of the last question on PSUD usage:
PSUD in its current form isn't comfortable with the small values, as you know. From a practical point of view, this hasn't normally been an issue which is why I asked about your supply as the reasons for requesting extended values is normally people playing around with extremes of numbers rather than a logical design reason backed up by sound physical principles.
That wasn't a criticism, I get what you are trying to do here, however I would be looking at the inductance of the capacitors too as this may screw the whole filtering idea. For example, if the inductance of the capacitor is 50uH and you want to feed it with a 1.5uH filtering choke, it's not going to do a lot for you.
Coming back to PSUD for a minute - it won't model inductance in capacitors even if you know the value anyway, and the time stepping is not geared to dealing with high frequency artifacts. That's two good reasons why you might prefer to put PSUD away and pick a SPICE based package, backed up by real world inductance measurements from the capacitors you are using.
I will kickstart it with the tail end of the last question on PSUD usage:
PSUD in its current form isn't comfortable with the small values, as you know. From a practical point of view, this hasn't normally been an issue which is why I asked about your supply as the reasons for requesting extended values is normally people playing around with extremes of numbers rather than a logical design reason backed up by sound physical principles.
That wasn't a criticism, I get what you are trying to do here, however I would be looking at the inductance of the capacitors too as this may screw the whole filtering idea. For example, if the inductance of the capacitor is 50uH and you want to feed it with a 1.5uH filtering choke, it's not going to do a lot for you.
Coming back to PSUD for a minute - it won't model inductance in capacitors even if you know the value anyway, and the time stepping is not geared to dealing with high frequency artifacts. That's two good reasons why you might prefer to put PSUD away and pick a SPICE based package, backed up by real world inductance measurements from the capacitors you are using.
I habe a maybevery simple question on usage:
I have a classical EL34 Stereo Amp where both channels for the EL34 share one PSU. The driver stage gets each its own LC-leg.
So let's say: Bridge-30uF-6H-400uF to EL34 and 25H-50uF two times in paralel to each driver stage per channel.
So, how do I model these two legs in a correct way ? I can see that the resonance behavior of stages when using multiple chokes influences each other, so I guess the resonances at the first choke are going to ne different if I hve two 25H chokes following in parallel ?
I have a classical EL34 Stereo Amp where both channels for the EL34 share one PSU. The driver stage gets each its own LC-leg.
So let's say: Bridge-30uF-6H-400uF to EL34 and 25H-50uF two times in paralel to each driver stage per channel.
So, how do I model these two legs in a correct way ? I can see that the resonance behavior of stages when using multiple chokes influences each other, so I guess the resonances at the first choke are going to ne different if I hve two 25H chokes following in parallel ?
> 25H-50uF
Model one network, with load.
*Probably* if nothing bad happens with one, two will also be fine.
Remember that in the Old Days, NOBODY could simulate before build. Stuff worked, or you figured out "why?" and did something else. By the 1940s, large power grid stability questions forced pre-"simulation" with small parts on a board, to see if Delaware got surged if Philadelphia lost power. But small stuff like audio didn't get simulated until the last decade or so, and we managed.
Model one network, with load.
*Probably* if nothing bad happens with one, two will also be fine.
Remember that in the Old Days, NOBODY could simulate before build. Stuff worked, or you figured out "why?" and did something else. By the 1940s, large power grid stability questions forced pre-"simulation" with small parts on a board, to see if Delaware got surged if Philadelphia lost power. But small stuff like audio didn't get simulated until the last decade or so, and we managed.
Im going to build a tube psu with Az1 rectifier.
My idea is to use a 10uf cap after the rect followed
by a 20H choke & a 47uf cap at the output. Now
from here I would like to split the supply into 2
chokes each suppyling 1 channel of the preamp.
How do I simulate this in PSUD ?
Thks
My idea is to use a 10uf cap after the rect followed
by a 20H choke & a 47uf cap at the output. Now
from here I would like to split the supply into 2
chokes each suppyling 1 channel of the preamp.
How do I simulate this in PSUD ?
Thks
That is what I did as well sofar, but I believe that this is not giving the correct result.
Reason: The resonance / inductivity of the three chokes (the big on after the rectifier and the two smaller ones for each channel) influence each other. Look at the Resonance on zhe first choke in the voltage domain when you change the valies of the secomd choke, not changing anything else.
Reason: The resonance / inductivity of the three chokes (the big on after the rectifier and the two smaller ones for each channel) influence each other. Look at the Resonance on zhe first choke in the voltage domain when you change the valies of the secomd choke, not changing anything else.
True! I just try to eliminate resonances - at least in simulation. Then changing the value of the choke doesn't seem to affect previous stage. not enen if I move from LC to RC. But I agree it may be not accurate.
Are you sure ? If I look at the Voltage raise without softstart on the first cap after the first choke, it behaves differently when introducing a second LC stage....
Here is an example of what I mean - likely to be wrong though. All graphs are C3 voltage (first cap after the first choke). First pic is CRCLC then splited to two LC one represented as current tap 1. Second pic is with everything after C3 removed and replaced with total load. Third pic is with the final choke increased from 4,1H to 10H. And fourth pic is with last choke decreased from 4,1H to 2H. Pretty much unaffected.
Attachments
The reason for that is simple: You have an extremely dampened PSU modelled here with a very high impedance. This is normally not your design target. You want a very low impedance/stiff regulation.
The more resistance you add, the more any resonance will be killed. You should model it with let's say 25H/90ohm first choke and 25/90ohm second choke and play with the inductance and resistance of the second choke....I guess then you will see the effect...
The more resistance you add, the more any resonance will be killed. You should model it with let's say 25H/90ohm first choke and 25/90ohm second choke and play with the inductance and resistance of the second choke....I guess then you will see the effect...
If you have two chokes each feeding their own cap then a good approximation - assuming equal current draw from each channel - is to model one choke of half the inductance feeding one cap of twice the capacitance.sumotan said:
> Pretty much unaffected.
Not a shock.
Also: if you are looking at L-C resonances, your loads are probably resistor-like (tube and resistor?) rather than current-source. This will add damping.
I got a "scientific calculator" for $1 at Dollar Tree. Let's see if it works. (Buttons are not too responsive.) 25H and 50uFd makes 4.7Hz. (1/x key is a 2-key, tiny label.) 50uFd (or 25H) at 4.7H is 678 Ohms. The 146 Ohms in the choke will keep Q down near 4, no wicked ringing. The 460r in the supply makes low Q, something over 1. (Ah, 16K resistor legs won't add much damping.)
What would excite a 4.7Hz ring? Not power line. 4.7Hz is 282BPM, so very fast dance music might excite it. (Metronomes traditionally go just past 200BPM, but Speedcore has BPM running up into the audio band.)
I think you are over-thinking.
The fact that PSUD does not handle multiple resistive legs is not new. It would probably complicate a very good and FREE program. I'm grateful to Duncan for making it easy to mock-up and document the Base Supply. Working all the legs of the supply does not (should not) need a computer, IMHO, since they are usually small and cheap to over-specify (50uFd when 10uFd might be OK).
Not a shock.
Also: if you are looking at L-C resonances, your loads are probably resistor-like (tube and resistor?) rather than current-source. This will add damping.
I got a "scientific calculator" for $1 at Dollar Tree. Let's see if it works. (Buttons are not too responsive.) 25H and 50uFd makes 4.7Hz. (1/x key is a 2-key, tiny label.) 50uFd (or 25H) at 4.7H is 678 Ohms. The 146 Ohms in the choke will keep Q down near 4, no wicked ringing. The 460r in the supply makes low Q, something over 1. (Ah, 16K resistor legs won't add much damping.)
What would excite a 4.7Hz ring? Not power line. 4.7Hz is 282BPM, so very fast dance music might excite it. (Metronomes traditionally go just past 200BPM, but Speedcore has BPM running up into the audio band.)
I think you are over-thinking.
The fact that PSUD does not handle multiple resistive legs is not new. It would probably complicate a very good and FREE program. I'm grateful to Duncan for making it easy to mock-up and document the Base Supply. Working all the legs of the supply does not (should not) need a computer, IMHO, since they are usually small and cheap to over-specify (50uFd when 10uFd might be OK).
I'm trying to beat my ignorance which is reflected on designs like the one I post here. Your replies help a lot on this! I'm also very happy that PSUD reliefs me from doing all this math. And I feel fine that I didn't even knew what speedcore is😀
My over-thinking derives from an obsession wrt noiseless psu under all conditions no matter what BPM. But I suppose there's no free lunch. At least, I feed my brain. Thanks!
My over-thinking derives from an obsession wrt noiseless psu under all conditions no matter what BPM. But I suppose there's no free lunch. At least, I feed my brain. Thanks!
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Obsessing about something in electronic design almost always means not thinking enough about two or three other more important issues. However, we have all done it when starting out; as we learn about each new issue it for a while becomes for us the most important issue.
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