I built an experimental voltage regulator this weekend, whose main main features are
Two stages of shunt regulation are used in the VREF generator. The first stage generates 10V using current source Q3 (10mA) and Zener diode D4. This regulated 10V supply drives a second shunt regulator made from R10 and the LM329 reference voltage IC, U3. R11-C7 form a filter which keeps noise out of the VREF node.
The opamp's output voltage is level-shifted up by 5.0 volts, using a TL431 as a low impedance 5V zener. A constant current of 10mA (from Q4) flows in the level shifter, ensuring it remains a low impedance. Setting the opamp's output pin 5V below the MOSFET gate node, keeps the output pin well below the supply pin, and operates the output stage in its sweet spot.
Frequency compensation is provided by (R13-C8). The gate snubber network R5-C1 was not populated; those are optional components that were never tried.
The regulator was built on a thru-hole PCBoard, see photos below. The opamp was socketed, making it easy to swap in different opamps with different Gain-Bandwidth products. Eight different opamps were tried; the voltage regulator operated correctly in all eight cases. A transient load test with high current, fast square waves (500mA -> 1000mA -> 500mA) was performed each time; in no case was instability, oscillation, or ringing observed. The opamps were
- Very high fT device used as series pass transistor: Nchannel MOSFET
- VREF bias current from VIN a la Sulzer Regulator
- Opamp power supply from VIN a la Sulzer Regulator
- Works with opamps from 0.6 MHz to 66 MHz gain-bandwidth
Two stages of shunt regulation are used in the VREF generator. The first stage generates 10V using current source Q3 (10mA) and Zener diode D4. This regulated 10V supply drives a second shunt regulator made from R10 and the LM329 reference voltage IC, U3. R11-C7 form a filter which keeps noise out of the VREF node.
The opamp's output voltage is level-shifted up by 5.0 volts, using a TL431 as a low impedance 5V zener. A constant current of 10mA (from Q4) flows in the level shifter, ensuring it remains a low impedance. Setting the opamp's output pin 5V below the MOSFET gate node, keeps the output pin well below the supply pin, and operates the output stage in its sweet spot.
Frequency compensation is provided by (R13-C8). The gate snubber network R5-C1 was not populated; those are optional components that were never tried.
The regulator was built on a thru-hole PCBoard, see photos below. The opamp was socketed, making it easy to swap in different opamps with different Gain-Bandwidth products. Eight different opamps were tried; the voltage regulator operated correctly in all eight cases. A transient load test with high current, fast square waves (500mA -> 1000mA -> 500mA) was performed each time; in no case was instability, oscillation, or ringing observed. The opamps were
- OP07 (0.6 MHz)
- TL071 (3 MHz)
- OPA134 (8 MHz)
- NE5534A (10 MHz)
- LM318 (15 MHz)
- OPA604 (20 MHz)
- AD817 (50 MHz)
- LME49710 (55 MHz)
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I don't feel any motivation at all, to make any more measurements and gather any more data; at least, not for a good long while. The project has met my goals already.
I suppose that leaves you with a few options. You can either (i) forget about this, or (ii) build up a board and measure it yourself, or (iii) run a simulation. The good news is that the power MOSFET model is presupplied with LTSPICE. Also since the real board works well over a wide range of real opamps, you can drop an opamp into your simulation that's "pretty close" to the opamp you care about, but use one whose model is presupplied. (For example: TL071 is not a presupplied model in LTSPICE. But you can use the presupplied LT1352, which has the same GBW and slew rate, to get a pretty good idea of how the TL071 might simulate).
I don't know for sure what results you might get. But I kinda expect that they might resemble the LTSPICE results shown below. If you believe in simulation, give it a try and see. If you don't believe in simulation, whip up a lemon ice box pie and enjoy a couple slices.
I suppose that leaves you with a few options. You can either (i) forget about this, or (ii) build up a board and measure it yourself, or (iii) run a simulation. The good news is that the power MOSFET model is presupplied with LTSPICE. Also since the real board works well over a wide range of real opamps, you can drop an opamp into your simulation that's "pretty close" to the opamp you care about, but use one whose model is presupplied. (For example: TL071 is not a presupplied model in LTSPICE. But you can use the presupplied LT1352, which has the same GBW and slew rate, to get a pretty good idea of how the TL071 might simulate).
I don't know for sure what results you might get. But I kinda expect that they might resemble the LTSPICE results shown below. If you believe in simulation, give it a try and see. If you don't believe in simulation, whip up a lemon ice box pie and enjoy a couple slices.
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Interesting that it is so flexible with respect to op amp choice.
Also good that the IPP037 is fine with just 10R as a gate stopper. I stopped at 22R. The lower gate stopper won't slow the speed of the IPP and will have a good impact on line rejection in the higher frequencies. Were it not for project fatigue on my side I'd still be tempted to try the Zobel/snubber (your C1 R5) in lieu of the gate stopper.
With the AD817 I found I did not need any frequency compensation around the op amp. Did you find this necessary with one of the op amps you tried or it was just en situe for all?
And, of course, we found that one can power the op amp and Vref from Vout which allows some simplification of the circuit (I dropped your Q3 and D4).
Now for the negative voltage rail...
And if one could get the thermals figured out the BUK9 series pass transistors might be even better.
Andrew, I found at least 4-5V was best.
Also good that the IPP037 is fine with just 10R as a gate stopper. I stopped at 22R. The lower gate stopper won't slow the speed of the IPP and will have a good impact on line rejection in the higher frequencies. Were it not for project fatigue on my side I'd still be tempted to try the Zobel/snubber (your C1 R5) in lieu of the gate stopper.
With the AD817 I found I did not need any frequency compensation around the op amp. Did you find this necessary with one of the op amps you tried or it was just en situe for all?
And, of course, we found that one can power the op amp and Vref from Vout which allows some simplification of the circuit (I dropped your Q3 and D4).
Now for the negative voltage rail...
And if one could get the thermals figured out the BUK9 series pass transistors might be even better.
Andrew, I found at least 4-5V was best.
Very nice design. Thank-you for sharing.
The compensation arrangement of R13 and C8 is innovative (at least to me). I would guess it's this which gives the design its excellent opamp invariance. How did you choose their values? Were they experimentally determined? Were they discerned using LTSPICE? Do you have a theoretical method for calculating them? Are they just the choice of experience? Or what?
The compensation arrangement of R13 and C8 is innovative (at least to me). I would guess it's this which gives the design its excellent opamp invariance. How did you choose their values? Were they experimentally determined? Were they discerned using LTSPICE? Do you have a theoretical method for calculating them? Are they just the choice of experience? Or what?
I appreciate the time and effort involved, but if you get a chance would you be able to post oscilloscope screen shots of the output voltage during chop chop box rising and falling edges, together with simulations of the same?
It would be interesting to compare SPICE and reality.
It would be interesting to compare SPICE and reality.
The JFET + 25 turn trimpot, performed delightfully as a 10mA current reference. The trick is to select a JFET whose IDSS exceeds the desired current, guaranteeing that some source degeneration resistance Rsource will be required. Then choose a trimpot value for Rsource such that (Rtrimmer * Idss) > RawSupplyVoltage.
In this case, Idss=40mA and Rtrimmer=RV2=1K, so (Rtrimmer * Idss) is forty volts, which comfortably exceeds the supply voltage. With a 25 turn pot you aren't too concerned about "wasting" trim range by using a too-high max resistance value.
Of course you couldn't be quite this cavalier if the headroom were tiny. But in a 12V supply, it's huge.
In this case, Idss=40mA and Rtrimmer=RV2=1K, so (Rtrimmer * Idss) is forty volts, which comfortably exceeds the supply voltage. With a 25 turn pot you aren't too concerned about "wasting" trim range by using a too-high max resistance value.
Of course you couldn't be quite this cavalier if the headroom were tiny. But in a 12V supply, it's huge.
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Post#9 suggested one (crude) way to select the source degeneration trimmer potentiometer Rsource. Other, somewhat more refined, design approaches are possible. Here are two of them.
First, an inspection of the schematic of the +12V regulator (1st attached image) shows that the voltage across the current source is 12.5 volts or greater. Since 10 milliamps is flowing, (Rsource * 10mA) must be less than or equal to 12.5 volts. This means Rsource <= 1250 ohms. Choosing a 1K trimmer pot seems like a good idea.
Second, we can look at datasheets for the family of JFETs to which this particular device (J109) belongs. DigiKey's handy "Compare Selected Devices" feature gives the 2nd attached image. It appears that Fairchild has provided several JFET devices for different IDSS ranges:
And now I'll add another little slice of safety margin, by assuming the max IDSS is not four, but FIVE times the min IDSS. For the J109, that means (40mA < IDSS < 200mA). Now we can zoom in on the appropriate piece of the "Parameter Interactions" graph in the J109 datasheet: 3rd attached image.
We draw a red horizontal line at IDSS=40mA, and we draw a blue horizontal line at IDSS=200mA. These intersect the J109 measured data at points "A" and "B" respectively. Point A tells us that a J109 with IDSS=40mA also has a VGSOFF value of -0.95 volts. Point B tells us that a J109 with IDSS=200mA also has a VGSOFF value of -3.8 volts.
VGSOFF is the (negative) Gate-to-Source bias voltage that turns the JFET completely off; IDS=zero. However our current source is supposed to operate at IDS=10mA, so we our VGS cannot be as low as VGSOFF.
Since the gate is tied to ground (figure 1), VGS is the (negative) voltage across the source resistor Rsource. Eureka! The voltage across the source resistor must be less than the absolute value of VGSOFF:
By the way, I measured the final adjusted value of Rsource on my PSU board, which gave exactly 10.0 mA with this one particular J109. It is 275 ohms.
Summarizing these three design procedures for choosing the Rsource trimmer max resistance, arranged in order from sloppiest to most refined,
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First, an inspection of the schematic of the +12V regulator (1st attached image) shows that the voltage across the current source is 12.5 volts or greater. Since 10 milliamps is flowing, (Rsource * 10mA) must be less than or equal to 12.5 volts. This means Rsource <= 1250 ohms. Choosing a 1K trimmer pot seems like a good idea.
Second, we can look at datasheets for the family of JFETs to which this particular device (J109) belongs. DigiKey's handy "Compare Selected Devices" feature gives the 2nd attached image. It appears that Fairchild has provided several JFET devices for different IDSS ranges:
- 10mA or more: J110
- 20mA or more: J111
- 40mA or more: J109
- 80mA or more: J108
- 100mA or more: J107
And now I'll add another little slice of safety margin, by assuming the max IDSS is not four, but FIVE times the min IDSS. For the J109, that means (40mA < IDSS < 200mA). Now we can zoom in on the appropriate piece of the "Parameter Interactions" graph in the J109 datasheet: 3rd attached image.
We draw a red horizontal line at IDSS=40mA, and we draw a blue horizontal line at IDSS=200mA. These intersect the J109 measured data at points "A" and "B" respectively. Point A tells us that a J109 with IDSS=40mA also has a VGSOFF value of -0.95 volts. Point B tells us that a J109 with IDSS=200mA also has a VGSOFF value of -3.8 volts.
VGSOFF is the (negative) Gate-to-Source bias voltage that turns the JFET completely off; IDS=zero. However our current source is supposed to operate at IDS=10mA, so we our VGS cannot be as low as VGSOFF.
Since the gate is tied to ground (figure 1), VGS is the (negative) voltage across the source resistor Rsource. Eureka! The voltage across the source resistor must be less than the absolute value of VGSOFF:
- IDS * Rsource < |VGSOFF|
- Rsource < |VGSOFF| / 10mA
- {Rsource < 95R} and also {Rsource < 380R}
By the way, I measured the final adjusted value of Rsource on my PSU board, which gave exactly 10.0 mA with this one particular J109. It is 275 ohms.
Summarizing these three design procedures for choosing the Rsource trimmer max resistance, arranged in order from sloppiest to most refined,
- Choose Rsource =approx= (3-4 * Vsupply) / (min IDSS)
- Choose Rsource =approx= (DCinput - 1.5) / (desired current)
- Guess that IDSSmax = 5*IDSSmin. Look up VGSOFFmax for IDSSmax on the datasheet "Parameter Interactions" graph. Choose Rsource =approx= |VGSOFFmax| / (desired current)
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You analyze it the exact same way you analyze a BJT pass device.
In the BJT pass device you want
- VCE >= max_possible_VBE + Cushion_Of_Comfort
In the Nchannel MOSFET pass device you want
- VDS >= max_possible_VGS + Cushion_Of_Comfort
The "max_possible_VBE" occurs at the worst case extreme temperature (Tj=-55C for Silicon devices) and the worst case extreme base current (min Beta + max I_LOAD).
The "max possible VGS" occurs at the worst case extreme temperature (Tj=-55C for Silicon devices) and the worst case extreme threshold voltage (datasheet max VGS_th) and the worst case extreme load current (max I_LOAD).
The only significant difference is that the variability of the MOSFET's threshold voltage (stated on the datasheet) is quite a bit larger than the variability of a bipolar's VBE.
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Just curious, does the multi MHz capability , just for Op Amp and FET make much of a difference, if any at all, considering that the Power Supply output is loaded/shunted with a 470uF cap?
Rather than simply giving you the answer, I will provide some data that may help you discover the answer yourself, and learn in the process.
Attachment 1 is a graph from the website of Linear Audio magazine, showing a comprehensive test of a large number of voltage regulators. Output impedance (closed loop) is plotted versus frequency. Lower impedance is preferable, as it stops audio circuits from modulating their power supplies when drawing time-varying currents to drive a load. So the best regulator is the one that has the lowest impedance at the highest frequency. As you can see the best is Jung AD797. Its output impedance rises to 1 ohm (red arrow/black dot) at 2E7 Hertz {extrapolated}. That's 20 Megahertz! The second best is the Jung AD825, whose output impedance rises to 1 ohm at 1E7 Hertz {extrapolated}, namely 10 Megahertz.
Attachment 2 shows the schematic of the Jung regulator. Please notice electrolytic capacitor C4, from regulator output to ground. The regulators that performed best in Attachment 1, with 10 Megahertz performance, had 120uF capacitors shunting their output to ground.
But how can this be true? That's a problem to think about and work on, for a couple of days.
On Friday I'll give you a link to an online article by Mr. Bang S. Lee, who explains everything.
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And how does your compare to those tested in Attachment 1?
Also what about some other OP like LMH6624? What to look for in datasheets?
Also what about some other OP like LMH6624? What to look for in datasheets?
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The other question is - does it matter if the power MOSFET is a "fast switching" one? Especially since the chosen one has a 10000pF Ciss and you're trying to drive it with an opamp not a gate driver.....
Hi Mark, can you post a link to the article? (I thought adding output capacitance lowered Zout so I'm missing the conflict.)
Ah I had seen that article before (likely because you led me to it.) Glossing over the detail of the mathematics for a moment (never a good idea but)... So the better regulators (amongst other things) have pole/zero structures which allow a higher level of output capacitance and hence lower output impedance?
I don't know how to say it without mathematics; each individual regulator design has a happy region in the Cartesian plane of (X=output capacitance, Y=ESR), where that regulator works really well. If you plunk down an output capacitor that's within the happy region for regulator ABC, then ABC will be happy (stable). If you plunk down an output capacitor that's well outside the happy region for regulator ABC, then ABC will be unhappy (unstable).
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