Life is not simple. See https://forum.kicad.info/t/finished-hole-sizes-after-plating-how-does-the-calculation-work/143/5
Here is a snip from that web page
Here is a snip from that web page
Typically, if you're worrying about the plating thickness, then your hole is too small. A larger-than-needed hole is rarely an issue, but a smaller-than-needed one ruins your board. If you've already half assembled a board before finding a hole size issue, then you've also potentially ruined some parts. A better approach is to simply make the hole larger than necessary, and shrink it down on later revisions as needed.
You should be fine just by following the datasheet's suggested part layout. They take into account all the part tolerances, and add in typical fab tolerances for something that should be pretty robust. Just double check to make sure that the fab's drill size chart supports it, and then you'll be fine.
The precise answer for coping with the plating is that it's fab specific. Some fabs assume that the size you specify is the "finished hole size" (eg, after plating), and some assume it's the "unfinished hole size" which will be plated afterward.
AP Looks like an example of a fab that expects you to specify unfinished hole sizes. So, if you specify a 20 mil drill, then it gets fabbed as 20 mil, then plated, and the board has a 17 mil hole.
OSH Park is an example of a fab that expects finished hole sizes. Specifying a 20 mil hole means we select an 23 mil drill, plate it, and give you a 20 mil hole.
This means that, depending on the board house you choose, you have to take into account what they expect: finished or unfinished hole sizes.
This also means that, when you create footprints, you have to take into account the "worst case scenario". However, while designing the footprints, you might not have any clue yet to which board house you will send your board. Hence, again the "risk" of choosing the wrong drill diameter while creating the footprint(s) for a new component...
As mentioned, if you're using a "recommended footprint" (which is a good idea), then you should be OK going with their suggested hole sizes. Those usually take into account general fab variances, so you don't need to worry about them.
If you're calculating the hole sized based on the pin, then I would simply add an extra 3-5 mil as a fab tolerance. That will cover most fab-specific issues, as well as rounding for their drill selection. So, an initial calculation (using a header pin as an example) would look like this:
(35 mil nominal pin size + 2 mil pin size tolerance + 2 mil clearance for fit + 5 mil fab tolerance). That gives you 44 mil, which is pretty reasonable, if not a bit generous. But, it gives you total fab immunity. Even if the fab punched this with a 40 mil drill and then plated it, the board would still work, which is what we want.
You should be fine just by following the datasheet's suggested part layout. They take into account all the part tolerances, and add in typical fab tolerances for something that should be pretty robust. Just double check to make sure that the fab's drill size chart supports it, and then you'll be fine.
The precise answer for coping with the plating is that it's fab specific. Some fabs assume that the size you specify is the "finished hole size" (eg, after plating), and some assume it's the "unfinished hole size" which will be plated afterward.
AP Looks like an example of a fab that expects you to specify unfinished hole sizes. So, if you specify a 20 mil drill, then it gets fabbed as 20 mil, then plated, and the board has a 17 mil hole.
OSH Park is an example of a fab that expects finished hole sizes. Specifying a 20 mil hole means we select an 23 mil drill, plate it, and give you a 20 mil hole.
This means that, depending on the board house you choose, you have to take into account what they expect: finished or unfinished hole sizes.
This also means that, when you create footprints, you have to take into account the "worst case scenario". However, while designing the footprints, you might not have any clue yet to which board house you will send your board. Hence, again the "risk" of choosing the wrong drill diameter while creating the footprint(s) for a new component...
As mentioned, if you're using a "recommended footprint" (which is a good idea), then you should be OK going with their suggested hole sizes. Those usually take into account general fab variances, so you don't need to worry about them.
If you're calculating the hole sized based on the pin, then I would simply add an extra 3-5 mil as a fab tolerance. That will cover most fab-specific issues, as well as rounding for their drill selection. So, an initial calculation (using a header pin as an example) would look like this:
(35 mil nominal pin size + 2 mil pin size tolerance + 2 mil clearance for fit + 5 mil fab tolerance). That gives you 44 mil, which is pretty reasonable, if not a bit generous. But, it gives you total fab immunity. Even if the fab punched this with a 40 mil drill and then plated it, the board would still work, which is what we want.
Thanks. A most informative webpage. At least I have some idea of the real world situation now.
A small design change and a new PCB layout.
The new PCB layout incorporates the design change, and has had the hole sizes rationalized as best I can. The relationship between the drill diameters specified in the PCB files and the diameters of the holes in the finished PCB remains somewhat mysterious to me. I wish PCB makers would publish lists of the exact hole sizes they can actually make.
In order to make it easier to set an exact voltage I changed the voltage reference from a zener diode to a TL431. The rest of the circuit remains the same. The voltage form the reference (whether zener or TL431) is passed through an RC low pass filter having a 10uF capacitor and an aprox 4 Hz corner frequency. The output from the RC low pass filter's connected to the base of the regulator output voltage sensing transistor.
Given the presence of the low pass filter I didn't expect changing the reference to make any significant difference to the circuit's performance. But, at least in LTSpice, it made a worthwhile reduction in the deviation from the specified output voltage during load current transients. It seems that even with the low pass filter an (unwanted) signal could get all the way round the loop R16 -> R13 -> Q7 -> R16 ...
The new PCB layout incorporates the design change, and has had the hole sizes rationalized as best I can. The relationship between the drill diameters specified in the PCB files and the diameters of the holes in the finished PCB remains somewhat mysterious to me. I wish PCB makers would publish lists of the exact hole sizes they can actually make.
In order to make it easier to set an exact voltage I changed the voltage reference from a zener diode to a TL431. The rest of the circuit remains the same. The voltage form the reference (whether zener or TL431) is passed through an RC low pass filter having a 10uF capacitor and an aprox 4 Hz corner frequency. The output from the RC low pass filter's connected to the base of the regulator output voltage sensing transistor.
Given the presence of the low pass filter I didn't expect changing the reference to make any significant difference to the circuit's performance. But, at least in LTSpice, it made a worthwhile reduction in the deviation from the specified output voltage during load current transients. It seems that even with the low pass filter an (unwanted) signal could get all the way round the loop R16 -> R13 -> Q7 -> R16 ...
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If it were me, I would prefer mechanical connectors that are a little more snug and tight for CONN2, 3, 4, 5 on the DC inputs and outputs. Something like EuroBlox connectors (example) or else spade lugs (male) , (female) . I want it to be vibration proof and moving-van-bouncy-bouncy proof and United Parcel Service package handler proof.
Also I think you will be happier with the ground plane if you move CONN3 another 0.3" away from the corner of the PCB, i.e., 0.3" up and 0.3" left. You want a super low-impedance pathway from CONN3 to CONN4 with as few "squares" of copper as possible. You might even consider the BFMI idea of putting one or more wide straight runs of thick copper desoldering braid on the bottom (non component) side of the PCB, as was done here. Brute Force and Massive Ignorance: BFMI.
Finally, I recommend you study (the datasheet) of the discrete component voltage regulator from one of your competitors. Especially Figure 7. His method of applying fast-risetime square wave load currents, has the nice advantage of making it possible to observe the current waveform itself. Merely attach a scope probe to measure the voltage across the 1 ohm resistor. Also notice that his signal generator's output does not need any special DC offset. Yours needs to be carefully adjusted so the DC offset exactly cancels VBE_Q9 + VTH_X4.
Also I think you will be happier with the ground plane if you move CONN3 another 0.3" away from the corner of the PCB, i.e., 0.3" up and 0.3" left. You want a super low-impedance pathway from CONN3 to CONN4 with as few "squares" of copper as possible. You might even consider the BFMI idea of putting one or more wide straight runs of thick copper desoldering braid on the bottom (non component) side of the PCB, as was done here. Brute Force and Massive Ignorance: BFMI.
Finally, I recommend you study (the datasheet) of the discrete component voltage regulator from one of your competitors. Especially Figure 7. His method of applying fast-risetime square wave load currents, has the nice advantage of making it possible to observe the current waveform itself. Merely attach a scope probe to measure the voltage across the 1 ohm resistor. Also notice that his signal generator's output does not need any special DC offset. Yours needs to be carefully adjusted so the DC offset exactly cancels VBE_Q9 + VTH_X4.
Interesting argument: security of mechanical connection verses security of electrical connection.
My plan for CONN2, 3, 4, 5 has been to solder the wires directly into the holes in the PCB. This makes the best possible electrical connection (I think) at the cost of a requirement to "handle with care" at all times because of the delicacy of the solder joints. The current PCB for this circuit is only a proof of concept PCB. Its purpose is solely to test the regulator circuit design and the accuracy of the simulations. Its life cycle will be: Build -> Test -> Junk Box (no Use phase). So for this particular PCB I think it will be possible to handle it carefully enough for it to last through the test period even with wires soldered directly into the board.
However, at the end of the day I'm aiming for a combination pre-amp and headphone amp. In that application the regulators will be on the same PCB as the amplifier they power, thus eliminating the need for wire connections between the 2. In fact, the elimination of the wire connection's the main reason for putting them on the same board. Connecting wires seemed to cause SGK no end of trouble.
But there will, of course, be ground, signal in & out, and raw power in connections to that board. And its long term reliability is important, since it is intended for long term use. And so the question of how to connect to that PCB also arises. My (tentative) plan being to solder the wires directly into the holes in the PCB, just like with the test board. It's been done before, attached is a picture I found on the web of John Curl's Vendetta phono stage constructed this way. I'm also considering using small plastic tubes (like drinking straws, but stronger) as miniature wire ducts. The idea being to support and hold in place the wires, in part to relieve strain on the wire to PCB solder joints.
What do people think about this. What's the "gold standard" for connecting wires to PCBs?
Hmm. Actually it's only out of prettiness that I've put CONN2 and CONN3 side by side. CONN2 is raw power in and CONN3 is ground in (& CONN4 is ground out). Ground and raw in are not going to be twisted together or anything like that -- so actually there's no need for CONN2 and CONN3 to be close to each other.
How about moving CONN3 to be right next to CONN4?
I'm flattered to be considered a competitor in any sense to Sparko’s Labs. The data sheet is indeed unusually informative, thank-you for drawing it to my attention. It's 1 of the few (in my (limited) experience) to include measured transient response oscillographs.
Sparko's circuit and mine are quite similar. The current waveform can be observed in the same way with my circuit by scoping the voltage across R17, and there's a BNC connector (CONN10) included on the PCB for this purpose. Having a connector for a BNC cable is easier than using a scope probe, and doesn't prevent the use of a probe if the x10 setting's desired. 5 of the 6 BNCs on the PCB are for making easy scope connections for test purposes.
The big difference between Sparko's circuit and mine is the power transistor/MOSFET driving arrangement. Where I use an emitter follower with a current sink load to drive the gate of a MOSFET, Sparko uses an opamp and feedback to drive the base of a power transistor. (At low frequencies) Sparko's method will yield a test load current waveform more accurately the same shape as the voltage waveform from the signal generator due to the feedback correction.
But which circuit will be fastest? The emitter follower with current sink load copies the design of the shunt's MOSFET driver (which performs in inverse the same changes in drain current as the test load). The performance of the shunt in LTSpice is amazingly (perhaps unbelievably) good -- see the attached LTSpice graph for 100 ns edges (vertical scale 6E-5 v/div & 8 mA/div, horizontal 1E-6 s/div).
Looking at Sparko's figure 7 I note that mod(Z(220pF)) = 1K at 723kHz, suggesting that around that frequency it loses responsiveness as the voltage at the opamp's inverting input starts tracking the opamp output directly rather than the voltage at the power transistor's emitter.
BTW What's the purpose of the diode in Sparko's circuit?
This comment sent me scurrying over to my signal generator and oscilloscope to check that the signal generator can in fact produce the required DC offset. It can. Phew. I'd have felt a bit stupid if it turned out it couldn't.
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I'm sure that soldered wires with short cantilevers are quite tolerant of vibration and shock. The rest is simply food for thought; do with it as you see fit.
Slightly Revised PCB Layout
I've moved CONN3 to be both further from the edge of the ground plane, and very much nearer CONN4 (the other ground connection). Also I added copper on the bottom of the board joining CONN3 and CONN4 (in addition to the ground plane joining them on the top of the board). Thus, I hope, greatly reducing the impedance between CONN3 and CONN4.
I've moved CONN3 to be both further from the edge of the ground plane, and very much nearer CONN4 (the other ground connection). Also I added copper on the bottom of the board joining CONN3 and CONN4 (in addition to the ground plane joining them on the top of the board). Thus, I hope, greatly reducing the impedance between CONN3 and CONN4.
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PCBs Arrive
Following Mark Johnson's suggestion I went to PCBShopper » A Price Comparison Site for Printed Circuit Boards and found a cheap PCB maker -- cheap for 1 board even though it's minimum quantity was 5! The 5 (4.5 inch by 6 inch double sided) PCBs cost $46 including shipping, tax, and everything, paid by Paypal. They arrived 11 days after a Friday evening gerber upload, and appear to have no manufacturing defects.
Following Mark Johnson's suggestion I went to PCBShopper » A Price Comparison Site for Printed Circuit Boards and found a cheap PCB maker -- cheap for 1 board even though it's minimum quantity was 5! The 5 (4.5 inch by 6 inch double sided) PCBs cost $46 including shipping, tax, and everything, paid by Paypal. They arrived 11 days after a Friday evening gerber upload, and appear to have no manufacturing defects.
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