Mystery load current spike in dual rail 9V low-battery cutoff circuit - diyAudio
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Old 20th June 2015, 04:50 PM   #1
agdr is offline agdr  United States
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Default Mystery load current spike in dual rail 9V low-battery cutoff circuit

I would like to ask if any of the circuit gurus here can figure out the source of a load currrent spike in a dual-rail low battery cutoff circuit I'm putting together. This is intended to be an upgraded version of the power management circuit in NwAvGuy's O2 headamp.

The circuit has one comparator per 9V battery, each set for a 7.0Vdc trip point. The goal is to disconnect the load(s) when either battery drops below 7.0V. The two mosfets on the comparator outputs (M1 & M2) form a "wire AND" logic circuit such that if either battery drops below 7.0V then both rails get cut off at exactly the same time due to the current flow though both BJT bases cutting off at the same time.

The M3 mosfet is a place holder for a to-be-designed latch circuit that so far I can't get to work either, but first things first. The gate is tied out of the way for now. Removing M3 makes no change in the current glitch problem.

The circuit simulates perfectly with the bottom battery set at a voltage higher than the cutoff point, like 7.2V. The problem comes when the bottom battery is below the trip point (dead battery), like 6.8V, such that the bottom M2 mosfet is off. The load current through the top 100R dummy load then shows a mysterious spike when the upper comparator drops from 7V to 0V to turn on the M1 mosfet but no current through it since the bottom M2 mosfet is off).

To make things even stranger, I've tried completely removing R5 in series with the mosfets - and the spike is still there!

So my question: anybody have any idea what could be causing that spike, or is it simply a simulation ghost? Yeah, I know, time to build it for real and measure it. But before sending a test board out to fab I'd like to find out if there is a simple circuit design screw up here I'm missing.

My best guess, if the spike is real, is something to do with the mosfet gate-to-source capacitance charging/discharging with the comparator state change, causing a current spike through the Q2 base. And if that is what is going on, what can be done about it? This is also the reason for D2 and D6. Given that the mosfet gate-to-source will charge to 7V initially with the top comparator output at 0V, then the instant the comparator switches that "capacitor" would add to the rail producing 14V, exceeding the Q2 5V or so maximum Vbe in reverse. The diode then is just a safety clamp. In the forward direction I've specifically chosen Schottkys here since they are leaking in reverse, giving the mosfet source a path to the positive rail. I don't trust the properties of the Q2 Vbe junction with no current going through it.

* the first attachment is the circuit
* next is the piecewise linear waveform in green for the top battery. Starts charged at 7.5, drops to 6.8V at 5 seconds, then rises back up to 7.2V with the load removed
* next adds the to comparator output in blue
* next adds the load current in red through the top dummy load resistor
* next is a closeup of the glitch
* and finally what happens whem R5 is removed - same glitch
Attached Images
File Type: png PM ckt.png (46.7 KB, 89 views)
File Type: jpg input PWL waveform.JPG (29.1 KB, 86 views)
File Type: jpg comparator output.JPG (26.0 KB, 84 views)
File Type: jpg load current.JPG (34.1 KB, 80 views)
File Type: jpg current spike closeup.jpg (38.8 KB, 80 views)
File Type: jpg Current spike with R5 removed.JPG (183.8 KB, 13 views)

Last edited by agdr; 20th June 2015 at 05:00 PM.
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Old 20th June 2015, 05:00 PM   #2
cbdb is online now cbdb  Canada
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There is no load current other than the spike. There is no output voltage before or after the spike. Is this circuit working?
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Old 20th June 2015, 05:14 PM   #3
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It may help your troubleshooting if you plot V(m2source, m2gate), and if you also plot V(q2emitter, q2base), and if you also plot I(q2collector), and if you also plot I(q2base).

Can you show that the current pulse I(R7) does not flow through Q2's collector? Or can you prove that it does flow in Q2's collector?

If the current pulse does flow in Q2's collector, is there a corresponding base current (you know: Ibase = Icollector/Beta)? If there is a base current, where does it come from?

and so forth.
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Old 20th June 2015, 05:25 PM   #4
Mooly is offline Mooly  United Kingdom
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I suspect this might be a non problem. Have you tried a cap across the switched rails because in reality that would be present. Even if its only a 0.1uf, try it. You could also try some gate resistors, try crazy values like 10meg down to 100 ohm.

I experienced odd simulation behaviour here,
Thoughts on running LED's from high voltage into a constant current sink.
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Old 20th June 2015, 05:44 PM   #5
agdr is offline agdr  United States
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Quote:
Originally Posted by cbdb View Post
There is no load current other than the spike. There is no output voltage before or after the spike. Is this circuit working?
Good point, I didn't post a plot with the bottom "negative rail" battery above 7.0V to just show normal operation with both batteries good. All the plots above are with the negative rail battery set to 6.8V to be "bad" and below the 7.0V trip point, since that is where this spike shows up.

So here is a plot with the bottom battery at 7.2V. No current spikes and the load current through the positive rail dummy load does what I would expect. Again red here is the load current through the positive rail (top) dummy resistor. Starts out with the full 7V/100R = 70mA with both batteries good, then gets cut off when the top PWL wave drops below 7.0V, then back to 70mA when the top battery voltage rises up with the load cut off. That last part with the load turning on again when the battery voltage rises on cutoff is what the latch circuit will eventually lock out from happening, but I figure that I better get this spike solved first.

Thanks for all the helpful replies here! I'm going to have to run out for a bit but I will circle back.

Last edited by agdr; 20th June 2015 at 05:51 PM.
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Old 20th June 2015, 07:22 PM   #6
agdr is offline agdr  United States
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Quote:
Originally Posted by Mooly View Post
I suspect this might be a non problem. Have you tried a cap across the switched rails because in reality that would be present. Even if its only a 0.1uf, try it. You could also try some gate resistors, try crazy values like 10meg down to 100 ohm.

I experienced odd simulation behaviour here,
Thoughts on running LED's from high voltage into a constant current sink.
Good thoughts Mooly, I hadn't tried adding rail capacitance. Below are 0.1uf and then 220uf across the rails, but unfortunately no change.

I have tried experimenting with some base & gate stopper resistors, but no effect on the spike. I'll experiment with it a bit more tonight.
Attached Images
File Type: jpg 0.1u across batteries.JPG (182.2 KB, 11 views)
File Type: jpg 220u across batteries.JPG (177.7 KB, 7 views)
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Old 20th June 2015, 07:30 PM   #7
agdr is offline agdr  United States
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Quote:
Originally Posted by Mark Johnson View Post

Can you show that the current pulse I(R7) does not flow through Q2's collector? Or can you prove that it does flow in Q2's collector?

If the current pulse does flow in Q2's collector, is there a corresponding base current (you know: Ibase = Icollector/Beta)? If there is a base current, where does it come from?

and so forth.
Mark, you may be onto something here. You are quite right, I should have traced that current spike back through the parts. The spike is showing up at the gate of M2, and I'll bet I know where it is coming from. These particular comparators have a push-pull output section, a bit different than the more typical open collector and pull-up. I picked the part to lower the parts count (no pullups required). The spike may be the push-pull transition region. If I switch to an open collector model that may solve it. I'll give it a try.

Lol - the data sheet makes a big deal about "By eliminating the cross-conducting current that normally occur when the comparator changes logic states, power supply glitches are eliminated". Maybe power supply glitches, but not output glitches.

I forgot to say that R6 and C1 are from the datasheet, a bypass on the internal 1.182V reference to help isolate it from power supply glitches. R9 and R10 are hysteresis resistors from the datasheet - the part has the capability of built in hysteresis up to +/-50V or so. The comparator can simply be wired with all those parts gone, with the reference directly tied to the hysteresis pin and then to the "+" input. I've tried that before and it has no effect on the current spike.

In the plots below I'm using red as the tracer, deleting the previous use each time.

* First is the collector of Q2
* Next the base of Q2 = source of M2
* Next is the gate of M2. Looks like M2 is just doing exactly what it is being told to do.

Intersting that the other, rising, edge of the comparator transition also seems to have a small current spike.
Attached Images
File Type: jpg Q2 collector spike.jpg (34.3 KB, 8 views)
File Type: jpg Q2 base spike.jpg (34.6 KB, 7 views)
File Type: jpg M2 gate spike.jpg (34.3 KB, 6 views)

Last edited by agdr; 20th June 2015 at 07:43 PM.
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Old 20th June 2015, 10:16 PM   #8
agdr is offline agdr  United States
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Whoops - I just remembered the probe in the post above is for current, not voltage. So that is a 250uA *current* spike on the gate - on a mosfet, with an insulated gate. Probably not the comparator output section after all. I've just tried breaking the connection to the mosfet gate in the sim and trying a resistive load from the comparator output to ground. No current spikes. I also tried the load to the positive rail.

The second plot is the results with a gate resistor on M2. This is with 100 ohms, but I've tried 10 ohms to 1meg ohm. No change in the current spike. The red plot is the current through the gate resistor.

The third plot is the M2 source to gate voltage (back to no gate resistor on M2), and the 4th plot is the Q2 emitter-base voltage. Looks like the glitch exists on that VQ2eb.
Attached Images
File Type: jpg resistive comparator out.JPG (322.4 KB, 4 views)
File Type: jpg M2 gate resistor.JPG (314.7 KB, 3 views)
File Type: jpg VM2sg.jpg (28.6 KB, 4 views)
File Type: jpg VQ2eb.jpg (28.8 KB, 4 views)

Last edited by agdr; 20th June 2015 at 10:39 PM.
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Old 21st June 2015, 03:06 PM   #9
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Occasionally you'll see a post here on diyAudio from a LTSPICE beginner, who cannot accomplish what he's trying to do, so he blames LTSPICE and claims it's full of bugs. Usually the problem is the human, not the software.

I wanted to see whether LTSPICE might be giving a wrong answer in this particular case, so I entered a slightly modified version of the schematic (picture 1) and ran a simulation (picture 2).

It looks to me, like LTSPICE is working and giving the right answer. When one of the batteries falls below ~ 7 volts (minus the hysteresis deltaV), BOTH loads are disconnected. When that battery voltage rises again and crosses above ~ 7 volts (plus hysteresis), BOTH loads are reconnected. Turkey worky.

Rejoice, it is indeed possible to get this working in LTSPICE. The steps are simple: (1) design a good circuit; (2) enter it into LTSPICE without mistakes; (3) run the simulations; (4) analyze the results.
Attached Images
File Type: png schema.png (19.7 KB, 9 views)
File Type: png transient.png (29.7 KB, 11 views)
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Old 21st June 2015, 03:30 PM   #10
agdr is offline agdr  United States
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Mark, I just noticed your bottom "battery" voltage source it set above 7.0Vdc. I haven't had any troubles in the case of the bottom battery "good", the circuit works just fine as per post #5. The spike only shows up when the bottom battery is below 7.0V and the bottom mosfet is cut off. Or vise versa, with the PWL waveform running on the bottom "negative rail" voltage source and the top voltage source set for less than 6.8Vdc.

Is your modified circuit also current-spike free with the bottom battery less than 7.0V? If so thanks for pointing out a circuit screw-up here.

Last edited by agdr; 21st June 2015 at 03:46 PM.
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