Hello all.
Power amp usually does not have a regulator in its final stage. Lot of reasons have been said to avoid the power regulators, such as losing power, feedback stability problem, generate heat, space problem etc, etc. But if these problem are solved, power regulator may be reconsidered.
I have implemented current feed back with LDO technology, then I think demerits are minimized and can enjoy high PSRR, low output impedance.
This regulator has voltage reference , grounded base current feedback input, JFET folded cascode, PMOS pass transistor and output capacitor.
looks very simple.
JFET allows PMOS gate to be driven below output level then low drop out is realized. Refferene voltage activation current is sourced from stabilized output, so the refference voltage is very clean.
The bode plot of current gain which is the result of AC analysis shows good phase characteristic. Number of pole is less than usual LDO.
Actual regulator board is shown, this could operate at 5A , 20V
. The DC current handling capability is determined by PMOS and this utilize 2SJ618 (10A 130W). Drop out is also determined by this PMOS.
50KHz swing 1.25App (10V 8ohm) load test is favorable result 20mvpp drop with identical waveform to load voltage.
Output capacitor is OScon SEPF 330uf (low ESR, 14mohm)
Measured PSRR is 93db @100Hz ,output impedance is 16 mohm
Power amp usually does not have a regulator in its final stage. Lot of reasons have been said to avoid the power regulators, such as losing power, feedback stability problem, generate heat, space problem etc, etc. But if these problem are solved, power regulator may be reconsidered.
I have implemented current feed back with LDO technology, then I think demerits are minimized and can enjoy high PSRR, low output impedance.
This regulator has voltage reference , grounded base current feedback input, JFET folded cascode, PMOS pass transistor and output capacitor.
looks very simple.
JFET allows PMOS gate to be driven below output level then low drop out is realized. Refferene voltage activation current is sourced from stabilized output, so the refference voltage is very clean.
The bode plot of current gain which is the result of AC analysis shows good phase characteristic. Number of pole is less than usual LDO.
Actual regulator board is shown, this could operate at 5A , 20V
. The DC current handling capability is determined by PMOS and this utilize 2SJ618 (10A 130W). Drop out is also determined by this PMOS.
50KHz swing 1.25App (10V 8ohm) load test is favorable result 20mvpp drop with identical waveform to load voltage.
Output capacitor is OScon SEPF 330uf (low ESR, 14mohm)
Measured PSRR is 93db @100Hz ,output impedance is 16 mohm
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Ketje , Yes, your circuit is simpler, and PSRR may be the same or less
but considering input impedance of current feedback, series impedance of the zener diode and JFET( low gm), considered as a current feedback resister Rf will be far bigger.
The output impedance of this regulator is simply calculated as Rf/(R10*gm(PMOS)), total Rf should be small.
if you use BJT, the input impedance will be 26/Ic(mA) from theory and very small if Ic is big. Reesistor R17,5 ohm can be eliminated if you want to increase load regulation.
but considering input impedance of current feedback, series impedance of the zener diode and JFET( low gm), considered as a current feedback resister Rf will be far bigger.
The output impedance of this regulator is simply calculated as Rf/(R10*gm(PMOS)), total Rf should be small.
if you use BJT, the input impedance will be 26/Ic(mA) from theory and very small if Ic is big. Reesistor R17,5 ohm can be eliminated if you want to increase load regulation.
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