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Old 16th October 2014, 04:05 PM   #1
SGK is offline SGK
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Default Adventures with 5A regulated voltage circuits

Hi

As some of you know I have been embroiled in a project to construct a linear power supply with three regulated rails with output voltages of 12V, 5V and 3.3V respectively. The circuit involves combining a TL431 (or rather it's newer, lower noise, cousin the SPX431AN) with an LT1084. I started with the 5V rail then looked at 3V3 and lastly 12V. Each required slightly different tweaking to the RCR filter that skirts around the TL431 but in essence the circuit is the same. I've attached an image of the LTspice simulation circuit for the 12V rail below (12V) along with its modeled noise rejection (12VNR) and transient response (12VTR) for a step in load from 0.25A to 4.75A.

I am very puzzled by the output impedance analysis of this circuit. For loads less than 0.8A I get 'normal' looking output similar to the 5V and 3.3V rails. (That is, zero impedance rising to a peak of 6.3mOhms around 446kHz and then declining.) From a load of 0.85A and beyond I get the output in the image below (12VOZ). I'm baffled as to why and would appreciate any input people may have.

Also, I have a model of all the rails connected to the secondaries of their transformers in turn coupled through a soft start circuit to the mains. One odd thing I encountered with this larger model was that when I added caps to reflect the load capacitance each voltage rail needs to be able to service, the voltage rails produced saw tooth output until I added a very small amount of series resistance to the caps. Of course the load capacitance will have series resistance and likely a lot more than was needed to settle the sim, nonetheless I would be interested in an explanation as to why the addition of a small amount of ESR was needed to settle the voltages rails back to their behaviour prior to adding the load capacitance (or, rather, why adding capacitance with no ESR unsettled the rails).

Cheers

Steve
Attached Images
File Type: jpg 12V.JPG (478.1 KB, 1336 views)
File Type: jpg 12VNR.JPG (205.0 KB, 1264 views)
File Type: jpg 12VTR.JPG (143.3 KB, 1133 views)
File Type: jpg 12VOZ.JPG (238.3 KB, 1090 views)
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Old 16th October 2014, 04:33 PM   #2
Elvee is offline Elvee  Belgium
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Quote:
Originally Posted by SGK View Post
I am very puzzled by the output impedance analysis of this circuit. For loads less than 0.8A I get 'normal' looking output similar to the 5V and 3.3V rails. (That is, zero impedance rising to a peak of 6.3mOhms around 446kHz and then declining.) From a load of 0.85A and beyond I get the output in the image below (12VOZ). I'm baffled as to why and would appreciate any input people may have.
I guess that since the output current can pull the output to -∞V, it does funny things to the startup conditions of the reg.
Try a reverse schottky on the output, or in the startup conditions, check the start at 0 option, or use a resistor as a load
Quote:
Also, I have a model of all the rails connected to the secondaries of their transformers in turn coupled through a soft start circuit to the mains. One odd thing I encountered with this larger model was that when I added caps to reflect the load capacitance each voltage rail needs to be able to service, the voltage rails produced saw tooth output until I added a very small amount of series resistance to the caps. Of course the load capacitance will have series resistance and likely a lot more than was needed to settle the sim, nonetheless I would be interested in an explanation as to why the addition of a small amount of ESR was needed to settle the voltages rails back to their behaviour prior to adding the load capacitance (or, rather, why adding capacitance with no ESR unsettled the rails).
.Asc?
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Old 16th October 2014, 09:25 PM   #4
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Thanks Mark. I will take a closer read on Sunday when I am back home.

A quick scan suggests these references are related to my second question - is that correct?

I ran through all the phase margin testing on the 12V rail with the reg output caps and 100mA quiescent current generating resistor* in the sim, but I did not include the "load capacitance" in this work - in large part because the actual load capacitance is unknown and can only be guestimated or, as I did, one can assume the level in the ATX spec. A tiny amount of series resistance (I added just 40 or 50 milliOhms) cleared the issue in the full AC-driven PSU sim. When I did the phase margin tests with the circuit in post one (with the obvious required changes to break the loop etc for this analysis) I stepped the load and checked each increment and all was fine.

* I found I had to create a minimum current of 100mA as the circuit was unstable at very low loads. I figured the resister was the easiest way to get around this issue.
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Old 16th October 2014, 09:29 PM   #5
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Quote:
Originally Posted by Elvee View Post
I guess that since the output current can pull the output to -∞V, it does funny things to the startup conditions of the reg.
Try a reverse schottky on the output, or in the startup conditions, check the start at 0 option, or use a resistor as a load

.Asc?
The odd thing is the output impedance issue doesn't present itself in the 5V or 3.3V circuits. And, of course, there don't appear to be issues in noise rejection, phase margin and transient tests with a stepped load.

I will post a link to all my modelling work when I can get access to the file. The last version is stuck on my office PC with a copy sent home via an email that seems to be lost in our office security screening.
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Old 17th October 2014, 07:45 AM   #6
AndrewT is offline AndrewT  Scotland
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Does trace and wire inductance have much effect on regulator stability?

Could adding nominal values of trace inductance into the sim model give useful information?
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Old 17th October 2014, 08:41 AM   #7
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Elvee,

Here is a link to a zip folder of all my models. Within it is a sub folder for each of the 3 voltages. For each voltage there is a model for Loop Gain Stability, Noise Rejection, Output Impedance Analysis and Transient Analysis. The "5V with rectification" and "12V with rectification" files are now superseded by "All With Rectification" within the 3V3 folder; this includes the soft start circuit. (The Operating Point Analysis files are also superseded by this file.) Everything that is needed to run the models is in the relevant folder.

I'm about to drive out of town for the weekend so will read through Mark's links more carefully when I return on Sunday afternoon.

Cheers

Steve
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Old 17th October 2014, 09:25 AM   #8
Elvee is offline Elvee  Belgium
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OK, as I suspected the problem was caused by the start-up conditions: using a resistive load solved it.
As for the instability, the LT1084 doesn't seem to have any requirement on a minimum ESR, but since you have hugely increased the loop gain with the TL431, it could become an issue.
The large cap value may also trigger the current limit and cause strange interactions
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File Type: jpg SGK1.jpg (424.7 KB, 1019 views)
File Type: jpg SGK2.jpg (466.7 KB, 254 views)
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Old 17th October 2014, 09:48 AM   #9
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Originally Posted by Elvee View Post
OK, as I suspected the problem was caused by the start-up conditions: using a resistive load solved it.
Meaning it is a LTspice peculiarity? Odd that it doesn't appear in the other rails which use the same load configuration. Must be something more to it, no?

On the second pic, it is not possible to see the change you made but I assume you removed the 50 milliOhms of ESR from the load capacitance. The oscillation was driving me nuts until I realised I had just dropped in a perfect cap and so tried a little ESR. (The load capacitance was added to observe in-rush conditions. It's obviously not part of the PSU rail.) I'm sure Mark's links will provide the detailed explanation as to why. The many capacitors on the board being powered will easily fulfil that requirement (and the level of stabilising ESR may well be lower - I've not solved for the threshold level).
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Old 17th October 2014, 10:12 AM   #10
Elvee is offline Elvee  Belgium
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Quote:
Originally Posted by SGK View Post
Meaning it is a LTspice peculiarity? Odd that it doesn't appear in the other rails which use the same load configuration. Must be something more to it, no?
Yes and no: in real life, there is little chance the load is a current sink capable of going to 0V and beyond, but if it happened to be, you'd observe the same kind of behavior.
Note that with the real circuit, the startup might end to be much trickier that it is in sim, and it is possible it won't even start with a resistive load

Quote:
On the second pic, it is not possible to see the change you made but I assume you removed the 50 milliOhms of ESR from the load capacitance. The oscillation was driving me nuts until I realised I had just dropped in a perfect cap and so tried a little ESR. (The load capacitance was added to observe in-rush conditions. It's obviously not part of the PSU rail.) I'm sure Mark's links will provide the detailed explanation as to why. The many capacitors on the board being powered will easily fulfil that requirement (and the level of stabilising ESR may well be lower - I've not solved for the threshold level).
Yes, I removed the resistance. In reality, the capacitors and wiring will probably amount to more than that, thus normally no problem to be expected, but unpleasant surprises are always possible
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