Hello,
Do you think my mosfet gate drive transformer is designed using the right core, a good winding strategy and good choice of primary inductance of the gate drive transformer?………………………
Its for a Class B amplifier supply
I am designing a mosfet gate drive transformer for a 330W two transistor forward converter.
Vin = 385VDC.
Switching frequency = 85KHz.
Its for the upper FET only.
I have decided to use the EFD 20/10/7 ferrite core using N87 ungapped ferrite. (B66417G0000X187).
EFD 20/10/7 Datasheet:-
http://www.epcos.com/inf/80/db/fer_07/efd_20_10_7.pdf
I will use 16 turns on primary and secondary, and even though there is going to be 400V between the primary and secondary, I will wind primary and secondary bifilar using standard enamelled copper wire…..eg as follows….
Enamelled copper wire:-
http://www.farnell.com/datasheets/1633613.pdf
The 16 turns gives an inductance of 307uH. This is not much, but it will mean a low value of leakage inductance……..because…..
..With most ferrite transformers, its extremely difficult to get the leakage inductance below 0.1% of primary inductance……..i need the leakage inductance to be less than 350nH, so therefore I need my primary inductance to be less than 350uH……do you agree?
……unfortunately the low-ish primary inductance of the gate drive transformer means that the magnetising current in the gate drive transformer will be high-ish, which means that the bias winding on the main power transformer will have to supply this high-ish current….and during start-up, the Controller’s Vcc capacitor will have to be large to allow the bias winding to start supplying before the controller Vcc falls beow the UVLO level….this will also mean a longer start-up time unfortunately.
While simulating the Two Transistor Forward SMPS, I found that any more than 350nH of leakage inductance in the gate drive transformer leads to excessive switching losses.
Anyway, do you think my modus operandi is good?
……Will I be ok with the minimal isolation between primary and secondary windings of the gate drive transformer.?
……Is my theory about having L(pri) of the gate drive transformer no greater than 350uH a good one?
…….Is my choice of ferrite core good enough to allow low leakage inductance?
Do you think my mosfet gate drive transformer is designed using the right core, a good winding strategy and good choice of primary inductance of the gate drive transformer?………………………
Its for a Class B amplifier supply
I am designing a mosfet gate drive transformer for a 330W two transistor forward converter.
Vin = 385VDC.
Switching frequency = 85KHz.
Its for the upper FET only.
I have decided to use the EFD 20/10/7 ferrite core using N87 ungapped ferrite. (B66417G0000X187).
EFD 20/10/7 Datasheet:-
http://www.epcos.com/inf/80/db/fer_07/efd_20_10_7.pdf
I will use 16 turns on primary and secondary, and even though there is going to be 400V between the primary and secondary, I will wind primary and secondary bifilar using standard enamelled copper wire…..eg as follows….
Enamelled copper wire:-
http://www.farnell.com/datasheets/1633613.pdf
The 16 turns gives an inductance of 307uH. This is not much, but it will mean a low value of leakage inductance……..because…..
..With most ferrite transformers, its extremely difficult to get the leakage inductance below 0.1% of primary inductance……..i need the leakage inductance to be less than 350nH, so therefore I need my primary inductance to be less than 350uH……do you agree?
……unfortunately the low-ish primary inductance of the gate drive transformer means that the magnetising current in the gate drive transformer will be high-ish, which means that the bias winding on the main power transformer will have to supply this high-ish current….and during start-up, the Controller’s Vcc capacitor will have to be large to allow the bias winding to start supplying before the controller Vcc falls beow the UVLO level….this will also mean a longer start-up time unfortunately.
While simulating the Two Transistor Forward SMPS, I found that any more than 350nH of leakage inductance in the gate drive transformer leads to excessive switching losses.
Anyway, do you think my modus operandi is good?
……Will I be ok with the minimal isolation between primary and secondary windings of the gate drive transformer.?
……Is my theory about having L(pri) of the gate drive transformer no greater than 350uH a good one?
…….Is my choice of ferrite core good enough to allow low leakage inductance?
Treez,
first off: this looks like a reasonable design. you're thinking about the right things.
the big question: how many volt-seconds (absolute max) will you stick on the primary? in other words whats the peak magnetising current, and hence the energy stored (wasted) in your gate drive transformer core.
If your gate drive transformer saturates - kaboom.
You're a bit off wrt leakage. yes its important, your sims are bang on. but your thinking wrt Lmag is not quite right (damn near there though).
Leakage is uncoupled inductance. You can show this by measuring leakage, removing the core then doing it again. the measured value does not change.
this means that L_leak is independant of the core permeabilty - it depends only on winding geometry and the number of turns.
And Bifilar is the best way to minimise it. Keeping N low also minimises leakage as you note, but has the downside of reducing Lmag. [edit: terribly worded. L_leak is proportional to N^2, as is Lmag. so you're bang on - keep N and hence Lmag as low as you can tolerate, based on the driver circuitry itself. THEN use either bifilar (best) or interleaving to maximise coupling]
Lmag is coupled through the core, so the actual value depends entirely on core permeability. This means that expressing leakage inductance as a percentage of Lmag isnt very helpful at all.
If you use a high-perm material, eg W or 3E25, Lmag will be about 5-6 times higher than if you use a power ferrite. the leakage inductance wont change (you've changed the core, not the physical winding), but the % leakage will (because Lmag changed).
Lmag is an annoying "parasitic" - ideally it would be very large and you can ignore it.
many gatedrive transformers use the high-perm materials like W, 3E25 etc. this keeps Lmag high and Imag low. you need to ensure two things:
1. the gatedrive xfmr core doesnt saturate - hence my volt-seconds question (Vin*Ton).
2. your circuitry driving it can deal with whatever Lmag/Imag ends up being.
the high perm materials have lower Bsat than power ferrites, but perm. is much, much higher - which is why they are used.
a split-core (eg EFD) always has some air gap, which will nobble the actual permeability somewhat - depending on how tight you clamp the core halves together. and it might drop perm. by 30% or more. a toroid always has maximum permeability, but is a PITA to wind.
as far as isolation: I would use TIW (eg Rubadue or Furukawa Tex-E) but thats hard to get hold of. make sure you use heavy-build or triple-dipped magnet wire, and pick a really tough insulation like polyamide-imide. it has to be mechanically stripped, but a scalpel or dremel works ok there.
and make damn sure to hipot test your xfmr - if you damage the insulation this will spot it, and is cheaper than blowing up your SMPS.
first off: this looks like a reasonable design. you're thinking about the right things.
the big question: how many volt-seconds (absolute max) will you stick on the primary? in other words whats the peak magnetising current, and hence the energy stored (wasted) in your gate drive transformer core.
If your gate drive transformer saturates - kaboom.
You're a bit off wrt leakage. yes its important, your sims are bang on. but your thinking wrt Lmag is not quite right (damn near there though).
Leakage is uncoupled inductance. You can show this by measuring leakage, removing the core then doing it again. the measured value does not change.
this means that L_leak is independant of the core permeabilty - it depends only on winding geometry and the number of turns.
And Bifilar is the best way to minimise it. Keeping N low also minimises leakage as you note, but has the downside of reducing Lmag. [edit: terribly worded. L_leak is proportional to N^2, as is Lmag. so you're bang on - keep N and hence Lmag as low as you can tolerate, based on the driver circuitry itself. THEN use either bifilar (best) or interleaving to maximise coupling]
Lmag is coupled through the core, so the actual value depends entirely on core permeability. This means that expressing leakage inductance as a percentage of Lmag isnt very helpful at all.
If you use a high-perm material, eg W or 3E25, Lmag will be about 5-6 times higher than if you use a power ferrite. the leakage inductance wont change (you've changed the core, not the physical winding), but the % leakage will (because Lmag changed).
Lmag is an annoying "parasitic" - ideally it would be very large and you can ignore it.
many gatedrive transformers use the high-perm materials like W, 3E25 etc. this keeps Lmag high and Imag low. you need to ensure two things:
1. the gatedrive xfmr core doesnt saturate - hence my volt-seconds question (Vin*Ton).
2. your circuitry driving it can deal with whatever Lmag/Imag ends up being.
the high perm materials have lower Bsat than power ferrites, but perm. is much, much higher - which is why they are used.
a split-core (eg EFD) always has some air gap, which will nobble the actual permeability somewhat - depending on how tight you clamp the core halves together. and it might drop perm. by 30% or more. a toroid always has maximum permeability, but is a PITA to wind.
as far as isolation: I would use TIW (eg Rubadue or Furukawa Tex-E) but thats hard to get hold of. make sure you use heavy-build or triple-dipped magnet wire, and pick a really tough insulation like polyamide-imide. it has to be mechanically stripped, but a scalpel or dremel works ok there.
and make damn sure to hipot test your xfmr - if you damage the insulation this will spot it, and is cheaper than blowing up your SMPS.
Thanks Terry, thats great reading.
I am using a UCC38C44 controller which has maximum 50% duty cycle, and gate drive voltage is 14V, so maximum v.us = 82e-6.
The actual maximum duty cycle (at maximum load) is 0.23, so mostly, the v.us will be just 37.8e-6.
...however, i am not so sure, but believe that i need to be prepared for the 82e-6 v.us product, as during transients, and at start up, this will occur?
I am using a UCC38C44 controller which has maximum 50% duty cycle, and gate drive voltage is 14V, so maximum v.us = 82e-6.
The actual maximum duty cycle (at maximum load) is 0.23, so mostly, the v.us will be just 37.8e-6.
...however, i am not so sure, but believe that i need to be prepared for the 82e-6 v.us product, as during transients, and at start up, this will occur?
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Honestly I'd be scared to use a gate drive transformer here, fed by varying duty cycle from modulator, that is different from e.g. half bridge, where GDT is fed by positive-zero-negative (no DC) waveform. A series cap is a must and so is volt-seconds headroom.
Why not use a bootstrap high side driver?
Why not use a bootstrap high side driver?
Treez,
you pretty much knew this already, and Rikkitikkitavi confirmed it. standard engineering really - plan for the worst, hope for the best.
and like Rikkitikkitavi also says, make sure you reset your gatedrive transformer (aka ensure GDT Imag returns to zero) to prevent staircase saturation.
If you capacitively couple into your gatedrive transformer, you need to capacitively couple thwe output and have a "dc restorer" diode - see app note SLUP169 by Laszlo Balogh, or AN1 by Fritz Schundler (message me your email addy and I'll send the PDFs, 346k & 1M5 if you cant find them)
here's a fun thought though. the UC3844 has a 50% duty cycle limit (T-FF). you could drive the GD xfmr with a diagonal half-bridge. UC3844 OP to DOT end of GDT primary, FET to 0V on the other end of the primary winding, and a diode to Vcc. drive the FET from the UC3844 output too.
UC3844 op high - GDT primary Dot end = high, GDT FET on so other end low => +v pulse out, i_mag ramps up.
UC3844 OP low: - GDT primary Dot end = low, GDT FET off => Lmag commutates to diode =) -ve pulse out (same amplitude as +ve pulse) and i_mag ramps down.
you pretty much knew this already, and Rikkitikkitavi confirmed it. standard engineering really - plan for the worst, hope for the best.
and like Rikkitikkitavi also says, make sure you reset your gatedrive transformer (aka ensure GDT Imag returns to zero) to prevent staircase saturation.
If you capacitively couple into your gatedrive transformer, you need to capacitively couple thwe output and have a "dc restorer" diode - see app note SLUP169 by Laszlo Balogh, or AN1 by Fritz Schundler (message me your email addy and I'll send the PDFs, 346k & 1M5 if you cant find them)
here's a fun thought though. the UC3844 has a 50% duty cycle limit (T-FF). you could drive the GD xfmr with a diagonal half-bridge. UC3844 OP to DOT end of GDT primary, FET to 0V on the other end of the primary winding, and a diode to Vcc. drive the FET from the UC3844 output too.
UC3844 op high - GDT primary Dot end = high, GDT FET on so other end low => +v pulse out, i_mag ramps up.
UC3844 OP low: - GDT primary Dot end = low, GDT FET off => Lmag commutates to diode =) -ve pulse out (same amplitude as +ve pulse) and i_mag ramps down.
integrated half-bridge drivers: these work really, really well. IFF (if and only if) you have a good layout. I designed a 50W DHB forward converter running from 24...60VDC using half-bridge driver ICs in 2002, and we built 100,000 or so (planar magnetics too).
you can get away with a lousy layout at low voltages, but try that at high voltages and/or high power (big fields) and expect explosions. true story: in the 1990s IR tried to sell us on HV half-bridge driver ICs for use in AC motor controllers (we made them from 0.5kW - 1MW). they gave us a demo board, we ran it and it blew up straight away (self-removing IC). end of consideration. turned out they did a lousy layout on their own demo board, and got this embarassing result more than once. oops.
you can get away with a lousy layout at low voltages, but try that at high voltages and/or high power (big fields) and expect explosions. true story: in the 1990s IR tried to sell us on HV half-bridge driver ICs for use in AC motor controllers (we made them from 0.5kW - 1MW). they gave us a demo board, we ran it and it blew up straight away (self-removing IC). end of consideration. turned out they did a lousy layout on their own demo board, and got this embarassing result more than once. oops.
Terry: I sincerely did few things using this chips, only a Class D audio amplifier powered from +-12V actually jobbing in this PC, because is what I had at hand, I work repairing industrial and medical electronics, and thousands of them I had seen in several circuits working very properly, normally between few KHz to a 200KHz. But I believe it is simpler and cost effective than make a transformer driver. Moreover in case of this guy that will drive one FET directly and other from transformer, I had seen those topology but I dislike it. I prefer that both FET´s driven from the xformer or from IR´s, for timing balance between them.
Osvaldo,
yep. they really do work. perhaps the biggest disadvantage is that if and when it goes bang, the trail of destruction can reach back into the isolated side. of course thats also true when you have a low-side switch thats directly driven.
like most things: done properly they work well. done badly they dont. for all values of "they".
you make a great point about matched drive paths. for any type of half-bridge power stage this is CRUCIAL. I cannot emphasise that enough, and you win todays internet for pointing it out. Because half-bridges have a built-in self-destruct mode (turning high- and low-side switches on together). Interlock is your friend (IGBTs are a good way to find this out, as they dont like turning off).
the diagonal half-bridge is a great topology for several reasons, one of which being that its immune to this failure mode (its the operating mode). and because nothing turns on until both switches are on, but it turns off when the first switch does, it can tolerate huge variations in gate drive timing with essentially no change in performance. I once designed a 2MHz DHB converter that drove the high-side switch from the low-side winding - it used the primary as its own level shifter, so only needed low-side drive. 24V in, using bipolar transistors, and only a few watts. we made about 300,000 or so.
yep. they really do work. perhaps the biggest disadvantage is that if and when it goes bang, the trail of destruction can reach back into the isolated side. of course thats also true when you have a low-side switch thats directly driven.
like most things: done properly they work well. done badly they dont. for all values of "they".
you make a great point about matched drive paths. for any type of half-bridge power stage this is CRUCIAL. I cannot emphasise that enough, and you win todays internet for pointing it out. Because half-bridges have a built-in self-destruct mode (turning high- and low-side switches on together). Interlock is your friend (IGBTs are a good way to find this out, as they dont like turning off).
the diagonal half-bridge is a great topology for several reasons, one of which being that its immune to this failure mode (its the operating mode). and because nothing turns on until both switches are on, but it turns off when the first switch does, it can tolerate huge variations in gate drive timing with essentially no change in performance. I once designed a 2MHz DHB converter that drove the high-side switch from the low-side winding - it used the primary as its own level shifter, so only needed low-side drive. 24V in, using bipolar transistors, and only a few watts. we made about 300,000 or so.
The major problem with all bridges , timing is essential or you will have a big bang on the bridge where everyone meets
A question though, diagonal half-bridge, is it same as two-transistor forward? Like in the other topic we are discussing
I e it drives the transformer in an unipolar fashion and you have two catch diodes taking care of reset and any leakage inductance voltage spikes?
Doesn't that happen in a bridge also?
The mosfets internal diode takes care of those as in TTForward?
And if not, why not?
I c...
Any recomendations for core reset diodes for a TTForward?
I would expect an ordinary 4148 to blow in no time - but would be fast enough at least (max 100V limited off course)? How much current exactly are we talking about here in such a fact of the matter?
Any known formulas for calculations?
Any recomendations for core reset diodes for a TTForward?
I would expect an ordinary 4148 to blow in no time - but would be fast enough at least (max 100V limited off course)? How much current exactly are we talking about here in such a fact of the matter?
Any known formulas for calculations?
the diode catches the magnetising energy + any energy stored in leakage inductances , and they should be fairly small so powerwise not so big. But I have seen 3-400 W single switch forwards where the catch diode is bolted to the heatsink...
peak power can be.huge though , as they are fast. very fast...
I would say though that about 1-2 amps Iavg rating is sufficient. Voltage rating as for for the mosfets. But dont.take my word for it without.some simulations or experience to back it up.
peak power can be.huge though , as they are fast. very fast...
I would say though that about 1-2 amps Iavg rating is sufficient. Voltage rating as for for the mosfets. But dont.take my word for it without.some simulations or experience to back it up.
I havw simulated the circuit in Fritz schundlers report and.it works nicely but when shutting.of .drive , the leakage inductance forms a resonance with the.coupling caps , causing the powerFET to turn on a few times over a few ms., on time quite undefined.
what this means is catastrophic failue in the FET by enormous currents. I think this needs a pnp shorting out stored energy in the cap. i have a app note mentioning the problem but not why, how . see if I can dig it up.
what this means is catastrophic failue in the FET by enormous currents. I think this needs a pnp shorting out stored energy in the cap. i have a app note mentioning the problem but not why, how . see if I can dig it up.
The major problem with all bridges , timing is essential or you will have a big bang on the bridge where everyone meets
A question though, diagonal half-bridge, is it same as two-transistor forward? Like in the other topic we are discussing
I e it drives the transformer in an unipolar fashion and you have two catch diodes taking care of reset and any leakage inductance voltage spikes?
Yes, it is. You can draw the TTForward converter as a bridge converter with two switches and two diodes. the active switches are on opposite diagonals, as are the passive switches (diodes). IOW if you replace two diagonal switches in a full bridge with diodes, you get the Diagonal Half-Bridge aka Two-Transistor Forward converter.
and yes the diodes clamp both leakage and mag current. assuming its a forward converter. a DHB flyback (works great, almost no leakage loss) has the constraint that the flyback voltage must be less than the input voltage, else all the stored (mag.) current gets returned to the input supply.
[edit: duh, forward has same constraint on Vout & turns ratio]
as for the diode current: the actaul current depends on the topology (forward or flyback), but in either case the following statement is always true:
The leakage inductance is in series with the switch(es) and the parallel combination of magnetising inductance and reflected load impedance
Therefore when the primary switch(es) turn off, the current stored in the leakage inductance is simply the switch current at turn-off (so the peak switch current). Always. every single time. CCM or DCM. the leakage is in series with the switch....
In a flyback the secondary diode is off, so there is no reflected load and the leakage inductance current is the peak magnetising current + any DC offset if its in CCM. which is of course the peak switch current at turn-off.
In a forward converter the secondary diode is on, so the leakage inductance current is the peak magnetising current + the reflected output inductor current. which is of course the peak switch current at turn-off.
and lastly, with a relay catch diode - same thing. the relay diode current is whatever the relay current was just before it turned off. I dont know why, but I could never figure this out when I was a technician, or studying for my degree. but about 1 month into my first real job, I asked one of the technicians about it, and got told in no uncertain terms how it worked. with an exasperated "how much work is this idiot going to make for me" tone of shouting. That got through my thick head. I must have fitted thousands of 1N4007 catch diodes to 30mA 12V relays and coin counters over the years......
these questions can also be answered using one of Maxwells equations. which is simply "current flows in loops". draw the circuit, explicitly showing ground and power connections, then trace the loop the current flows in.
The clamp diode duty cycle is pretty low though - with a DCM flyback its Ton*(L_leak/Lmag) because the clamp voltage is the supply, and the switch current at turn-off is only magnetising current. so if the leakage is 2% of the mag current, the diode conduction time will be about 2% of the on time.
so it has to be a fast diode.
with a CCM flyback that goes up because of the stored (magnetising) current. And in the forward converter it has a similar increase due to the reflected output inductor current.
regardless of topology, the diode conduction time is always given by:
Tdiode*Vsupply = L_leakage*I_switch_peak
because the diode conduction time is small, you can use quite a small diode. In a flyback with 3% leakage and Ipeak = 4A I use 1A 35ns diodes for my leakage clamp (same reasoning applies). I got all carried away and did a transient thermal analysis, but simple calculations work pretty well.
for two clamp diodes, each diode dissipates about 0.5*I_switch_peak*Vdiode*Tdiode*Fsmps watts. if you want you can use (Vf + I*Rdiode) instead of Vdiode, but if you use Vdiode at I_switch_peak then you've got a bit of margin.
just make sure the diode Ifsm >> I_switch_peak. you can happily use a diode with Iavg = I_switch_peak/2 and ignore pretty much all calculations.
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I have fiddled around a bit with some ferrite toroids used in common mode filters, they have fairly high Al, in the range 8-10000 nH/n^2 (at low flux , even very low)
Would they be suitable for a good GDT or is the material to lossy ?
in general, these came out of a broken ATX supply, CE marked (chinese equipment) so I have no more data.
Would they be suitable for a good GDT or is the material to lossy ?
in general, these came out of a broken ATX supply, CE marked (chinese equipment) so I have no more data.
Rikkitikkitavi,
high perm cores are often used for GD transformers, precisely because they are high perm. which increases the (parasitic) magnetising inductance, thereby reducing the (parasitic) magnetising current.
As always you need to make sure the core doesnt saturate - and Bsat varies with temperature, anywhere from quite a bit to a whole lot. And as you suggest, you also have to keep the losses under control.
its easy if you know the exact material - read the datasheet. harder for a random core.
you can easily check saturation at high temperature with a heat gun and a splat test (fairly large cap charged to some V, "splatted" across the winding while you measure V & I. If V is pretty constant then dI/dt = current slope = V/L, and you'll see it saturate quite clearly).
losses are harder to measure though. if you build a diagonal half-bridge driver stage and run it at just under 50% duty cycle, with no load on the secondary (or even a secondary) then you will make the mag current ramp up then back down, repeatedly. bypass the supply with a reasonable sized cap, then measure the DC power drawn by the primary driver. that'll give you a reasonable idea of the losses, and you can also measure the temperature rise.
high perm cores are often used for GD transformers, precisely because they are high perm. which increases the (parasitic) magnetising inductance, thereby reducing the (parasitic) magnetising current.
As always you need to make sure the core doesnt saturate - and Bsat varies with temperature, anywhere from quite a bit to a whole lot. And as you suggest, you also have to keep the losses under control.
its easy if you know the exact material - read the datasheet. harder for a random core.
you can easily check saturation at high temperature with a heat gun and a splat test (fairly large cap charged to some V, "splatted" across the winding while you measure V & I. If V is pretty constant then dI/dt = current slope = V/L, and you'll see it saturate quite clearly).
losses are harder to measure though. if you build a diagonal half-bridge driver stage and run it at just under 50% duty cycle, with no load on the secondary (or even a secondary) then you will make the mag current ramp up then back down, repeatedly. bypass the supply with a reasonable sized cap, then measure the DC power drawn by the primary driver. that'll give you a reasonable idea of the losses, and you can also measure the temperature rise.
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