Power Supply Resevoir Size

[Nico Ras]

Increasing the cap size means you droop less. Increasing the transformer voltage means you start higher up. Both mean your minimum voltage is raised. Once the capacitor droop becomes a small proportion of the total voltage drop, as is the case here, then a small increase in transformer voltage does more than a big increase in cap value. This was made clear in the thread, on several occasions.

Am I providing free consultancy for a commercial product development?

I provide paid for consultancy, thus I remain responsible for the outcome.. I would never trust a DIY doctor if he does not charge me for a professional service.

 

[jacco vermeulen]

I don't trust the doctors that do charge either.

 

[gootee]

Since I am doing all of this for free, anyway, I would prefer to see the results applied to the development of a commercial product. I am happy for all of the diyers too. But helping someone make a better product, and a profit, is even more gratifying. And if we can also help Nico to look better professionally, and make more money, I can't see any downside to that. Nico did mention, a long time ago, what his intentions were.

 

[gootee]

this bounding case is seen as clipping of the signal.
We can see that easily on a scope with both sinewave and with music.
There is a tertiary case: The signal gets progressively more distorted as clipping is approached. I have seen FFT plots showing the increase of high harmonics as clipping is approached. I suspect this tertiary case is showing the effect of non linearity of the amplifier as Vce of some devices becomes similar to Vbe or even worse becomes less than Vbe. As device Vce approaches zero, then we see the bounding case of clipping.

Actually, it would be well-before Vce gets to zero. It would be Vceomin instead of zero, wouldn't it? The amplifier has to have the transistor's minimum voltage plus the voltage across the low-value resistor. If that voltage space is violated, by a ripple voltage minimum dipping into it from above, it will gouge a ripple-shaped chunk out of the output signal's waveform.

 

[gootee]

Tom/DF/Frank,

following is a set of practical measurements from our latest commercial development. After the amplifier design was finalized and frozen the power supply was optimized with the objective that started this thread. The amp is essentially 100 watt into 8 Ohm and I will qualify this so that we are all aware of the criteria used to obtain the results.

The measurement was intended to detect any artifacts in the output signal compared to the input signal added by the amplifier while delivering the rated rms voltage across an 8.2 Ohm resistive load at 20 Hz sine wave input stimulus(mains =50Hz; 240VAC).

The observations were made by comparing the signals between the inverted (NFB) and non-inverted inputs of the amplifier under test using a scope with A-B and dB meter at rated output nulled at 1kHz as reference output.

The amplifier uses four pairs of L-MOSFET as output devices and 0.22 ohm non-inductive drain resistors. There is no current limit applied, no "zobel" across the output nor any series output inductor.

6.3 mm spade terminals were crimped to the caps so that we could connect several in parallel onto an 8 x 8mm copper, positive and negative rail.

A 35 Amp soft recovery fast bridge rectifier type SRDB-3500P-1A was used between the transformer and reservoir without any capacitors across the diodes. We used multiple Hitano ELP range 4700 uF/100V 30 mm diam caps to arrive at an observed optimum value.

We used the same 368VA toroidal transformer wound to supply 36 - 0 - 36 to 46V - 0 - 46 VAC at 2 V intervals (taps) for all measurements.

Our method consisted to set a transformer voltage by connecting to the lowest tap, then starting with 4700uF, and increase the capacitance until the differential voltage on the scope/meter was as low as possible.

If after adding further caps the difference was hard to detect we removed the last cap and returned to the 1 kHz reference signal to make sure this has either improved or remained the same as before.

We then stepped to the next transformer voltage and incremented the capacitance by 4700uF until we reached the point that an observed improvement was uncertain and so on.

The instruments used for this exercise was HP 54645A scope, HP 33120A function generator and HP 33401A multimeter.

The final results was achieved by using four paralleled 4700uF capacitors per rail and 42V setting on the transformer which was higher than one would expect the rail to be for a 100 watt amplifier. In fact the max average power measured with the final settings was 132 watt into 8 ohm (to produce the optimum performance at 100 watt which we find interesting)

Tom/DF/Frank can these observations be verified by any of the theoretical scenario?. There is still a lot of measurements and tests before the amp goes to production, thus I will perform other measurements you may require such as transformer inductance or what-ever is needed to plug into the formulas.

I will not divulge the schematic but it consists of a typical Hitachi topology using double differential amps driving L-MOSFETs, you all know the topology.

I will get back to you in a few hours for more information but your results seem very consistent with everything we have learned here so far.

 

[Telstar]

I don't trust the doctors that do charge either.

 

[gootee]

Nico,

Did you try it with speakers and music, yet???

What is the gain, or what was the amplitude of the 20 Hz sine wave input?

What peak and RMS voltages do you see across the MOSFET and resistor, total, with the 20 Hz sine input?

It would be useful if you could measure the transformer parameters, per the procedure at the beginning of the transformer tab in the spreadsheet, for your 42V case. You would probably need a variac (variable transformer).

Do you have a way to measure the ESR of the 4700 uF caps at different frequencies (e.g. 20 Hz), or have some spec?

I can't think of anything else I might need to be able to simulate certain aspects of it, at the moment.

It would be interesting to see the rest of the uF vs Vrms data points that you found, and maybe the A-B measures for them.

Regards,

Tom

 

[gootee]

If the ripple calculation assumes the worst-case current draw, as it should, then no music current will exceed this. Music at frequencies higher than the (doubled) supply frequency are guaranteed to draw less than the worst case, as for part of the time between charging pulses the music will be drawing current from the other supply rail. Music at frequencies lower than this can only draw the worst case current, and no more. I think we are agreeing?

The only exception to this would occur if capacitor stray inductance (+wiring) caused extra voltage drop for higher frequencies, but in reality this inductance is just as likely to reduce the voltage drop across much of the audio range as it has the opposite sign to the capacitive reactance. Naive bypassing could screw this up, but people using naive bypassing are unlikely to do ripple calcs anyway.

Now if the final PSU cap is well separated (electrically) from the reservoir cap (e.g. by a choke) then the ripple requirements for the reservoir cap and the music current requirements for the final cap get partly decoupled. We can assume the final cap gets fed with a DC current which on average is exactly right to meet music current requirements. The problem now is that the voltage drop in the final cap has to be added on to the average DC droop (i.e. half the maximum droop) in the reservoir cap. We can no longer count on the charging pulse to reset things every 10ms so low frequency requirements are more demanding. So if you have LC smoothing and you want good bass then the final cap may need to be larger than you would need for a single reservoir cap, as it may need to supply current for 25ms (half a cycle at 20Hz) rather than 10ms.

I am getting ready to order 200 electrolytic capacitors, to create two 10x10 "Terry Given" cap-arrays on two 150x203mm two-sided 1mm-thick FR4 PCBs. The 1000uF Nichicon UHE-series caps are 12.5mm diameter max. But the rows of caps will be offset, so the rows can be a little closer than 12.5mm + spacing. But I wan't sure I needed to use 1000 uF caps and wondered if I could possibly use the next-smaller diameter, 10mm.

Unfortunately, the largest 50V value that's 10mm is 470 uF. And their ESR is 2X the ESR of the 1000 uF.

Anyway, I thought that I might as well see what I come up with when calculating the capacitance needed to fully-support perfect bass down to 20 Hz.

My capacitor arrays will function as both the PSU and decoupling caps, because they will fill the space between the rectifiers and the amplifier's output stage. I will most-likely be mounting the output devices (probably a chipamp for initial testing) on a parallel PCB, as close as possible to the rear side of the cap array PCBs (like, 3 mm, but I might try to make it 0 mm, or use some extremely low-inductance connection method; I would hate to get 0.5 nH inductance from the array and then throw any of it away with a stupid connection method). I will place the amp pcb over the junction of the adjacent edges of the two array pcbs (one for each rail), so that the power and ground pins can go directly into the cap array boards' power and ground planes.

If I calculate what would be needed for a full 20 Hz half-cycle without any charging pulses available for 25 ms, then it should be more than enough to be sufficient for most real music, and even for continuous DC at the full peak output voltage, when there ARE charging pulses.

OK. For a 20 Hz sine, if we use:

(17a): C ≥ Δi / ( πf∙(Δv - (ESR∙Δi)))

which is 2x equation (17), to consider the whole half-cycle,

and we use an estimate for the ESR:

ESR = 0.02 / (C x VR), where VR = Voltage Rating of capacitor

and substitute that into (17a), we get:

(18a): C ≥ Δi ((0.04πf / VR) + 1) / (πf∙Δv) [approximate, for electrolytic cap, only]

If we assume that we want Dpct percent voltage droop, then

(19a): Δv = Vsupply∙Dpct/100

and if we leave Vamp Volts for the minimum voltage across the power amplifier, the peak usable output voltage would be:

(20a): Vpk = (Vsupply - Vamp)(1 - (Dpct/100))

and then, with Rload,

(21a): Δi = Vpk/Rload = ((Vsupply - Vamp)(1 - (Dpct/100)))/Rload

We could get an equation for the minimum required capacitance in terms of Vsupply, Dpct, Rload, and the cap's voltage rating VR, by substituting (19a) and (21a) into (18a).

EXAMPLE:

Say we want a 100 Watt RMS sine output power spec, into 8 Ohms. We would need the usable peak voltage to be

(22a): V_usable_pk = sqrt(2∙Rload∙Power_rms)

The minimum power supply peak voltage would then need to be

(23a): Vmin_psu >= (V_usable_pk + Vamp)/(1 - Vripple_percent)

Vmin_psu >= (sqrt(2∙8∙100) + 4)/(0.975) [assuming 2.5% max ripple]

Vmin_psu >= 45.13 V (peak) = 31.91 V RMS minimum transformer secondary rating for 100 Watts into 8 Ohms (or more, if more than 2.5% ripple were allowed) [NOTE that transformer regulation and AC Mains deviations were NOT taken into account.]

So, we will, for now, assume that we can use capacitors rated at VR = 50 VDC, which we will do because lower VR gives a worse case, i.e. larger required C, than higher VR does.

V_usable = 40V peak = 28.28 V RMS

The load current will swing 5 Amps when the voltage across the load swings 40 V. So use Δi = 5 Amps.

Using equation (18a):

C >= (83577 uF) / Δv

Estimated ESR was .02/(.083577 x 50) = 0.0048 Ohm. That appears to be reasonable since an 8200 uF 50V cap was quoted (at mouser.com) as having ESR = 0.04 Ohm and ten of those in parallel would be about 0.004 Ohm.

For 2.5% voltage droop (ripple) with 40 V, Δv = 1 V, giving C >= 83577 uF.

Allowing 10% ripple would give C >= 20900 uF.

Just to check the worst-case upper bound, a square wave, or DC, for 25 ms at 40 V output would require

C >= Δi Δt / Δv (without taking ESR into account)

C >= 5(0.025)/1 = 125000 uF [ = 1.5 * 83577 uF ]

Or, with the same ESR approximation as was used above:

C ≥ (Δi / Δv)∙(Δt + (0.02 / Vrating)) (approximation, for electrolytic capacitors ONLY; NOTE: Used 2x, for DC instead of linear ramp.)

C >= (5/1)(.025+(.02/50)) = 127000 uF

That means that with charging pulses every 10 ms, only 127000(10/25) = 50000 uF should be sufficient, to handle continuous DC output at the rated peak voltage of 40V, without allowing more than 2.5% rail-voltage droop.

So 82000 uF should be enough for a single 20 Hz sine of 100 Watts into 8 Ohms, with <= 2.5% ripple, without being recharged for a full 25 ms half-cycle of 20 Hz.

If being recharged every 10 ms, 33431 uF should be sufficient (i.e. (10ms/25ms)*83577 = 33431), for a single sine, at the maximum rated output power.

So my planned 10x10 array of 1000 uF caps (100000 uF) will be fairly-massive overkill, for 100 Watts into 8 Ohms. But what about 4 Ohms? It turns out that 100000 uF is exactly the minimum required C to supply a continuous 10 Amps of DC current at 40 Volts DC, into 4 Ohms across the output, with less than 2.5% rail voltage droop, if charging pulses occur every 10 ms, and 200 Watts into 4 Ohms only requires 7.07 Amps RMS. So the 10-Amp peaks required for that should be effortless, for these arrays.

The cost of the caps is still worrying me, a little. If I used two arrays per channel, that would be 400 caps. Might as well go for the Qty 500 price break and use 11x11 arrays, in that case. Still, it's a few hundred dollars. Maybe I will think a little longer about either using smaller arrays or smaller-value caps.

Cheers,

Tom

 

[a.wayne]

I don't trust the doctors that do charge either.

Agree Dutchie ....

@Gootee,

Whats the anticipated ripple voltage at full output and what min-z value are you using to determine values, surely not 8ohm ..?

 

[abraxalito]

Unfortunately, the largest 50V value that's 10mm is 470 uF. And their ESR is 2X the ESR of the 1000 uF.

Have a look at Rubycon ZL range - that's showing 330uF/50V in 10mm with a max 100kHz impedance of 28mohm. In my limited experience of extreme paralleling of caps, I found going above 330uF to be problematic in that the self-resonant freq comes down a bit too low for comfort. I doubt when paralleling 100 caps that the high frequency ESR is going to be limited by the caps' ESR, more likely the interconnections.

I would hate to get 0.5 nH inductance from the array and then throw any of it away with a stupid connection method).

The inductance seen by the die inside the chipamp package is surely what matters? This to include the total loop area including the die attach wires. Hard to see how that's going to be in the sub-nH territory as the rule of thumb is that for bond wires, the inductance in nH is roughly the length in mm, to a first approximation. The distance between the power pins on your chipamps is going to be higher than 0.5mm.

The cost of the caps is still worrying me, a little. If I used two arrays per channel, that would be 400 caps. Might as well go for the Qty 500 price break and use 11x11 arrays, in that case. Still, it's a few hundred dollars. Maybe I will think a little longer about either using smaller arrays or smaller-value caps.

Get someone to source you directly out of Shenzhen I suggest, rather than using local distribution. I just bought 500 390uF/35V Rubycon ZL caps for my chipamps and that order was around $30.

 

[gootee]

Have a look at Rubycon ZL range - that's showing 330uF/50V in 10mm with a max 100kHz impedance of 28mohm. In my limited experience of extreme paralleling of caps, I found going above 330uF to be problematic in that the self-resonant freq comes down a bit too low for comfort. I doubt when paralleling 100 caps that the high frequency ESR is going to be limited by the caps' ESR, more likely the interconnections.

Thanks for reminding me about not using 1000 uF! I had noticed that the self-resonant frequency wasn't quite where I thought I would want it, in Terry's measurements. Or maybe it was KSTR's measurements. I think that one of them even mentioned it. I'll find the data and re-think the C value. Thanks again for pointing that out!

Are you thinking that something more like 330 uF would be about right?

The inductance seen by the die inside the chipamp package is surely what matters? This to include the total loop area including the die attach wires. Hard to see how that's going to be in the sub-nH territory as the rule of thumb is that for bond wires, the inductance in nH is roughly the length in mm, to a first approximation. The distance between the power pins on your chipamps is going to be higher than 0.5mm.

Yeah, I know. I should have said I didn't want to ruin it any more than I had to. It will definitely be WAY more than 0.5 nH, by the time it gets into the output devices. But I'll still fight for every nH.

Get someone to source you directly out of Shenzhen I suggest, rather than using local distribution. I just bought 500 390uF/35V Rubycon ZL caps for my chipamps and that order was around $30.

Wow. Thanks for the tip. I have a friend or two there. I haven't bought large lots for a long time and just didn't think about it.

 

[fas42]

You fellas are really going to town there ... in my playtime i went with good ol' FCs, 1200/50. Availability, ripple current, costing meant these were the best bang for the buck for me, I went the rounds many times looking at options. Didn't use as many caps, regulated feed took care of a lot of the sag.

And, chopped off the legs of the chip amps to give me just enough metal to solder to - every nH is precious ...

Frank

 

[gootee]

Agree Dutchie ....

@Gootee,

Whats the anticipated ripple voltage at full output and what min-z value are you using to determine values, surely not 8ohm ..?

With a sine with 5-Amp 40V peaks, the ripple should be less sthan 2.5% of 40V, i.e. 1 Volt or less, peak to peak.

I used 8 Ohms and 4 Ohms. It's just an example, basically. The point, really, is that you can set the ripple (and the load resistance) to whatever you want and then calculate what you need to do to achieve that under worst-case (or any other) conditions.

I guess I just like developing equations again, for a change. But it's much easier and more-flexible to just simulate the whole power supply in LT-Spice. Then you can do things like have it automagically sweep parameters over ranges and see the resulting series of plots, for example.

With equations, it's probably difficult for others to keep in mind what ASSUMPTIONS and conditions I have set, too. I spent some time figuring out what "worst case" should be and usually that is embodied in the equations. (I state them, usually, but it's still hard to keep in mind, maybe.) But it's probably different than what most people are accustomed to seeing, as far as C values. I usually prefer to meet the ripple spec while driving DC through the load, at the max rated peak values, for example. That way, I "KNOW" that it's truly able to work how I want it to, with the worst worst case. Most people assume a sine wave. But what if there are two? And in reality there might be dozens or hundreds simultaneously, especially if you consider all of the Fourier components of anything non-sinusoidal, which includes all music. With one piece of music someone came up with, instead of one sine peak grazing the peak value periodically, you got more and more and pretty soon there was almost always a wave touching the peak rated output value. So it might be more like a square wave, with its horizontal parts at the peak rated voltages. But that's just DC, part of the time. So "all of the time" is an even better "worse".

Then I usually also look at what the resulting configuration will do at NORMAL listening levels. Peak rated level performance is good to design to. But I never ever listen at that level. If I design for the really-worst worst-case, though, everything is usually surprisingly good at listening levels.

 

[gootee]

You fellas are really going to town there ... in my playtime i went with good ol' FCs, 1200/50. Availability, ripple current, costing meant these were the best bang for the buck for me, I went the rounds many times looking at options. Didn't use as many caps, regulated feed took care of a lot of the sag.

And, chopped off the legs of the chip amps to give me just enough metal to solder to - every nH is precious ...

Frank

Which ones have the rail voltage (or is it ground?) on the back plate? Would it help if I bolted or soldered that to the appropriate plane on the array board? (Actually, I guess I'd have to use a large/wide L-shaped piece of copper or something, so the chip could stand up and have a real heatsink, also.) Just a crazy thought.

I will at least make the pins as short as possible, like you did.

(Gotta get to bed. Early meeting tomorrow.)

 

[abraxalito]

Seems to me as the inductance of the paralleled caps isn't going to be the major issue, by at least an order of magnitude that to do this properly the chipamps should be paralleled up too?

@Tom - I'm settling on whatever's easy to get but below 470uF yep. Most recently 390uF but yet to build with those.

 

[fas42]

Which ones have the rail voltage (or is it ground?) on the back plate? Would it help if I bolted or soldered that to the appropriate plane on the array board? (Actually, I guess I'd have to use a large/wide L-shaped piece of copper or something, so the chip could stand up and have a real heatsink, also.) Just a crazy thought.

I will at least make the pins as short as possible, like you did.

(Gotta get to bed. Early meeting tomorrow.)

The National LM3875 come in 2 versions, from memory mine didn't have the -ve(??) rail connected to the heatsink metal. With regard to insulating or not, if you need to decide, I would do some tests, and think a lot about it!

I used a very long, narrow, finned black heatsink, standing upright - had the best thermal rating for the size, and money. Hence chip upright, and circuit horizontal. Obviously awkward in normal situation, but I was using these effectively to create active speakers, was on a slab of material against the back of the carcase.

Frank

 

[fas42]

Then I usually also look at what the resulting configuration will do at NORMAL listening levels. Peak rated level performance is good to design to. But I never ever listen at that level. If I design for the really-worst worst-case, though, everything is usually surprisingly good at listening levels.

Personally, I would design for the very highest level volume as being that for normal listening. I regularly drove, and still do, chip amp systems flat out, the heatsinks are stinking hot most of the time. If you do that there are no surprises with the volume control, the tonality and dynamics remain intact right up to maximum ...

Frank

 

[a.wayne]

You fellas are really going to town there ... in my playtime i went with good ol' FCs, 1200/50. Availability, ripple current, costing meant these were the best bang for the buck for me, I went the rounds many times looking at options. Didn't use as many caps, regulated feed took care of a lot of the sag.

And, chopped off the legs of the chip amps to give me just enough metal to solder to - every nH is precious ...

Frank

Using inventory , which means 80K/2 per channel and then decoupled at board , remote transformer , Not into the million caps to achieve the same value , never liked the sound of the ones i have heard in the past ...

Suggestions on the decouple value at the board .....?

 

[Telstar]

You fellas are really going to town there ... in my playtime i went with good ol' FCs, 1200/50. Availability, ripple current, costing meant these were the best bang for the buck for me
Frank

The panasonic FC are definitely a best buy, and so are the FM if you can use their limited value range.

 

[a.wayne]

What about the sonics, FM or FC ...?