Power Supply Resevoir Size

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
(In the transformer data table, the "654.3" for the 240 VA case should be "854.3".)

Now we can check to see how the simulation data compare to the approximate equations for selecting capacitance based on ripple voltage and average load current. I haven't done that yet but I will, unless someone beats me to it. It might be complicated a little bit by the fact that some of the simulated configurations are more viable than others, in terms of the ratings of the transformer versus the task at hand.

It did become obvious, while watching the simulations run, that the ripple voltage does not have to reach all the way down to the peak signal voltage, in order for the signal to get distorted by the effects of the capacitance being too small.
 
Last edited:
gootee said:
It did become obvious, while watching the simulations run, that the ripple voltage does not have to reach all the way down to the peak signal voltage, in order for the signal to get distorted by the effects of the capacitance being too small.
You have 3 Vbe drops plus the 0.22 emitter resistor. I realise that the Vbe drops could be small but this means the BJTs are in collector saturation mode on peaks which could create problems at high frequencies.

With a zero resistance transformer you would need about 3500uF for 100W at 8ohms. Your simulation shows about twice this. I would expect transformer voltage drop to explain this. If you adjust your model to boost the secondary voltage you will find that a smaller cap is needed.
 
You have 3 Vbe drops plus the 0.22 emitter resistor. I realise that the Vbe drops could be small but this means the BJTs are in collector saturation mode on peaks which could create problems at high frequencies.

With a zero resistance transformer you would need about 3500uF for 100W at 8ohms. Your simulation shows about twice this. I would expect transformer voltage drop to explain this. If you adjust your model to boost the secondary voltage you will find that a smaller cap is needed.

No. The simulation shows almost exactly what you predict; maybe even slightly less.

If you look at the first plot in the second set of plots (i.e. for 100W, 8 Ohms, 240 VA, "raw"), where there are enough VA available for 100W at 8 Ohms, you will see that. It's likely showing between 3000 and 3500 uF, since we're looking for the minimum, not the last 0.002% THD.

Maybe you only looked at the Cmin in the table, which is not a direct simulation result but rather something that I "derived" from the results. But I mentioned that I did not understand how to pick the Cmin, too well. The best way might be for me to look only at the raw plots, and never look at the zoomed versions. They make me forget the "min" part. <grin>


But yes. As you said earlier, you can trade excess voltage for capacitance. So far these runs are just to try to work toward a model that can predict the minimum needed capacitance for commonly-used power transformer and amplifier-output-spec configurations or combinations, to help Nico find out if there are any "rules of thumb" for reservoir capacitance. It is not even a real amplifier; just a piece torn from the output stage of one of Bob Cordell's models, minus the feedback etc. (Maybe that is another part of this simulation model that should be improved?)
 
Last edited:
So far these runs are just to try to work toward a model that can predict the minimum needed capacitance for commonly-used power transformer and amplifier-output-spec configurations or combinations, to help Nico find out if there are any "rules of thumb" for reservoir capacitance. It is not even a real amplifier; just a piece torn from the output stage of one of Bob Cordell's models, minus the feedback etc. (Maybe that is another part of this simulation model that should be improved?)
And nicely done too, Tom, :up: .

This can all go quite some way: including feedback path, and the rest of the full amplifier circuit, will make life very interesting, because the complete amplifier has significantly poorer PSRR than just the output chunk. Fun times ahead ...

Frank
 
Tom,

I may have started the thread but just considering the number of member/readers tells me that you are not wasting your time. I bet these guys are all itching for an the outcome so they can all upgrade there systems in order to achieve an example that is closer to perfection and you have been an absolute inspiration.

In my opinion, (and maybe a moderator can check the statistics) this has been one of the most read threads over a period of one month.

I applaud you contributing to this thread because it has been hugely informative and you all have done an excellent job.
 
Last edited:
What a coincidence. I just came back to post the rest of it.

Below are the schematic used for the simulations, the main table of initial results, some info about the power supply behavior (because if that's no good then the data might be no good), plots of THD vs reservoir capacitance, and a zip file with the simulation files plus the Excel spreadsheet that has all of the data in it.

Please understand that I used THD here only as a tool (with an incomplete amplifier), only in order to more-easily find the minimum viable capacitance value, during C-value sweeps, to find the point (C value) where the PSU itself was no longer deforming the amplifier's output waveform due to the capacitance being too low. Otherwise, I would have had to try to very-closely inspect the output error plot and the signal output plot. And then there also would have been no real context for the swept capacitance values.

After all of that, I still didn't know exactly how to actually CHOOSE the minimum capacitance, from the data. So I tried a couple of ways:

First, I looked at the THD for a huge capacitance, then backed up until I found a THD that was 1.01 times the THD with the huge capacitance. The capacitance value found that way in labeled "Cmin 1%", in the table.

Second, I just "eyeballed" the plots and tried to pick a minimum value that was past the more-vertical section of the plot, without being too greedy about the THD, which was not changing much anyway, and while trying not to think about the uF per Amp that would result. That process was very difficult to be objective about, especially after expanding the low-level portion of each plot. The minimum capacitance found that way is labeled "Cmin from Plot", in the table, and might be more or less meaningless.

Note, too, that the plots posted as jpgs are not "to scale". The horizontal axes just have all of the data points, in sorted order. I also did some plots with linear scaling. They're in the Excel spradsheet file, in the zip file attachment, along with the actual raw data tables.

The transformer model was fed with about 144% higher voltage than I used when measuring the real transformer for the model, i.e. 173 VRMS instead of 120 VRMS. That way, it has an output level that's more like a 36 VCT transformer's secondary. Maybe I should note that when I originally tested it, I did so with both the primaries and secondaries paralleled, because a) that's how I was using it, and b) the modeling algorithm I had was only for single-primary/secondary transformers. I'm hoping that since it was in that high-current configuration when I measured it, and it was also designed for use with 230 V mains, that maybe the model won't be too far off. Anyway, I posted a little table of transfomer data that I took from the simulation, hoping that one of the transformer experts here will either pronounce it DOA or give a review of its good and bad points. (I will try to make whatever data is needed, for that, with the simulator. The original physical measurements are posted in this thread, in the transformer model schematic, or I can provide them again if that's too difficult to find.)

Oh, in order to be able to sweep the capacitance automatically, I used some equations that I found in a paper somewhere to calculate the ESR and EPR on the fly. ESR = {0.02/(cap_value*Vrating)} and EPR = {1/(0.01*cap_value)}. I used Vrating = 100 Volts. ESL was just set to 10nH.

Now that I have the setup built, it wouldn't be TOO terribly difficult to do it over again, if model changes are needed.

Cheers,

Tom

Thanks Tom. :cheerful:Using these results its possible to see what capacitance is required as well as transformer VA. Using this data we are able to see whats too little and whats too much. If you notice as the VA increases the rail sags less but definately there will be a point where there are diminishing returns. It is interesting that this validates our earlier predictions on expected capacitance and VA.

I am now looking forward to inclusion of decoupling caps in the simulations. :scratch2:
 
gootee said:
to help Nico find out if there are any "rules of thumb" for reservoir capacitance.
I thought these were already known, and based on ripple calculations. Your simulations seem to confirm this. A bit of algebra gives the minimum capacitance. Then other issues such as local decoupling and inductance tells you how to split that capacitance. ESR might mean you wish to go a bit higher in cap value, but there seems to be no hard evidence that massive caps bring any advantage. Huge caps and a huge transformer just mean narrower but taller charging pulses so more risk of induction into signal circuits, but this is hard to simulate unless you have full EM wave software.

The rule of thumb would appear to be: calculate the minimum then double it. Then make sure you have good low resistance and low inductance connections, and grounding in the right place.
 
DF,

I thought these were already known, and based on ripple calculations. Your simulations seem to confirm this.

Depends on what "known" means.

A bit of algebra gives the minimum capacitance.

The commonly-used approximate ripple equations are only valid if the ripple is small (< 10% of Vsupply) and the load current is constant DC or the load is a simple fixed R. They also don't take into account the transformer parasitics.

We have neither of those first two assumptions, with a large AC output and an active load, and might also be violating the "small ripple" assumption when using "small C" to find the minimum C.

As shown by the links to the papers I posted, the mathematics for a transformer, rectifier, and fixed-R load is surprisingly complex, even for most electrical engineers.

So I opted for simulation while studying the math in the background (perhaps we could add a sinusoidally-varying R to the existing Rload, in the real equations, to mostly account for the output transistor with a sinusoidal control signal, for our purposes here).

Anyway, initial testing seemed to show that the results were difficult to predict, with things like a seemingly-safe C value still experiencing occasional deformation of low-frequency output waveform if phase-angle happened to cause a particular alignment relative to an extra-large charging pulse.

So it seemed worth trying to nail it down better, either with simulation or with the exact equations.

(And I STILL haven't had time to compare each of the simulation scenario results to the standard approximate method for choosing C!)

That reminds me that I did not complete the phase-angle sweeps to verify that the C values near the minimums posted were safe from output waveform deformation for all phase angles. In some cases it's difficult to be sure unless you simulate for a long time, otherwise, which is also quite tedious.

That also reminds me about the pulse testing. I tried square waves with the same output RMS power level as the sine, and even came up with .measure statements that found the worst-case "pulse top deformation" for a particular time period. But since the voltage amplitude of the square waves was so much lower than that of the sines, for the same power level, they were always fine.

However, NOW I realize that I should have lowered the duty cycle until their amplitude was the same as the sine's, but the RMS power was still the same! That would be a worse case than the sines, although I don't know how important it is for an amplifier that is made for music. It might be nice for getting a sort-of "bullet proof" upper-bound for the minimum C, though.

Then other issues such as local decoupling and inductance tells you how to split that capacitance. ESR might mean you wish to go a bit higher in cap value, but there seems to be no hard evidence that massive caps bring any advantage. Huge caps and a huge transformer just mean narrower but taller charging pulses so more risk of induction into signal circuits, but this is hard to simulate unless you have full EM wave software.

The rule of thumb would appear to be: calculate the minimum then double it. Then make sure you have good low resistance and low inductance connections, and grounding in the right place.

Well, that's what we're trying to figure out.

Regarding simulaton of the narrower charging pulses, etc, we would see those in the conductors, in our simulations, under those conditions, without doing anything special. If you are talking about their propagation through the air, to other conductors, then no, LT-Spice is not set up to be able to handle that. Let's hope that everyone knows about Faraday's Law and the more-general Maxwell's Equations, and the (bad) ramifications of "enclosed loop area", and tightly twists-together, or otherwise minimizes the space between, all of their conductor pairs, especially the mains/transformer, secondary/rectifier, rectifier/caps, and input signal/ground pairs.

Anyway, I think we're mostly still on the same page. I was aware that the simulation results might show that the simple approximate ripple equations would work well-enough, after all, which might then have made it seem like the effort was somewhat wasted. But it still seemed like the quickest and easiest way to become more certain about what what would really happen with various C values and various transformers and loads.

I wish we also had a continuously-variable transformer model, which Terry Givens hinted at in one of his posts, and wish I had sufficient time to play with all of this. My "math refresher" class is over, now, so maybe I will have time to do a little more, or a little better.

Cheers,

Tom
 
Tom,

I may have started the thread but just considering the number of member/readers tells me that you are not wasting your time. I bet these guys are all itching for an the outcome so they can all upgrade there systems in order to achieve an example that is closer to perfection and you have been an absolute inspiration.

In my opinion, (and maybe a moderator can check the statistics) this has been one of the most read threads over a period of one month.

I applaud you contributing to this thread because it has been hugely informative and you all have done an excellent job.

Nico,

I appreciate your saying all of that but you are being too kind.

It has been interesting and fun, though!

However, I do hope that someone will attempt to validate and verify the simulations, both the assumptions and the actual outputs. There are many variables and many opportunities for error. I will be very surprised if what I have done so far is totally valid.

Regards,

Tom
 
gootee,
I have to admit that most of what you are doing is over my head here but I still have a question regarding what you are saying and doing. You talk about a constant R value in the simulation not being a real world situation. Am I to assume that this takes the place of the loudspeaker load on the amplifier? If that is the case is this also some of the phase shift that you are referring to or is this phase shift on the transformer end of the circuit. If it is the loudspeaker would a simple matched Zobel network close to the loudspeaker simplify the phase shift and impedance rise that is loading the output devices and driving the load to follow this phenomena?
 
Thanks Tom. :cheerful:Using these results its possible to see what capacitance is required as well as transformer VA. Using this data we are able to see whats too little and whats too much. If you notice as the VA increases the rail sags less but definately there will be a point where there are diminishing returns. It is interesting that this validates our earlier predictions on expected capacitance and VA.

I am now looking forward to inclusion of decoupling caps in the simulations. :scratch2:

Actually...

If we look only at the first (non-zoomed) plot for each scenario, we get minimum capacitances, in posted plot sequence order, of:

4500 uF, 3300, 4000, 4000, and 11000 uF.

Using the I_load currents in the table in post 740 at

http://www.diyaudio.com/forums/solid-state/216409-power-supply-resevoir-size-74.html#post3134179 ,

that gives "minimum uF per RMS output Amp" figures of:

1273, 933, 653, 653, and 1556 uF/Amp,

for the scenarios simulated, which should result in no significant distortion of output signal due to "capacitance too low", in each case.

THOSE are the numbers that "should" have been in the table column labeled "uF per Amp from (Cmin Plot)".

I'm not suggesting that those are what should be used, or that those should be used to form any "rule of thumb". But they "should" be workable values, for the scenarios tested, in terms of never experiencing gross distortion, up to the rated output power level (at 25 Hz).
 
I went back in and found the ACTUAL Cmin values, by carefully examining the magnified Output Error waveform while adjusting the capacitance 100 uF at a time.

The CT transformer power supply and Rload setup that is being used is a little confusing (at least to me). Since each rail does only half (one polarity) of the load's waveforms, in order to be consistent with the current and power being supplied, I changed the table to reflect "per rail" power output, and used 1/2 the load current when calculating the "uF per amp" numbers, which makes them twice as large when compared to the first version of this table. But the RMS power being delivered to the load is double the RMS power being delivered by each rail. If you prefer thinking about it with the full RMS current and power of the load, then just divide the "uF per amp" numbers by two.

I'm too tired to do a recap or anything, tonight. Going to bed after this.

Cheers,

Tom
 

Attachments

  • Data_Table2.jpg
    Data_Table2.jpg
    97.1 KB · Views: 438
gootee said:
The commonly-used approximate ripple equations are only valid if the ripple is small (< 10% of Vsupply) and the load current is constant DC or the load is a simple fixed R. They also don't take into account the transformer parasitics.

We have neither of those first two assumptions, with a large AC output and an active load, and might also be violating the "small ripple" assumption when using "small C" to find the minimum C.
In most real amplifiers the ripple will be small in % terms, and the approximate formulas should be good enough. After all, big caps usually have wide tolerances anyway. For the worst case, full amplitude LF square wave, the load is a constant R (at least for a while, until it switches to the other side of the output). I think the problem is that people design with Idc, when they should design with Ipk=2 Idc.

Testing/simulation with square waves might be more tricky, as it would be harder to spot changes in harmonic structure when there are plenty of harmonics already present. Using sine waves, as you are, creates the problem of phase alignment as you have found. Full amplitide square waves could be used if you look for mains-related IM suddenly appearing, although you would have to choose your frequencies carefully. Maybe 25Hz, and look for 95Hz and 145Hz sidebands? You might even see some 35Hz and 85Hz, if the PSU becomes temporarily unbalanced. Testing with square wave RMS values equal to the sine RMS will show nothing, as you have found. You need equal peak values.

Transformer parasitics could be an issue, but these (apart from DC resistance) are usually unknown and could vary from one manufacturer to another.

I realise that the full equations get messy, especially with a varying load. However, a varying load is not the worst case so we don't have to design for it. This assumes, of course, basically good PSRR in the amp circuitry so we only have to worry about output stage limiting. For PSUs, unlike the rest of the circuit, we are not interested in calculating exact values because the exact values don't matter and we can't buy exact components anyway. Therefore we don't need the full equations.

Yes, I think we are mostly on the same page. I commend your effort. You probably know better than this, but I suspect some people are still hoping that some 'magic numbers' will drop out of your simulation. I don't expect this. At best you will confirm what the algebra tells us. I will shut up for a while, unless I can come up with some useful equations.
 
Possible "shelf" in the figures?

Slight problem: At higher power, the speaker support requirements might not increase as dramatically. This much is sure to support the 8 ohm speaker (2,200uF * 6 per rail divided by 2 rails seems similar to a single rail amp with 6600uF)
247247d1320044638-need-help-triple-parallel-lm1875-dynamics-amplifier-power-big-little-dual.jpg

After reaching enough capacitance to support the 8 ohm speaker down to about 3hz (same as sizing an output cap so large that it won't be an audio filter), then, at that point, the speaker frequency response support task has surely been completed, and I believe that portion of capacitance requirement is done.
New question:
I'd just like to know the estimated capacitance per ampere after having guaranteed the speaker support. Maybe the problem needs sorted in 2 steps?
 
Have you noticed that many "HiFi" amplifiers claim to be flat to 4Hz? This is generally the F(-1dB) value indicating they have chosen F(-3dB) of ~2Hz.
I believe that to get good audio performance from a speaker trying to reproduce down to 20Hz (even though it's frequency response is down by 20dB relative to the 1kHz output) the amplifier must be able to perform well down to ~ 2Hz to 3Hz. This just happens to be very close to the "mainstream" 4Hz value, quoted in specifications.
 
this is my opinion of course.
I do not know a speaker or speaker + box, which reproduces well 4Hz. I know speakers that reproduce well 16Hz. and I do not mean normal louspeaker.
To the amplifier, normally the declared value below 10Hz, refers only to the bandwidth. in this case it is fortunate that the audio sources, including recording, do not contain this frequency. :)
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.