|18th August 2012, 10:54 AM||#611|
Join Date: Mar 2008
thats a lovely analysis.
here's another way of looking at it. If one (in a fit of inspired madness) draws a block diagram representing the overall amplifier transfer function, there will be an input from the power supply - not terribly surprising as thats where all the power comes from.
The trick we pull when analysing smps transfer functions is to casually ignore the supply input - IOW assume it is pure DC and only affects the steady-state solution. we invariably do the same thing with the reference voltage - when we perturb the system of equations we just plain old ignore small-signal variations of Vin & Vref.
Unless something is horribly, horribly wrong, this is a good thing to do with the reference voltage - it really ought not vary. Its often NOT reasonable to ignore the input supply (eg when there is an EMI filter which there always is), but because it makes the analysis so much harder (A buck converter is a 2nd order system; with LC input filter its now a 4th order system), we often cheat - eg using middlebrooks impedance criteria.
We make similar approximations every time we use i = C*dV/dt - its really i = dQ/dt = C*dV/dt + V*dC/dt, but this almost never used (I imagine this would segue nicely into microphonics & electrostatic speakers). there's nothing wrong with approximations, but its wise to know when we are making them - eg if a circuit is physically small wrt wavelength we dont have to use maxwells equations, and can use the LF approximations - Kirchoff, Thevenin etc.
oops, wandered off-topic. Back to the supply rails.
Clearly the existence of PSRR as a concept - and of course curves (PSRR as a number is almost entirely useless - I once discovered the hard way a TL064 has GAIN from the supply to the output at 100kHz) - hint rather strongly that there is a path from the supply to the output.
A cursory examination of output devices show several methods - miller capacitance provides a path into the gate/base (capacitive so HF PSU noise will want to go here), Early voltage, Rds etc. This leads directly to the point Frank eloquently made earlier - that supply disturbances create output disturbances that the amplifier feedback networks must then reject. This is, after all, precisely what gives rise to PSRR.
You and Frank have shown clearly with your numerous simulations that the supply impedance-vs-frequency is very important, regardless of the final answer to the "how-many-farads-per-amp" question. real audio can and does have some exciting transients (Acka Dacka - an inspired choice), and poor HF design of the decoupling network just adds to the work the amplifier has to do.
The great thing about the HF response of the DC Bus networks is that it is essentially FREE. All one needs to do is:
- use multiple smaller caps in parallel (to reduce ESL & ESR)
- have a reasonable portion of them at the amplifier (bypasses the wiring harness inductance)
- do a decent low-inductance layout**
Last edited by Terry Given; 18th August 2012 at 11:20 AM.
|18th August 2012, 11:50 AM||#612|
Join Date: Mar 2008
this post was getting a bit long...
**this is not entirely free. the single best way to make a low-inductance layout is to use 2 (or more) layers, and make a parallel-plate "transmission line" - sounds fancy but in practice its dead easy - one layer is 0V the other layer is +Vsupply (or -Vsupply for the other rail). The inductance per unit length of a pair of parallel plates is approximately:
L = u0*separation/width [Henry/m], u0 = 4*pi*10^-7 (R, W & Van Duzer. ignores edge effects)
the separation is the PCB thickness (I use 4-layer PCBs a lot, with a thick double-sided core so the TL-ML1 = ML2-BL separation = 0.113mm), so if you need to reduce L just make it wider. this fits really nicely with using many smaller caps in parallel, and it obeys the "current flows in loops - minimise them" mantra.
If you already have a 2-layer PCB then this really is free. If not - use 2 layers. I do lots of dead-bug prototyping, with a mixture of smt & leaded parts. I use 1.6mm 1-sided PCB for a 0V plane, and have a bunch of 1-layer 0.5mm PCB material (I bought 20x A4 sheets from a supplier for not very much) that I stick on top (often using eg bypass caps to hold it down, sometimes superglue). this works really, really well.
I should also add:
- twist or braid (works great for +Vs/0V/-Vs) the interconnects to reduce the inductance (It also helpfully reduces the emission of, and pickup of, stray magnetic fields). This is especially important for the xfmr-bridge wiring!
- once you split the DC bus caps into rectifier & amp banks, separated by an interconnect, you might as well pop a small R in the interconnect and make a C-R-C filter.
- I would choose the R so that it damps the L-C circuit that is the interconnect L & the amplifier bypass caps. Unless power loss/volt drop is an issue I would heavily damp the network - so it has an RC-type curve (delta = 1) and no overshoot.
this can be done experimentally by using a FET to switch a decent resistive load across the amp decoupling caps, wait a bit & switch it off (fast) while measuring the cap voltage. If you can measure a ringing overshoot, measure its frequency Fring.
2*pi*Fring = 1/sqrt(L_wiring*C_bus) so you can calculate L_wiring if you wish.
this measurement is actually easier to do with high-inductance wiring***
you can then calculate the characteristic impedance of your lumped transmission line (sounds fancy but its just some wiring L and a bunch of caps) Z0 = sqrt(L_ring/C_bus)
And pick R_series >= 2*Z0
(or just pick R_series >= 2/(2*pi*F_ring*C_bus) its the same equation re-arranged)
I was going to say: BUT beware the inductance of WW resistors. But my HP4262A cant even measure the inductance of 0R1,10R,100R 5W ressitors at 10kHz so its << 1uH and can probably be ignored. just saying.....
*** a nice low-inductance braided/twisted wire will have << 1uH ESL, and along with >= 1mF of amplifier bypass cap will have a Z0 that is << 30mOhms - so the wiring resistance itself will probably damp the LC circuit. Fring will be a few kHz, so skin effect actually helps here.
For best AC line ripple rejection make the series R as big as possible (limited only by the volt drop and/or power loss)
|18th August 2012, 12:42 PM||#613|
Join Date: Mar 2008
Inductance of Single-Layer PCB layouts:
It would be reasonable to assume that if the trace-to-trace separation was equal to the PCB thickness then a single-layer layout will have the same inductance as a 2-layer parallel-plate transmission line (that just sounds so fancy, I love it).
It would also be quite wrong - the single-layer inductance will be quite a bit higher than this.
The reason is simple - AC current flows in the path of LEAST IMPEDANCE. DC current will take the path of least resistance - but above DC this becomes the path of least inductance.
Lets start by ignoring skin effect completely, and just looking at loop inductance.
If the current in the 1-layer traces was evenly distributed then the "loop" responsible for the inductance is the center-to-center distance of the adjacent traces times the trace length. This is usually true at DC and low frequencies.
But its quite different at even moderate AC frequencies. And here's 1 reason why: Loop Inductance.
If we pretend our PCB trace is made of N "filaments" that are 35um square, and pretend these are insulated, we can see that there are a whole bunch of different loops in which the current can flow. Inductance is proportional to loop area = length*separation, and they are all the same length so the inductance is proportional to the separation.
the two closest filaments (call them F1+ & F1- with numbers increasing as we move away from the center-line) have the smallest loop are and hence the smallest L.
There is a slightly larger loop from F1+ to F2- (its 35um further away than F1-), and ditto for F1+_F3- etc. all the way out to F1+_FN-
Then there is F2+_F2-, F2+_F3-....F2+_FN-
this continues all the way to FN+_FN- which has the largest loop.
[this is a perfectly valid, albeit horrific, way to calculate the current distribution. We had to do this in Heavy Current ELectronics, using Mathcad]
the average loop is clearly the center-to-center distance times the length, as asserted at the beginning.
So a 100mm long pair of 5mm wide traces separated by 1.6mm has a loop area of (5mm/2 + 1.6mm + 5mm/2)*100mm = 3.6mm*100mm.
Whereas a pair of 5mm wide traces on opposite sides of a 1.6mm PCB has a loop area of 1.6mm*100mm, which is 3.6/1.6 = 2.25x smaller than the parallel traces.
Note: I should really have added in the Cu thickness here; assume the current is evenly distributed vertically and take the middle of the Cu, giving (35um/2 + 1.6mm + 35um/2) = 1.635mm effective separation, and 1.635mm*100mm loop area. the approximation is only out by 1.635mm/1.6mm = 2.2% so it can be ignored, but for thinner PCBs and/or thicker Cu this might not be true - 4Oz Cu = 0.14mm thick and I have used up to 10Oz Cu = 0.35mm thick. A buddy once showed me a Syncor dc-dc PCB that was IIRC 8-layer 4-Oz Cu -the bare PCB was stupidly heavy, and was about 60% Cu, 40% FR4!!
So the single-layer PCB pretty much always has more loop inductance than the parallel-plane 2-layer PCB. Yeah we can have < 1.6mm trace separation, but it cant get too small, and the trace needs to be wide to carry any decent current.
But wait there's more - the single layer PCb is even worse because of skin effect....
|18th August 2012, 01:18 PM||#615|
Join Date: Mar 2008
This simple model also shows how current will crowd towards the inner edges - the innermost filaments have the smallest loop hence lowest inductance, so carry the most current, whereas the outermost filaments have the largest inductance and carry the lowest current.
Using the nomenclature N+ = filament no. on one side, N- filament no. on the other side (1 = closest to center) then the loop area = ((N+)*35um/2 + gap + (N-)*35um/2)*length which is:
Loop = [(N+ + N-)*35um/2 + gap]*length
then the innermost loop has N+ = 1, N- = 1 and Loop = [(1 + 1)*35um/2 + gap]*length = [35um + gap]*length
If we define the current flowing through this innermost loop as 1, then the relative current flowing in any arbitrary loop [A+ B-] is:
[(A + B)*35um/2 + gap]*length [(A + B)*35um/2 + gap]
1 x ======================= = ==================
[(1 + 1)*35um/2 + gap]*length [35um + gap]
again this would be fun for someone to play with - you will get a square matrix (assuming both traces same width so N+ = N-, but this will also work for different widths) with 1 in the top LHS (the innermost pair of filaments) and numbers < 1 everywhere else. it will be symmetric, and decrease down the diagonal. The rows represent the filaments on one side, and the columns represent the filaments on the other side.
One could then sum the entire matrix, to get the total relative current, call it S = SUM(all elements). If we then divided the actual current I by this factor S we get the current carried by the innermost filament loop, I_inner = I/S.
The current carried by each filament is just the sum of the relevant row (or column) times I_inner
which is the same as writing I_filament(x) = I_total*SUM(row x)/SUM(entire matrix)
we could then do some cute plots: I_filament(X) vs X gives a plot of current distribution.
later on I'll whack up a MathCAD worksheet for this and post it. Its basically a manual FEA, and is useful because:
1) it shows how the "filament loop" inductance distorts the current distribution, and
2) a manual FEA is actually a pretty good way to solve a bunch of problems if the geometry is easy. I've done it for thermal problems - evenly distributed heat in a wire cooled at either end.
3) it also shows how this approach gets out of hand fast (N^2 loops for N filaments), and why we use FEA programs to do it for us.
(sorry about the long waffly story, I kinda got carried away. Sometimes a simple analogy just doesnt cut it)
|18th August 2012, 02:15 PM||#617|
Join Date: Mar 2008
Magicbox @ #514 made an astute observation that I really like, but in a fit of inspired stupidity I've been erroneously attributing it to Frank (so many great contributions its easy to get confused. besides I'm thick). Sorry MagicBox, my bad:
At regulatory frequences, the AC output impedance of a MOSFET / Transistor is rather low; any HF signal on the output transistors 'walks' right through the output device, severely destructing PSRR. Luckily the amp must be stable and as such will not have HF AC regulatory swing (if it does, it can't stable out) for audio signals. But to keep that audio signal in perfect shape, you no longer have to view an amp as an LF amp but as an MF/HF amp operating in the 100KHz - 1MHz area.
Edit: Basically the amp has to be fast enough to compensate for its inherent slowdowns in the circuit.
in which he/she (the gender-neutral Xe is useful here, I have no basis for assuming xe is male) points out that the transient response of the amplifier supply directly injects artefacts into the output, which the amp must then correct via the magic of feedback - and this is why the amp BW needs to be higher than expected.
Like so many engineering issues this triggers off a spiral of despair - poor layout => nasty supply transients => higher amplifier BW required => exacerbate effects of poor layout. The really cool thing about this is that the supply rail HF performance can be hugely improved for little or no actual cost, which makes life easier for the amplifier.
That paragraph is worth its weight in spectrum analyzers! mathematical analysis is all well and good, but understanding is the key (and is something maths is all too good at preventing).
Toms detailed description of the correspondence between PSU current & output signal is similarly brilliant. These explanations are IMO clear, cogent and provide crucial insight into the subtleties of amplifier performance.
Add in the awesome simulations, the plethora of excellent questions and responses and voila - this book appears to be writing itself. I cant wait to see how it ends!
|18th August 2012, 02:31 PM||#618|
I believe that there is confusion about PSRR, unfortunately lends itself to various types of measurement depends on what you want to see. a good PSRR can completely change the result, as seen in a transient response.
I agree on small capacity additions, on electrolytic capacitors, in the case of bank capacitors, it is better to put a small capacity for each individual.
To obtain the results of a good investigation, decide to proceed with measures true, not by the simulator.
I understand that the only way (economic) in order to obtain good performance, is to use a capacity near the devices. it helps the transient current depends on the capacity can be up to 150ms and after? the sound level of the envelope down. a defect is very common on the "crescendo of classical music," or on the bass strings, eg. with female vocals. (Jazz).
Very poor is chord bass and trumpet with percussion.
it is clear that I am referring to high performance, just those who want a audiophile after spending a lot of money.
After all this, there is also to consider that the market wants new solutions, new dimensions without the weight of the transformer. this is the main reason to look and research new solutions.
I'm ready to put my experience to develop a new circuit, also analog, this can be based on a fast controller that plays in "relative" instead of "absolute". i mean, in a percentage of voltage reported to vInput, in this way it is possible to fix the dissipation. just an idea.
Last edited by AP2; 18th August 2012 at 02:36 PM.
|18th August 2012, 03:04 PM||#619|
Join Date: Nov 2005
Location: Amanzimtoti - East Coast of South Africa
Guys, I applaud you all for your contributions. This has been one of the most interesting threads that I have followed on DIYaudio. You really learn a lot from others and I am hugely impressed by the combined knowledge and experience being delivered.
|18th August 2012, 03:38 PM||#620|
Join Date: Aug 2012
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