Power Supply Resevoir Size

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I also believe this is Tom, Frank (I did not call you Fred this time) DF and Terry's observations with their simulations and would appear that both complex impedance and filtering effect of the power supply has some critical effect on the "apparent sound quality" which is of course distortion of some kind or another - probably related to inter-modulation distortion.


Now one final comment, could this be why some speculate that an amplifier with no overall NFB sounds "better" (or one with a non differential input). Or am I just opening another can of worms here. I do believe that we will come to conclusions that will benefit us all.
I knew I would like you in the end, Nico ... :D:D

People beating on about the speakers being so terrible with distortion compared to everything else in my experience is a real Furphy (that's Oz for a red herring ...:)). I've been constantly amazed by how almost miraculously good even very low life speakers sound, if the electronics feeding them are behaving themselves. The quality in sound that makes people jump to attention vs. dismiss the result as ho hum or fatiguing is all about the electronics, almost zero to do with the speaker drivers. In my experience.

Down the track I aim to do some interesting sim's about what happens to the behaviour of a typical power amp when gnfb has to operate in a real, rather than a theoretical world ...

As regards difference in sound with different brands of caps, do note that earlier on I posted a sim showing dramatically different voltage rail glitching depending on the ESR of the caps, something that varies with temperature, the frequency, the age of the thing, the time of day it was manufactured ... it's a can of worms ...

Frank
 
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Fas42,
With your observation that the ESR factor is important and changing with temperature and other factors do you think that besides total capacitance this is one of the specific qualities to look for? So if two capacitors have a graph of ESR as a function and they track similar will we get similar results? And using this specification as a baseline what are we looking for the lowest ESR numbers, or is there a tradeoff between higher or lower values?
 
Fas42,
With your observation that the ESR factor is important and changing with temperature and other factors do you think that besides total capacitance this is one of the specific qualities to look for? So if two capacitors have a graph of ESR as a function and they track similar will we get similar results? And using this specification as a baseline what are we looking for the lowest ESR numbers, or is there a tradeoff between higher or lower values?
All things considered the lower the ESR the better; a simple way to look at it is that the cap is to a large degree the power supply, a type of battery. Which is feeding a load of say 4 ohms through switches, the output active devices. High current flows at the peak power draw then causes a major voltage drop across the ESR, good ol' Ohms Law.

In my own experience it's always worked better when I had multiple caps in parallel to replace a single, large item, this will always reduce the ESR. Sometimes you win(!), ESR of caps reduces as temperature goes up, so, hey, that's one of the reasons maybe why amps sound better after an hour or so from switch on!! And why class A and tube amps do better, hmmm? Downside, the electrolyte inside the caps evaporates faster at higher temps, so life is reduced, and now we lose! The dance continues ...

Frank
 
Thanks for that post.
Multistrand cable? In an audio amp? I just said the "f" word. That cable has the copper fibers individually coated slightly for corrosion resist. Why do I want 16 bad copies of my signal distorted like a house of mirrors? Does that help tweeters? Apparently, they are selling tone differences, and they must mark up the price or else call it noise? The durability of the botique polypro caps looks acceptable for speaker crossovers, especially for shunt.

Daniel,

Multi-stranded, with each strand insulated, would mean multiple separate parallel conductors, which would make both their net ESR and net ESL lower than those of an individual strand, and hopefully lower than those of a single equivalently-large conductor. It could be significant for a decoupling cap. But if they're axial and large then forget it.

In some cases, something like that might be very helpful when implementing the decoupling caps' layout, where it can be very difficult to get low-enough ESL (and ESR), i.e. short-enough connection lengths, without using multiple separate parallel conductors (typically one pair for each decoupling cap, with multiple smaller parallel caps being used in place of one larger one).

Also, I still say that the power and ground rails should be implemented using multiple separate parallel pairs of conductors, that stay separate all the way from the rectifier outputs to the load, with a separate capacitance for each end of each pair of power/ground conductors.

The truly ambitious would experiment with the use of a separate set of those multiple pairs for each active power device. Shielded cables with multiple twisted pairs inside come to mind. (Or, implement with true multi-layer PCBs. But be careful to use multiple separate widely-spaced points to connect each power and ground plane to the PSU, with a separate conductor (to the PSU) for each feed point [because mutual inductance has to be avoided, to get the ESL to "divide down" exactly like the total R of parallel resistors does].)

Theoretically, we could make the power supply impedance, AS SEEN BY the active power devices, as low as we wanted, just by using enough parallel pairs of conductors for power and ground. (If we used enough, maybe they could also be the heat sinks. <grin>)

Tom
 
The truly ambitious would experiment with the use of a separate set of those multiple pairs for each active power device. Shielded cables with multiple twisted pairs inside come to mind. (Or, implement with true multi-layer PCBs. But be careful to use multiple separate widely-spaced points to connect each power and ground plane to the PSU, with a separate conductor (to the PSU) for each feed point [because mutual inductance has to be avoided, to get the ESL to "divide down" exactly like the total R of parallel resistors does].)

Theoretically, we could make the power supply impedance, AS SEEN BY the active power devices, as low as we wanted, just by using enough parallel pairs of conductors for power and ground. (If we used enough, maybe they could also be the heat sinks. <grin>)

Tom
I went to a great deal of trouble using much of these techniques for my version of the classic National gainclone: over sized transformer, huge array of caps, separate power planes, regulation. It was, is, virtually all power supply, the amp itself was a tiny, tiny part of the assembly.

And it worked, had no trouble hitting the bump stops without showing signs of stress. It had so much effective energy reserve that I could pull the power plug out of the wall while playing at a moderate volume level, and nothing would alter for many minutes, depending on what was playing, no change in tonality, etc.

Frank
 
Here is an example of the power supply distortion that I am using to determine the "cutoff" point for the "minimum" required capacitance.

The example setup is not extremly important, for this example, but for the sake of completeness here is its description: It has two 500-VA-each transformers acting as center-tapped secondaries of a simulated 1000 VA-rated transformer, with a rated voltage of 44-0-44 VCT RMS, powering a rectifier bridge, reservoir capacitors, and the amplifier previously shown, set up to produce 100 Watts into the single 8-Ohm load resistor, with 25 Hz square wave input and gain set to produce +/-40-Volt peaks. (That actually gives 100 Watts RMS, per power rail, but not at the same time. So it makes a total of 200 W RMS if both polarities of the square wave are considered, but would make 100 Watts RMS, total, for a sine wave of the same peak amplitude.) Anyway, the 1000VA 44-0-44 transformer should be enough that the transformer ratings will not prematurely distort the output signal (i.e. it should not require atypically-large reservoir capacitances).

Image 1 shows the measured parameters for reservoir capacitors (one per rail) of 1000uF to 2500 uF each, stepping 500 uF each time, with the sequence of colors being (except fpr the top two plot panes): 1. bright-green/yellow, 2. blue, 3. red, 4. light-green. As can be easily seen, the output signal plot (second from bottom)and the calculated error (bottom plot), have large spikes, or glitches. One such set of error pulses is shown magnified, in the next plot.

Image 2 shows a zoomed-in view of one set of the spikes. It appears that there are spikes for 1000, 1500, and 2000 uF, but none for 2500 uF. So the capacitance was then stepped from 2000 uF to 2500 uF, with 100 uF per step.

Image 3 shows a zoomed-in area that had a larger remaining error than the area shown in the previous plots. It looks like 2200 uF is still distorted but 2300 uF might be OK.

Image 4 shows the same area as plot 3, but zoomed-in much more. Now we can see that 2300 uF DOES still have some of the distortion. It's only about 0.5 mV, out of 40 Volts. It might not be audible, but one purpose of this study is to find out where (at what capacitance level) this "obvious" type of PSU-induced distortion goes away, "completely".

So, we could be overly-ambitious and try to find out where, betweem 2300 and 2400 uF, the distortion disappears.

Image 5 has the graphs for the sweeps from 2300 to 2400 uF, with 20 uF per step. The distortion is no longer obvious, with the plots unmagnified. But we now know exactly where to look...

Image 6 shows a partially-magnified set of plots, so we can see the "context" of the remaining error glitch, which is just to the left of the 370 ms line.

Image 7 shows the glitch with additional magnification. Now we can see that 2300 uF still gives the glitch, but 2320 uF looks good. Bingo. (It's only doing an excursion of about 700 uV. But for 20 uF more, it can be gone.)

Looking only at the "flat" tops and bottoms of the square waves, there is still another type of distortion, which is shaped like the voltage rail voltage, and which is reduced as capacitance is added. It looks like less than +/-10mV, in the plots, with 10 mV being 0.025 % of 40 Volts.

(And, of course, without decoupling capacitances placed close-enough to the points of load, there are still error impulses coinciding with the rise and fall of each square wave.)

Tom
 

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I went to a great deal of trouble using much of these techniques for my version of the classic National gainclone: over sized transformer, huge array of caps, separate power planes, regulation. It was, is, virtually all power supply, the amp itself was a tiny, tiny part of the assembly.

And it worked, had no trouble hitting the bump stops without showing signs of stress. It had so much effective energy reserve that I could pull the power plug out of the wall while playing at a moderate volume level, and nothing would alter for many minutes, depending on what was playing, no change in tonality, etc.

Frank

You are my hero, Frank!
 
Theoretically, we could make the power supply impedance, AS SEEN BY the active power devices, as low as we wanted, just by using enough parallel pairs of conductors for power and ground.
Tom, I'm trying to visualize that without epic loops with hot/unstable devices but didn't manage. Have you got a handy sketch of what the concept might look like? You made it seem so interesting and I'm sorry that I can't visualize it.
 
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Tom, you and Frank both rock!

As far as parasitics are concerned:

stray inductance and ESR can conspire to make a "DC bus" much, much worse than expected. that aspect of this thread isnt about making super-duper circuitry, its about using standard RF engineering practices to stop PCB layout & wiring from ruining otherwise good designs.

Parallel multiple smaller axial electrolytics to minimise ESR & ESL and maximise lifetime (caps, like every other component, can only dissipate heat through their surfaces. to minimise temperature rise many small caps are better than few large caps (its that old surface-area-to-volume ratio again)). Not only that but variations of individual caps are "smoothed out" by the parallel network - if the ESR rises sharply in one cap, thats a real problem if its the only one; if its one of say 10 in parallel it matters a whole lot less.

And once you have decided on a bunch of caps in parallel, use a double-sided PCB (handmade or proper) and have one entire side as the 0V plane, with NO SLOTS.

I think a C-R-C filter is a good idea - place the rectifiers and main cap bank as close as possible to the xfmr, but still tightly twist/plait the interconnect. Then an R (if desired) can be placed in series with the amplifier interconnect (which should also be tightly twisted/plaitted) and the second cap bank (same excellent layout) should be placed at the amplifier itself (I would be tempted to thread a few turns of the amp psu interconnect braid through a high-perm ferrite toroid to make a CM choke).

this has the advantage of decoupling (har har) the rectifier and amplifier currents, making cap lifetime calcs much easier.

Placing a fuse in the amplifier supply rails is a free source of "R" - but make sure the fuse is between the supply and the amp cap bank, NOT between the caps and the driver transistors - the fuse can never protect the silicon (its there to stop fires), and all it does if placed between the caps & transistors is increase the interconnect inductance.

I've been looking at the SYMEF layout, and figuring out a nicer way to do it. conclusion: good layout is not easy to do - I'm not surprised so many amp layouts are so bad. I'm getting there (4 layers is OK, 2 layers is much harder), but I really dont like the air-core output inductor.
 
Daniel:

make a 100,000uF cap bank with 100 x 1000uF capacitors in parallel. arrange them in a 10x10 array, with even rows offset (not for packing density, but to ensure air flow around all the caps - no straight "corridors" for air to flow thru).

do this on a 1mm thick FR4 PCB. Make the entire top layer 0V, and the entire bottom layer V+. It'll be about 120mm square. stick a rectifier in the middle of the top edge.

then place the +ve output transistors at the bottom edge, again centered. congratulations, you now have a stupidly low inductance interconnect - its about 10nH/m inductance, so about 1.3nH total inductance. this is << the caps internal ESL (around 10-20nH) so they will share nicely.

obviously the width of the cap bank should correlate stringly with the width of the power stage. and you might want a cap bank for the negative supply. but you get the general idea.....
 
You have not read this Thread!
The output stage is being investigated.
The input stage is being treated as if it were perfect.
This is equivalent to saying that the PSRR is infinity and CMMR is minus infinity.

This Thread is not investigating the performance of a voltage amplifying stage. That should rightly be left to simulation of an amplifier.
This Thread is investigating the effect of PSU on the performance of the output stage.
 
Terry Given,
Any chance you could post a simple schematic or even better yet that and a sketch of the physical layout you would use for the multiple distributed capacitors in parallel with and without the CRC configuration. It's up to you but it would be greatly appreciated.I assume at some point there would still be a single film capacitor in parallel also?

Steven
 
I've been looking at the SYMEF layout, and figuring out a nicer way to do it. conclusion: good layout is not easy to do - I'm not surprised so many amp layouts are so bad. I'm getting there (4 layers is OK, 2 layers is much harder), but I really dont like the air-core output inductor.

Hi Terry and fas, everyone Come on and show some team spirit :D:D by joining me here http://www.diyaudio.com/forums/group-buys/217240-symef-2nd-generation-pcb-group-thing-2.html. Yes Terry do show and tell.

Also I have wonderful PCBs for you to experience here http://www.diyaudio.com/forums/parts/218661-28-1diffqc-pcbs-available.html.

Using these we can be able to explore ground truths in relation to theory:)
 
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Steven,

yeah I will post my attempt at a layout when I'm done. but its really as simple as it sounds - two big flat plates, one 0V and the other V+ (or V-), on opposite sides of the PCB. the trick is quite simply to not chop great big holes/slots into either plate.

the inductance per unit length of a parallel plate transmission line w metres wide with a separation of s metres is u0*s/w [H/m], where u0 = 4*pi*10^-7 = permeability of free space. so for a 120mm width and 1mm separation, L = 10.5nH/m.

It makes sense to have the local cap bank as wide as the power stage - conversely its not a smart move to make it much wider, or narrower, than the power stage. if much wider the caps on the edges wont carry as much current (reductio ad absurdum - if its 10x wider than the power stage then they sure as heck wont do much). If the cap bank is much narrower than the power stage, then the transistors at either edge are too far away from the cap bank.

Likewise with the depth of the capacitor bank - the distance between the DC input and the power stage. Current from the DC input needs to "spread out" across the full width of the cap bank, before it gets to the power stage. If we imagine a cap bank that is a single row of caps deep (so as shallow as it can be), then the input current cant spread out (current spreading is a diffusion equation, exactly the same as heat spreading).

you really dont want to try and figure it out analytically (dyadic Green's functions & Schwarz-Christoffel transformations can ruin an otherwise good day), FEA is much friendlier (by which I mean less un-friendly). evil learning curve and $$$ for the really good SW though - but something 2D and free like FEMM can model a step-change in conductor width very easily.

Back in the real world, I'd make sure the cap bank is fairly square - or at least not too rectangular - and call it quits at that. Because I am assuming we're NOT designing for manufacture (IOW down to a price) here - if we were, then a full analysis/FEA would be used to determine the absolute minimum dimension & no of caps (and I'd get paid).


As far as paralleling film caps: the neat thing about a pair of parallel plates is they act as a free, zero-inductance capacitor. FR4 Er = 4.5, so the capacitance is about 40pF*Width*Depth/Spacing. for our hypothetical 120mm x 120mm 1mm PCB, thats 1/2nF. If I were to use a 4-layer PCB with a thick core and 0.13mm prepreg between TL & ML1 (and also ML2-BL) then that would be more like 4.5nF of extremely broad-band capacitance.

EL caps are in metal cans, so when you parallel them you can pretty much ignore mutual coupling. This means that the ESL really does go down in proportion to the no. of caps, as does ESR. But with leaded film caps, this is not the case - mutual coupling interferes with the reduction in ESL of paralleled caps. I measured the ESL of a panasonic ECQ-E 100nF 630V cap as 5.9nH. two in parallel gave 4nH - 30% more than you would expect. This was done with a network analyzer and special test PCBs, using full one-port calibration and custom calibration standards (same PCB & SMA interconnect). The PCBs were 1mm thick parallel-plate transmission lines, with an SMT SMA connector in the center, underneath the cap or caps (separate PCB for two caps in parallel).

So when you parallel a bunch of N x EL caps and do it properly, you really do get ESR/N and ESL/N - up to the point where the PCB itself dominates. eg our 100 x 1000uF caps - at ESL = 15nH this suggests 15nH/100 = 0.15nH. But the PCB is about 1nH, so after you have about 10 caps in parallel the overall DC bus inductance reduces much more slowly and eventually reaches a limit.

translation: a well-laid-out parallel cap bank is actually pretty darned good - enough that leaded film caps just wont help.

BUT smt caps probably would help. Never, ever use any dielectric "higher-K" than X7R - they all contain titanium baranate (IIRC) and are quite piezoelectric, along with horrendous boltage and temperature coefficients. I once replaced a 1206 1uF Z5U cap with a 1206 220nF X7R cap and tripled the amount of capacitance - there was 20V DC on a 25V cap and a wide temperature range. At Tmax the Z5U cap gave about 70nF (no, thats not a typo).

there are some quite nice smt film caps available. the inductance of an smt cap is governed almost entirely by its case size - a 1uF 0603 cap has the same ESL as a 10pF 0603 cap (about 0.8nH). So use the largest cap value you can get in a given footprint.

Alas vias also have inductance - about 1nH or so. So use 3 x 0V vias on the smt cap, close to the three visible edges of the pad (not enough room to put one under the cap).

[if you are crazy about low ESL, try mounting smt resistors upside down.....doesnt work for caps though)

HTH
 
Also, I still say that the power and ground rails should be implemented using multiple separate parallel pairs of conductors, that stay separate all the way from the rectifier outputs to the load, with a separate capacitance for each end of each pair of power/ground conductors.
Without a sketch, I don't know what to make of it. However, that is obviously the answer to my parallel filters question, which was asked because the loss of series filters makes the transformer less effective. You've redeployed the cable runs that were already in place, used them parallel to make the ballast for faster charging (makes transformer more effective) and located capacitance closer to the load (makes capacitance more effective). Those steps appear to decrease the power supply reservoir size requirements somewhat. Even so, I can't quite get it in my head until I see it. I'm afraid I'd make a mess of it.
 
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Daniel and HTH,
I am all for seeing the implementation of this parallel capacitor layout. Terry, most of what I think that you are talking about would require me to do a board layout following your recommendations. Now I am building one of OnAudio's IDIFFQC boards and so I can't implement this with his per-existing boards. So the idea of a multistrand wired circuit parallel to the boards is what I am wondering about. How to implement that is the question? I'm not sure that I can even do that with a board that wasn't planned this way to begin with. Perhaps there is a way to route the power rails around the rest of the circuit and still have a portion of the supply bypass the rest of the board and feed the output devices directly? I will wait to see a simple schematic and component layout and see if I can figure this out.

Steven
 
Steven (HTH = Hope That Helps),

Toms suggestion is, on the surface, something that could be done easily - at least it looks that way. In practice its just like my suggestions re. parallel planes - the PCB needs to be designed that way right from the outset. In either case its really important to get the layout and cabling right, lest you make things worse - using multiple cables provides lots of opportunities to get it really, really wrong unless you grok Toms concept (which is a good one), and the PCB layout isnt much better in that regard.

When you have an amp that doesnt have much local decoupling, you'll want to sit your cap bank nice and close - this maximises inductive coupling, so you must tightly twist/plait the xfmr leads (which will be fairly long). and likewise with the PSU to Amp Dc bus leads.

The advantage of a hefty bank of caps at the amp is that it allows you to move the main cap bank closer to the xfmr (shorter xfmr leads) and further from the amp (longer DC bus leads). all the wiring still must be tightly twisted though.

When you make your cap bank, use a DIY 2-sided PCB. Use DS Cu-clad PCB material, with one side 0V and the other side V+ (or V- or both). If you use leaded caps its not very hard - the top-side lead gets bent at right angles & trimmed, the other lead needs a hole. Then the cap is inserted, the top lead is soldered on and then the underside.

by doing one cap at a time you can get decent packing density and keep the caps nice and flush to the PCB, without having to pay for the fabrication of a DS-PTH PCB. Attached is a photo of one I prepared earlier, which has 24 x 270uF 100V KZE caps in parallel, giving 6.48mF. You can see how I've made the PCb is as outlined above.

I'll measure the DC bus impedance, along with the impedance of a 12mF 25V electrolytic (I dont have a 6.8mF cap handy). I need to wait for the network analyzer to warm up though.....
 

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Terry,
So if I am following this correctly you have used a double sided board with solid cu planes on each side. I see the banks of capacitors, and I think that the diodes are hanging on the end and that is your bridge rectifier, next to that are the capacitor/resistor snubbers? What I am not sure about are the two devices that are closest to the capacitors? what are those? I get the idea you are presenting. I would think that the wires should probably be twisted tighter then I am seeing but that is about all. Thank you for showing this,

Steven
 
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