|31st January 2013, 05:11 PM||#1721|
Join Date: Dec 2007
I haven't made any chipamp where the PSU is overly important, so I cannot tell. The FM should be a bit better, and I buy them anytime the value fit.
At least they dont introduce pleasant distortions like the Silmic.
"The total harmonic distortion is not a measure of the degree of distastefulness to the listener and it is recommended that its use should be discontinued." D. Masa, 1938
|31st January 2013, 10:03 PM||#1722|
|1st February 2013, 03:51 AM||#1723|
The lower audio frequencies are not usually a big worry, when thinking about decoupling caps. But the higher audio frequencies definitely can be affected, which can ruin stuff that is dependent on accurate timing, such as phase angles of Fourier components, which could blur the details that probably play a large part in soundstage image perception.
Basically, as you get closer and closer to the point of load, you can have: the PSU itself (not including its caps), PSU's inductance, the PSU's caps, the rails' inductances, the board caps, the traces' inductances, the decoupling caps right at the point of load, the device pins' and lead-frame's inductances, and any on-device capacitance, then the actual point of load.
The distance from the point of load determines what frequencies each of those Cs and Ls can affect, mainly because of the inductance and the self-inductance associated with the lengths of conductors.
The pattern of capacitance, inductance, capacitance, inductance, ... is not accidental. The inductances make the impedance versus frequency plot slope upward and the capacitances try to bring it back down, hopefully keeping it under the maximum "target impedance" that we want the point of load to see, which is simply the p-p ripple we decide is acceptable, divided by the current draw that causes it.
For each set of caps mentioned above, you can either set a cap value and then calculate the maximum distance from the point of load that they could be, to still keep the target impedance within range, or, you can pick a distance and calculate the minimum capacitance required, to still stay under the target impedance at the point of load.
Either way, the common enemy is the inductance, due to the length of the conductors.
More-directly to your question, For the "right-at-the-output-device" decoupling caps, you will want to make sure that they can supply ALL of the current for the highest slew-rate that the device is capable of ever achieving, while assuming that it slews over the maximum-possible voltage range at that slew-rate. And that should NOT be limited to audio-frequency slew rates. That will give the MINIMUM VALUE of the decoupling capacitance. The reason it's just the lower bound is because we are only looking at the FASTEST slew rate. Even small-value caps can produce very large currents for a SHORT time. But slower slew rates would need LARGER caps.
That's easy to calculate and I'll do it in a second. But NOTE that you then MUST calculate how much conductor length, i.e. inductance, there can be, between the decoupling caps and the point of load, so that when that massive slewing occurs, the ripple voltage it creates does not exceed your chosen target, which is the same as saying that the target impedance ceiling is not broken.
Because of the inductance that comes with conductor length, we have to first find out what minimum cap value is needed, at up to what distance from the point of load, to be able to supply the fastest and largest slewing event.
For slightly-lower slew-rates, we would actually need a LARGER capacitance, but it could be a little farther away from the point of load, because even though being farther away will incur more delay due to more inductance and more ripple due to more inductance (V = L di/dt), the slew rate is slower so more delay can be tolerated, and since slew rate IS dv/dt a lower slew rate makes less voltage across any given inductance.
Interestingly, we can now see that if we increased the inductance (by increasing cap's distance from load) at exactly the same rate at which we lowered the slew rate (for which we increase the cap's value), then the p-p ripple would stay constant. So, when a target impedance is able to be implemented (which is not always the case), there is apparently a continuum of equivalent solutions for the cap value and the caps's distance from the point of load, which we can scout along until we find a location and size combination that is practical to implement!
In reality, the inductance limits the frequency that can be decoupled, no matter what capacitance we might try to use, so we need to have capacitances every so often, in increasing values as the distance from the load (inductance) increases, so that all of the frequencies are covered well-enough, which is just what we do, with PSU caps, board caps, and then decoupling caps right at the power devices.
We might also then guess that it's not a good idea to make jumps in capacitances, between those points, that are "too large". I would guess that each stage should be within a factor of 10 or 1/10th of the next or previous stage's capacitance. Otherwise, the anti-resonances that always appear between parallel capaitances, in the frequency-domain (network analyzer) plots of impedance, might have a big-enough frequency span to peak above our target impedance.
MINIMUM DECOUPLING CAPACITANCE at MAXIMUM SLEW RATE and EXTENT:
Ideal capacitor: i = C dv/dt
From my post at creating 1 watt rms power from 5 watt chip amp? :
C ≥ (1/2)∙(Δi∙Δt ) / (Δv - (ESR∙Δi))
which gives the minimum capacitance required such that when the current ramps linearly and changes by Δi Amps in Δt seconds, the voltage across the capacitance (typically, the power rail voltage) won't dip by more than your choice of Δv.
NOTICE that if the denominator of that equation gets close to zero, the C value would get extremely large. The denominator would go to zero when Δv - (ESR∙Δi) = 0, i.e. Δv/Δi = ESR. BUT Δv/Δi is none other than our "target impedance"!
In plain English, that means that if the ESR is not a lot lower than our desired target impedance, then we would need excessive values of capacitance.
40 Volts per microsecond into 4 Ohms, for one rail in a system that can push 200 Watts into 4 Ohms or 100 Watts into 8 Ohms:
Find the peak current. The peak output voltage would, coincidentally, be 40 Volts, since V_peak = sqrt(2*R_load*Power_rms).
Swinging from 0 Volts to 40 Volts across 4 Ohms would mean that the current would swing from 0 Amps to 40/4 = 10 Amps. And that would happen in one microsecond.
Since we don't yet know the capacitance, we don't know the ESR. So we'll leave it out and see what C value we get and then go re-calculate it with an estimated ESR (and we might then have to iterate using the ESR of the new C value, until the results stop changing by very much).
C ≥ (1/2)∙(Δi∙Δt ) / Δv (without ESR, tempoarily)
C ≥ (1/2)∙(10 Amps∙1 us ) / Δv
C ≥ 5 uF / Δv
If we choose Δv = 1 volt maximum ripple peak-to-peak, C would need to be at least 5 uF.
We should be able to get a very low ESR for 5 uF, especially if we parallel three or more small-ish film caps. So 10*ESR should be able to be much less than our 1-Volt Δv, so we shouldn't need to re-calculate the C equation, in this case.
NOW, we MUST check to see if it is even POSSIBLE to mount the capacitor(s) in order to get a low-enough inductance that the ripple doesn't go over our chosen value, 1 Volt in this case.
V = L di/dt
We have di/dt = 10 Amps / 1 us = 10 / 0.000001 A/us = 10000000 A/sec, and need the resulting V (our Δv) to be <= 1 Volt. So
1 = L x 10000000
L = 1/10000000 = 0.000000100 = 100 nH
We could estimate that allowing 100 nH allows a round-trip distance of 100 mm. So (whew!) that should be able to be implemented, although it will be more difficult than it might seem. The four connections, each cap lead and each device lead (power and ground), need to total less than 50 mm, MINUS the cap's lead spacing, minus the device's additional lead lengths (going all the way inside to the silicon).
We should also check the required capacitance value another way, and choose the larger of the two (i.e. either the one above or the following one, whichever is larger):
Since the magnitude of the impedance of a capacitance is Z = 1 / (2 Pi f C), we can solve for C for a given Z (Ohms) and f as:
C = 1 / (2 Pi f Z)
The frequency that is equivalent to the example rise time of 1 us is:
f = 1 / ( π ∙ trise )
f = 318 kHz
So we must stay within our target impedance limit up to at least 318 kHz.
We can calculate that in order to maintain our target impedance of Δv/Δi, we would need a total capacitance of at least
C >= 1 / (2 ∙ π ∙ f ∙ Δv/Δi)
= 1 / (2 ∙ 3.14 ∙ 318000 ∙ (1/10))
= 5 uF
Never mind. If we substitute the f(trise) equation into this C equation, it becomes, exactly, the earlier original C equation.
OK. THAT example turned out to look implementable, with a target impedance of Δv/Δi = 1 / 10 = 100 mOhms, which corresponded to 2.5% ripple.
But that assumed we could have a whole VOLT of ripple. What if we had wanted a target impedance of 20 mOhms (0.5% ripple), in order to get 0.2 Volt ripple?
That would mean a Δv = 0.2 Volt, which would mean
C ≥ 25 uF
which would mean a much larger ESR (unless we used much larger (or many more) paralleled film caps). So that C value would likely have to be increased, a whole lot, when we re-calculated with the original equation that inckudes ESR, unless our ESR could somehow be a lot less than 20 mOhms. We would almost be forced to use several paralleedl caps, to get the ESR that low. But that takes a lot more space on the board.
At the same time, the maximum allowable inductance in the decoupling network is now 20 nH instead of 100 nH. That's only roughly 20 mm, including the cap's lead spacing plus all of the conductors to and from the device's silicon. And that's the absolute maximum.
It's looking close to impossible to implement, at least with a standard through-hole DIY configuration, unless we used lots of parallel caps, arrayed on unbroken copper planes, with extremely short and fat connections between the planes and the output devices.
|1st February 2013, 04:09 AM||#1725|
|1st February 2013, 04:30 AM||#1726|
After all of THAT, we don't have a proper decoupling capacitance, yet. The 5 uF of film caps would only cover the highest frequencies needed, as far as we know. Lower frequencies, with the equivalent of slower slew rates, would require larger caps.
We could do a lot of math, or simulations, but as we have already seen, really-good specs can result in impossible implementation requirements.
We COULD laboriously calculate until we find what should work, by trying many different target impedances, or by trying many different distances from the load, or many different capacitances, until we think we have good-enough specs for all three and might be able to implement them.
OR, we could start by trying to do the PCB layout, and just see how much capacitance can be mounted, and how close to the point of load it could be, and work our way outword with larger and larger C values, mounted as densely as is practical. And then we could calculate, just once (and maybe with much-more-accurate inductance estimates), and see what maximum slew rate and maximum ripple and minimum impedance we were able to attain. (OR, if we really think that we couldn't ever do any better, and could never get any more capacitance mounted closer or with with lower inductance, and the specs will never satisfy us anyway, then there's no need to even calculate. Just build it, and then maybe measure it. :-)
For the second approach, we might put three or hopefully more film caps (probably using the largst value available in whatever case size is small-enough) as close to the device pins as we can possibly get them, with at least 5 uF but hopefully more, and hopefully with much less than the 100 nH of maximum inductance we calculated. Then add another "layer" of caps, slightly farther away, probably using 47uF to 220 uF electrolytics, as many as will fit. THEN we could move out farther and put some larger electros, although I would always want to use multiple smaller paralleled caps instead of one or two larger ones, at each stage. And always use as much copper as possible, to lower the inductance.
BUT, of course, FIRST, we should have calculated the maximum peak-to-peak ripple voltage that we could tolerate, starting from PSRR.
Last edited by gootee; 1st February 2013 at 04:58 AM.
|1st February 2013, 04:52 AM||#1727|
I just make it up
as I go along,
and then follow where it leads.
So it could be wrong.
Or maybe it's MORE like...
singing a song...
that goes on too long...
so everybody leaves.
|1st February 2013, 06:35 AM||#1728|
I used to read [memorize?] the Motorola power supply design guide books - no longer on hand - but 1000uf per amp sticks in my head as a general rule of thumb for a basic power supply - as a design trade-off for ripple & cost.
Rather than go overboard on trying to find a XX,000 uf cap [FOR ripple reduction], why not use a floating cap multiplier?
|1st February 2013, 09:58 AM||#1729|
Ripple reduction is secondary. It's more about being able to provide current accurately on demand. All of what you have mentioned has been discussed in ten different ways, here, already.
Last edited by gootee; 1st February 2013 at 10:04 AM.
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