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Old 31st October 2012, 01:32 AM   #1561
gootee is offline gootee  United States
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Capacitance of electrolytics changes radically with frequency, and temperature.

Cornell Dubilier has a nifty visualizer and impedance modeler (provides frequency-dependent/temp-dependent SPICE models for their caps), at:

Cornell Dubilier Plug-In Thermal / Life Calculator

Attached is a screenshot for a particular 1000 uF electrolytic.

If you design anything for low temperatures, you had better take a look. This one is fairly typical, in that sense.
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Last edited by gootee; 31st October 2012 at 01:36 AM.
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Old 31st October 2012, 01:49 AM   #1562
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Originally Posted by fas42 View Post
With regard to capacitance changing with frequency, I note on a Rubycon technical document that they acknowledge a loss with increase in frequency, due a combination of the condition of the etched surface, properties of the film as a dielectric, properties of the electrolyte, and the nature of the construction of the capacitor: they show a 10uF, 50V unit being down by about 15% at 20kHz. But only by that much ...

At the higher frequencies the ESR and construction becomes everything for getting effective decoupling, the actual true value of capacitance becomes almost completely meaningless ...

It's easy to know where one end of the decoupling caps should go -- to the power pins -- but where to attach the other end? My take is that it should be the ground point that the feedback network sees, which should be electrically equivalent at all frequencies to the ground of the audio input.

Frank
Where the other ends of the decoupling caps get connected can vary. But I think that for chipamps, and power output stages, it's usually the output/load ground, which should also be the Zobel ground. They supply the fast-rising current transients when the power output stage wants them.

You wouldn't want them sharing any conductor with your signal input ground, or any other low-level-type signals or their grounds.
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Old 31st October 2012, 02:12 AM   #1563
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Quote:
Originally Posted by fas42 View Post
With regard to capacitance changing with frequency, I note on a Rubycon technical document that they acknowledge a loss with increase in frequency, due a combination of the condition of the etched surface, properties of the film as a dielectric, properties of the electrolyte, and the nature of the construction of the capacitor: they show a 10uF, 50V unit being down by about 15% at 20kHz. But only by that much...
I too found that smaller value electrolytics fare better at HF than larger ones. For example 2,220uF became 425uF at 20kHz, 1,000uF became 280uF and 470uF became 200uF. My own take-away is to parallel smaller values rather than use one big one, however the topology of paralleling is up for grabs...
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Old 31st October 2012, 03:03 AM   #1564
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Quote:
Originally Posted by gootee View Post
Where the other ends of the decoupling caps get connected can vary. But I think that for chipamps, and power output stages, it's usually the output/load ground, which should also be the Zobel ground. They supply the fast-rising current transients when the power output stage wants them.

You wouldn't want them sharing any conductor with your signal input ground, or any other low-level-type signals or their grounds.
Obviously, the ground that the signal sees should always have as low an impedance with respect to other "grounds" within the component as possible. But, the actual ground point that the amplifying circuit sees, and especially that of the feedback network, should have the lowest level of high frequency noise on it that you can possibly achieve, with respect to all parts in that amplifying circuit, for it to function correctly, to have the lowest distortion. If there is noise in the ground lines elsewhere, even in the return from the speaker it's not as important as getting the ground clean for the crucial parts of the amplifying circuit.

From this perspective the decoupling cap should not be seen as a battery, rather as a snubber short circuiting high frequency noise ...

Frank
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Old 8th November 2012, 04:50 AM   #1565
gootee is offline gootee  United States
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Originally Posted by fas42 View Post
Obviously, the ground that the signal sees should always have as low an impedance with respect to other "grounds" within the component as possible. But, the actual ground point that the amplifying circuit sees, and especially that of the feedback network, should have the lowest level of high frequency noise on it that you can possibly achieve, with respect to all parts in that amplifying circuit, for it to function correctly, to have the lowest distortion. If there is noise in the ground lines elsewhere, even in the return from the speaker it's not as important as getting the ground clean for the crucial parts of the amplifying circuit.

From this perspective the decoupling cap should not be seen as a battery, rather as a snubber short circuiting high frequency noise ...

Frank
(I know that you know all of this, Frank. But I'll say it for the benefit of everyone else who might read this someday. (Also, maybe I didn't understand the context and am talking about something completely different. <grin> But I'm too lazy to go check.])

Yeah. But I meant that the actual decoupling caps, which go from power rail to ground, very close to an active point of load, should never share a ground conductor with any signal ground or other low-level or sensitive ground. If they did, then their typically large and dynamic currents would probably induce relatively large voltages across the inductance and resistance of any shared ground conductors, making your nice quiet ground into a bouncing ground. And the bouncing ground voltage would then arithmetically sum with anything using it as a reference, which would be "a BAD thing". Decoupling caps go to power and load ground, which should only connect to signal and other quiet reference grounds back at the star ground point, so they don't share any length of conductor.

For what you were talking about, I guess you would use separate caps, which wouldn't be called "decoupling" caps. The "decoupling" term means "decoupling a local power rail from the rest of the power rail network", in order to try to confine the large transient currents to a local loop, so as to not cause large voltage disturbances on other parts of the main power and ground rails due to trying to pull and push fast-rising currents through their parasitic inductances and resistances.
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Old 8th November 2012, 05:44 AM   #1566
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... been quiet lately, Tom ...??

Yes, the whole business of return and loop currents and grounds can become messy if one doesn't think it through, or use a tool like Spice. Rather than try and explain it a different way, I'll attempt to find an authoritive reference, or tutorial, somewhere on the net that has all the right diagrams on it, etc; give me a chance to find something good ...

Frank
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Old 8th November 2012, 07:41 AM   #1567
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Progress Update:

Just FYI, I am still working on a power supply spreadsheet (transformer, rectifier bridge, capacitor, and active load). I know that I said that it was almost done, way back when. But I found some problems and started a "deep dive" into it. Wow this sh!t is complicated and difficult. I think that I have well over half of it figured out, now. But implementing it has been a bit of a nightmare. However, if I can do it successfully, then it will probably be quite accurate. And it won't be only for finding Cmin.

It would have been far easier to just have people use the LT-Spice model that I have been using, especially now that we have the scalable transformer model, thanks to Terry Given, and AndrewT. But a spreadsheet will be far easier to use, for most people.

However, had I realized how many times I would think that I was done and then realize that there was still a major discrepancy somewhere, that I didn't understand, I might have given up, long ago. (I'm trying to not think about the possibility that I am at a similar point, yet again.)

One big revelation came, somewhat recently, when I saw that everything seemed to be looking very good EXCEPT where I was trying to account for the effects of transformer losses on the maximum rail voltage, due to the secondary resistance and the secondary and primary leakage inductances, during charging pulses.

At that point I was mainly working with peak values of everything, including the peak charging pulse current (because the peak values of things were relatively easy to calculate and were mostly all that was needed). I apparently hadn't thought about it enough and was thinking that I could multiply the peak rectifier current by the sum of the transformer impedances to determine the voltage drop and then subtract that from the peak input voltage divided by the turns ratio to get the secondary's peak output voltage.

Wow that was so wrong! Consider the charging pulse. A large swing of fast-rising current and then a large swing of fast-falling current. It goes through a resistance and... an inductance, in the transformer model. This is not like AC analysis. Think "time domain", with a one-shot pulse through an RL series network. The voltage across the resistor follows the shape of the current pulse exactly, with a peak voltage determined by its resistance. So far so good. But the voltage across the inductor is V = L di/dt. And di/dt, the slope of the current waveform vs time, is first a large positive number and then a large negative number. So the inductance basically gets two opposite-polarity voltage pulses across it, during each charging pulse. And it doesn't end at zero, at the end of the pulse. And the total series voltage across the inductance plus the resistance is needed, to calculate what happens to the secondary output voltage.

Actually, it's a little harder than that. The secondary "INPUT" voltage, at the output of the ideal transformer in the model (since the parasitics are separated out), during a charging pulse, is the theoretical secondary input voltage ("ideal" sinusoidal primary voltage divided by turns ratio) MINUS the voltage across the secondary leakage inductance. And, of course, VSEC_IN - VSEC_OUT = V_Ls + V_Rs, also.

I noticed, while studying time-domain plots of the various voltages and currents from simulations, that at the beginning and end of a charging pulse, at least, VSEC_OUT = V_primary/turns_ratio -2 * V_Ls - V_Rs. But V_Rs is zero at the beginning and end of the pulse, since the current goes to zero there (but the slope of the current vs time doesn't go to zero there). So the delta_VSEC due to a pulse is Vprimary/turns_ratio (at pulse end) - 2 * V_Ls (at pulse end) - Vprimary/turns_ratio (at pulse start). That's nice, except I didn't know how to calculate where the pulse start and end times were, in order to know where to pick the Vin values off of the input sine wave, so I'd be able to calculate the secondary's output voltage after a charging pulse (Hint: It can be well-above the "ideal" theoretical maximum peak secondary voltage!).

I had originally thought that VSEC_MAX was the theoretical peak secondary input voltage minus the voltage across the secondary leakage inductance at rectifier turn-off (pulse end), which would only require multiplying the final down-slope rate of the pulse by the leakage inductance. That turned out to not always be correct. But I did learn to use Excel's curve-fitting apparatus, and found a polynomial for the terminal slope of the charging pulses, under various conditions. But that equation changed for different VA and output power combinations. (So I started looking into converting sets of equations that give parallel plots in a plane into a more-general 2-D "field" equation. But it turned out that "parameterization" is probably the usual best way to go, for that.) But then I found a better way to account for different VA and output power ratings, for that equation (mentioned farther below).

I was able to plot all of the (simulation) voltages and currents that happen during a charging pulse, and had studied them so much that I finally deduced the simple equations showing which things add and subtract to produce the plots, which for some reason were just not obvious to me, at the beginning.

But there seemed to be no easy way to calculate the actual values needed, in a spreadsheet, without an closed-form mathematical equation for the charging pulse itself, i.e. some algebraic expression that would give current in amps if I plugged in a time value.

The charging pulses somewhat resemble half of a rectified sine, in shape. But unlike a rectified sinusoid the beginning has a gradual starting slope at first, and the whole thing is asymmetrical and "slanted" and stretched toward the right, while the trailing edge's slope usually just gets steeper until it hits zero. (It turns out that, in my simulations at least, those right-triangle-like pulse shapes that some scientific papers' authors have used as an approximate model for the pulses are only produced when the parasitics are removed from the transformer model.)

The charging pulses appeared to have the same basic shape and features, almost no matter what their peak values were. So I decided to "take the plunge" and measured about twenty or thirty data points from one, off of the LT-Spice plot window screen, with my mouse cursor, and put the "measured" times and currents into Excel columns. Then I used the Excel curve-fitting feature on that data and got a very good match by using a fourth-order polynomial. I measured two other ones, with different peak current values, too.

I can get the maximum peak rectifier current, in my speadsheet, already, quite accurately, through other means. So I thought that it would probably be helpful (to say the least) if I could somehow "scale" the pulse-shape equation from the one particular (16.36 Amp peak) rectifier pulse that I had an equation for, in order to be able to get an equation for a pulse that had any other peak value.

So first I plotted, in Excel, the widths of the bottoms of several charging pulses, in milliseconds, versus their peak amps. Then I used the Excel curve fitter again and got a second-order polynomial with zero error that will give the width of the bottom of a charging pulse (in milliseconds), given only its peak value.

I then shifted the pulse data so that time=0 was at the peak and re-fitted the original equation, for that situation. I also normalized both the pulse widths and the peak values and re-did that polynomial. That way, I could take a new peak value, calculate the width with the polynomial equation for that, and then use the original equation, but with the input time values simply scaled for the new width, and then scale the resulting current (amps) values by the new peak current divided by the one used for the original polynomial.

It works! And it's trivial to differentiate and integrate polynomials. So now I also have equations, as functions of time relative to the peak's time, for the slope at any point in time, ih Amps per millisecond, and for the area under the curve between any two points in time, for almost any size of rectifier charging pulse (for the particular transformer model parameters supplied by AndrewT, at least). And note that the slope, for which I now have an equation, is the same "di/dt" that is needed to calculate the voltage across the secondary leakage inductance at any time.

And the capacitor current's equations are now also known, since it's just the rectifier current minus the load current and my load current is a simple square wave.

The rectifier pulse width also determines the exact time interval (or, equivalently, the phase angle range) for where the input sine wave gets "hacked into", during the charging pulses.

So now, that simple equation that I gave earlier, for the "delta Vsecondary due to a charging pulse", will become very useful, as soon as I get one more step completed, which is calculating the exact time when the decaying capacitor voltage runs into the next rectified sine peak (or maybe the one after that, in some cases). It shouldn't be too difficult. It just happens to be the step I'm on right now, thanks to the fact that I now finally have a way to use that information to continue on and calculate the actual solution.

It turns out that finding that intersection point, between the decaying exponential capacitor voltage and the rectified sinusoidal input voltage, can ONLY be done numerically (or graphically), since there is no closed-form mathematical solution for a transcendental equation such as that. So it's a good application for a computer.

I will (almost certainly) also have to go back one more time, at least, and re-do all of the charging-pulse-related equations. Earlier, when I was playing around with curve-fitting an equation for the maximum downslope at the end of a charging pulse, I eventually figured out that I could make it work for more than one output power and VA rating if I first multiplied the independent variable (the peak current value of a pulse for which the ending slope was desired) by the output power divided by the VA rating, and then curve-fitted to find the equation.

Then I could just first multiply any desired new peak charging pulse current value by Watts/VA, and then plug the result into the polynomial that had been found by Excel's curve fitter, and get the correct final slope for a charging pulse of any height, for any output power and transformer VA rating that was being used.

So I assume that I will need to do something similar for the pulse_amps(t) polynomial and the related equations for its derivative (slope) and integral (area under curve). "So many fun things to do. But so little time."

At any rate (at some rate?), I think that I will eventually get it done.

Cheers,

Tom

Last edited by gootee; 8th November 2012 at 07:57 AM.
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Old 8th November 2012, 08:49 AM   #1568
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Okay, Tom, I think I have the material that puts your point of view precisely: Ott's article "Ground - A Path for Current Flow". Here there are 4, yes, 4 separate grounds: power supply, amplifier, signal input, and load grounds for a highly conventional, single voltage, non feedback amp. All with significant impedance between them. But, the trouble with opamps is that there is no amplifier ground, no pin to which ground attaches, 2 supplies, and a very highly sensitive feedback network. In all, a different situation ...

So, I shall do some exploring to find, or work out, a "best" resolution ...

Frank

Last edited by fas42; 8th November 2012 at 08:52 AM.
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Old 8th November 2012, 09:56 AM   #1569
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Ciao my friends!

The JVC cdp is still on the surgery table... so no feedback, yet.

Forgive me but I was simply thinking of placing a bunch of 330u/100V near the output transistors of a power amp. So, one leg to the "+" power rail, fine. The other leg to load common (i.e. speaker return) as per Ott's article (I found on http://www.electro.fisica.unlp.edu.a.../GROUNDS_2.pdf) should do the trick, correct?
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Old 8th November 2012, 10:02 AM   #1570
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Quote:
Originally Posted by tsiros View Post
just a thought: a bank of smaller caps is better than two XBOX HUGE caps, because when they fail it will be cheaper to replace one 10 mF instead of one 100 mF

when i said there can't be too much capacitance it is implied that the rest of the circuit is built to withstand the current they will demand.

now i have to think what happens when you start up a psu (tranny-rect-caps).

the transformer will provide as much current as the capacitors demand. which is, how much? is it limited? i think not. So it will peak. Perhaps then a circuit should delay turning on the psu until the AC crosses zero so at least that way it won't be BAM max current to the caps

but isn't the transformer also a set of coils? doesn't it have inductance? perhaps it is too small to delay rising of the current... or it already does that so it doesn't matter

hm. it's time i put the oscilloscope to my amp's psu. now, where did i stash that fire extinguisher...
Such a device does exist. It is a relay guaranteed to close at a zero crossing of AC. Look for zero-voltage switching relay.
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