Hi Guys,
I am building a power supply for a pair of LM3886 amplifiers, the circuit which i will be using has two 10,000 uf, one each for the positive and negative supply.
it is difficult getting those caps in the place i stay but i have a lot of 4700 uf caps with me which i would like to use in parallel ( 2 x 4700 = 9400 which should be ok i guess)
my question is that are they any advantages in using a single capacitor in the power supply rather using two capacitors of smaller values in parallel, also noticed many schematics are using 2 x 10,000 uf for each rail (total 4 caps for both the rails), are those really required or 10k uf per rail would suffice
Thanks in adv
I am building a power supply for a pair of LM3886 amplifiers, the circuit which i will be using has two 10,000 uf, one each for the positive and negative supply.
it is difficult getting those caps in the place i stay but i have a lot of 4700 uf caps with me which i would like to use in parallel ( 2 x 4700 = 9400 which should be ok i guess)
my question is that are they any advantages in using a single capacitor in the power supply rather using two capacitors of smaller values in parallel, also noticed many schematics are using 2 x 10,000 uf for each rail (total 4 caps for both the rails), are those really required or 10k uf per rail would suffice
Thanks in adv
I'd use the 4700uF caps, three of them per rail. You should be ok using two as LM3886 has pretty decent supply noise rejection, but I'd go for the three just to be sure as you have nothing to lose and the supply will be smoother that way too with less headroom lost to ripple. Using parallel caps helps as you halve the ESR and the cap's inductance. I never use 10mF caps as they are expensive and you have to take into account the ripple current.
DF96 is correct.
With rail capacitance, in general, more is better. There are a few exceptions to this, but not with linear power supplies for the amp you're describing.
Regarding your setup, 10,000uF per rail is fine. So would 20,000uF per rail, as would 4,700uF X 2 per rail, or 2,200uF X 5 per rail, or 4,700uF X 5 per rail, etc., etc. As long as it fits, is constructed well, and both the + and - rails are symmetrical, you should be fine! In fact, there can actually be advantages with multiple, paralleled caps including reduced impedance, reduced ESR and ESL, reduced ripple current per cap, etc. There are some negatives too, but nothing to worry about at this level.
I would also add some film-caps in parallel with the big caps too. A couple 0.1uF mono-ceramics or film caps can help at high frequencies. Just make sure their rated voltage is above the supply voltage too.
With rail capacitance, in general, more is better. There are a few exceptions to this, but not with linear power supplies for the amp you're describing.
Regarding your setup, 10,000uF per rail is fine. So would 20,000uF per rail, as would 4,700uF X 2 per rail, or 2,200uF X 5 per rail, or 4,700uF X 5 per rail, etc., etc. As long as it fits, is constructed well, and both the + and - rails are symmetrical, you should be fine! In fact, there can actually be advantages with multiple, paralleled caps including reduced impedance, reduced ESR and ESL, reduced ripple current per cap, etc. There are some negatives too, but nothing to worry about at this level.
I would also add some film-caps in parallel with the big caps too. A couple 0.1uF mono-ceramics or film caps can help at high frequencies. Just make sure their rated voltage is above the supply voltage too.
"Whenever you need a capacitor over about 10µF, it's best to build up the capacitor from several smaller capacitors. For example, I keep a couple hundred 2.25µF mylar capacitors on hand, and if I need a 13µF capacitor, I use six 2.25µF capacitors in parallel. Alternatively, you could use a MultiCap, but a 13µF MultiCap costs about $35, and six 2.25µF mylars cost about $4.50. A 13µF non-polar electrolytic costs about 75¢, and, unfortunately, sounds like about 75¢.
The reason for adding up many small capacitors is that the capacitors have inductance and lead resistance, which make the capacitor less useful. When you place resistors and inductors in parallel, their effect shrinks, but the capacitor's effects add. So, building up large capacitors by placing several small capacitors in parallel makes our capacitors act more like perfect capacitors. This is a good thing."
taken from here;
The Crossover Design Cookbook Chapter 2: How Components Work
The reason for adding up many small capacitors is that the capacitors have inductance and lead resistance, which make the capacitor less useful. When you place resistors and inductors in parallel, their effect shrinks, but the capacitor's effects add. So, building up large capacitors by placing several small capacitors in parallel makes our capacitors act more like perfect capacitors. This is a good thing."
taken from here;
The Crossover Design Cookbook Chapter 2: How Components Work
As usual Rod Elliott has some nice explanations. I suggest that you read all of the article, but you can go directly to "Capacitor Ripple Current" approx. 4/5 down the page:
Elliott Sound Products - Linear Power Supply Design
Karsten
Elliott Sound Products - Linear Power Supply Design
Karsten
Multiple smaller caps in parallel is almost always better than one larger cap of equivalent value.
Be careful about adding a small film cap in parallel with a large electrolytic. It is practically guaranteed that you will create a resonant LC tank, which is not good to have in a circuit like this. Also, if your power and ground rails are more than a couple of inches long, then the small film cap can do absolutely no good for what happens at the load, at the other end of the rails, which is the only place that matters. Because of the parasitic self-inductance of the power and ground rails, any high-frequency demands by the load can only be met by a cap that is right at the load. So put the small film cap only there, if you put one anywhere.
While it is important to have enough smoothing and reservoir capacitance in the PSU itself, in order to not have too much ripple and in order to be able to supply the load's large low-frequency current demands and steady-state current demands, it is AT LEAST as important to have properly-configured capacitance at the active load.
Because of the parasitic self-inductance of the power and ground rails between the PSU and the load, any sudden demands for current by the load can only be met by the decoupling capacitors, which are placed as close as possible across the active load's power and ground pins.
For your chipamp the decoupling caps will need to be at least an absolute bare minumum of 220 uF per rail but ten times that would probably be much better.
THAT is where the "parallel capacitors" idea becomes really interesting and much more useful:
It turns out, if you do the math, and look at a typical LM3886 layout, that it's actually very difficult to get enough capacitance close-enough to the chip's pins, with low-enough total inductance, in order to not degrade the chip's transient-response capability.
That's where the benefits of paralleling really come in handy, and are probably actually required, in this case, for best performance (and possibly even for "good enough" performance).
But there's a potential "gotcha" when paralleling caps in order to lower the total inductance:
Inductance does reduce, just like resistance reduces, when paralleled. BUT, it turns out that unless there is no MUTUAL inductance, it wrecks the algebra and you don't get the full reduction that would be expected if paralleled inductors always reduced in value just like resistors do.
So in order to get the full inductance reduction from paralleling, they have to have completely-separate connections, and not share any length of conductor.
So when you use multiple parallel decoupling caps, their pcb traces or leads should stay separate all the way to the power and ground pins of the chip, if possible. (And note that the PCB traces or wires will be the major contributors, to the inductance of the decoupling caps. Most caps don't have any real inductance, except for the equivalent of a conductor as long as their lead-spacing.)
i.e. You shouldn't just bring two traces out from the power and ground pins and line up some caps in parallel on them.
However, since each smaller cap would handle less current, you could just use a set of smaller parallel traces in place of a single trace for one larger cap, and only use a little more width than the original single trace's width.
The inductance benefits of paralleling the caps and their traces are really pretty amazing. If you do the math, it turns out that:
If you replace one large cap with N caps with values 1/N, then the total inductance will be at least as good, as long as each of the separate parallel sets of traces are less than or equal to N times the original single cap's trace length.
If you think about it, it's pretty amazing: We could replace one large cap that would need to have a total trace length of, say, two inches, INCLUDING the cap's lead-spacing (which would be almost impossible to do with one large cap for each rail in an LM3886 layout), with, say, three smaller caps, and we could put those caps three times farther away from the pins and they would work just as well! And they're smaller caps, so placing even a larger number of them, farther away from the pins, should be much easier than placing one large cap.
However, that's only getting us the SAME level of performance. Shouldn't we be shooting for a significant improvement? Here's the same rule, stated slightly differently:
If you could use N caps instead of one, and their separate parallel connections' lengths could each be LESS than N times as long as those of the original single cap, then it would be an improvement.
So if we could place the smaller caps so that they were about the SAME distance from the pins as the single larger cap was, then that would be MUCH lower inductance; only 1/N as much inductance!
It's all about having a low-enough power supply impedance, AS SEEN AT THE DEVICE's POWER PINS, not at the power supply's output at the other end of the power and ground rails.
More capacitance means lower impedance. Less inductance means lower impedance. And less resistance means lower impedance. Paralleling of capacitors AND their connections improves all three components of the impedance. And using SHORTER conductors improves both the inductance and resistance components of the impedance.
Since you're building a dedicated chipamp power supply, here's a way to max-out the PSU performance that won't cost anything except a little bit of real-estate on your PCBs, or a little extra wire. But it will lower the impedance seen at the device pins, even from all the way across the power and ground rails, by a factor of N, where you get to choose N. So you can make it AS LOW AS YOU WANT.
There are practical limits, unfortunately. In the case of an LM3886 layout, it might depend on whether your PCB is single or double sided. But it will probably depend on how many parallel traces you can comfortably route to the power pins. And either the negative pin in the back (which will probably be near the board edge for easy heatsink mounting) will be the bottleneck, or, the spacing between the pin rows, to get traces to the inner positive pin, will be it. If you can use a double-sided PCB and put the ground traces on the top side, you might get the most room for parallel power traces on the bottom side. Alternatively, you might be able to "get creative" with added discrete wires, if you wanted to push N higher.
At any rate, here's what you could do:
In the PSU, starting right at the output of the rectifier bridge, use parallel traces or wires for both the rectified (DC+) and ground (-) conductors, using the same number of conductors for each of those as the number of smoothing caps you will parallel for each rail.
For example, for the positive rail, if you use three smoothing caps, then run three conductors from the rectifier + output, one to the plus of each cap. And run three conductors from the rectifier's Gnd or - output, one to the neg/gnd end of each cap. Then run three parallel V+ rail conductors, instead of one, all the way to the amp's V+ power pin(s) (one from each cap), and run three ground rails (one from each cap) almost all the way to the chip's V+ pin(s).
At the amp, as close to the chip's power pins as you can get them, put one decoupling cap across each of the three sets of parallel power and ground rails.
That's it!
That should give you much-more-robust performance than the typical chipamp, stronger and more accurate in both bass and treble, and with much better timing and time-alignment accuracies, and transient response performance characteristics, which should help, quite significantly, in providing a very powerful and rich yet crystal-clear, precise, and accurate soundstage image.
Sorry about the long post.
CHeers,
Tom
Be careful about adding a small film cap in parallel with a large electrolytic. It is practically guaranteed that you will create a resonant LC tank, which is not good to have in a circuit like this. Also, if your power and ground rails are more than a couple of inches long, then the small film cap can do absolutely no good for what happens at the load, at the other end of the rails, which is the only place that matters. Because of the parasitic self-inductance of the power and ground rails, any high-frequency demands by the load can only be met by a cap that is right at the load. So put the small film cap only there, if you put one anywhere.
While it is important to have enough smoothing and reservoir capacitance in the PSU itself, in order to not have too much ripple and in order to be able to supply the load's large low-frequency current demands and steady-state current demands, it is AT LEAST as important to have properly-configured capacitance at the active load.
Because of the parasitic self-inductance of the power and ground rails between the PSU and the load, any sudden demands for current by the load can only be met by the decoupling capacitors, which are placed as close as possible across the active load's power and ground pins.
For your chipamp the decoupling caps will need to be at least an absolute bare minumum of 220 uF per rail but ten times that would probably be much better.
THAT is where the "parallel capacitors" idea becomes really interesting and much more useful:
It turns out, if you do the math, and look at a typical LM3886 layout, that it's actually very difficult to get enough capacitance close-enough to the chip's pins, with low-enough total inductance, in order to not degrade the chip's transient-response capability.
That's where the benefits of paralleling really come in handy, and are probably actually required, in this case, for best performance (and possibly even for "good enough" performance).
But there's a potential "gotcha" when paralleling caps in order to lower the total inductance:
Inductance does reduce, just like resistance reduces, when paralleled. BUT, it turns out that unless there is no MUTUAL inductance, it wrecks the algebra and you don't get the full reduction that would be expected if paralleled inductors always reduced in value just like resistors do.
So in order to get the full inductance reduction from paralleling, they have to have completely-separate connections, and not share any length of conductor.
So when you use multiple parallel decoupling caps, their pcb traces or leads should stay separate all the way to the power and ground pins of the chip, if possible. (And note that the PCB traces or wires will be the major contributors, to the inductance of the decoupling caps. Most caps don't have any real inductance, except for the equivalent of a conductor as long as their lead-spacing.)
i.e. You shouldn't just bring two traces out from the power and ground pins and line up some caps in parallel on them.
However, since each smaller cap would handle less current, you could just use a set of smaller parallel traces in place of a single trace for one larger cap, and only use a little more width than the original single trace's width.
The inductance benefits of paralleling the caps and their traces are really pretty amazing. If you do the math, it turns out that:
If you replace one large cap with N caps with values 1/N, then the total inductance will be at least as good, as long as each of the separate parallel sets of traces are less than or equal to N times the original single cap's trace length.
If you think about it, it's pretty amazing: We could replace one large cap that would need to have a total trace length of, say, two inches, INCLUDING the cap's lead-spacing (which would be almost impossible to do with one large cap for each rail in an LM3886 layout), with, say, three smaller caps, and we could put those caps three times farther away from the pins and they would work just as well! And they're smaller caps, so placing even a larger number of them, farther away from the pins, should be much easier than placing one large cap.
However, that's only getting us the SAME level of performance. Shouldn't we be shooting for a significant improvement? Here's the same rule, stated slightly differently:
If you could use N caps instead of one, and their separate parallel connections' lengths could each be LESS than N times as long as those of the original single cap, then it would be an improvement.
So if we could place the smaller caps so that they were about the SAME distance from the pins as the single larger cap was, then that would be MUCH lower inductance; only 1/N as much inductance!
It's all about having a low-enough power supply impedance, AS SEEN AT THE DEVICE's POWER PINS, not at the power supply's output at the other end of the power and ground rails.
More capacitance means lower impedance. Less inductance means lower impedance. And less resistance means lower impedance. Paralleling of capacitors AND their connections improves all three components of the impedance. And using SHORTER conductors improves both the inductance and resistance components of the impedance.
Since you're building a dedicated chipamp power supply, here's a way to max-out the PSU performance that won't cost anything except a little bit of real-estate on your PCBs, or a little extra wire. But it will lower the impedance seen at the device pins, even from all the way across the power and ground rails, by a factor of N, where you get to choose N. So you can make it AS LOW AS YOU WANT.
There are practical limits, unfortunately. In the case of an LM3886 layout, it might depend on whether your PCB is single or double sided. But it will probably depend on how many parallel traces you can comfortably route to the power pins. And either the negative pin in the back (which will probably be near the board edge for easy heatsink mounting) will be the bottleneck, or, the spacing between the pin rows, to get traces to the inner positive pin, will be it. If you can use a double-sided PCB and put the ground traces on the top side, you might get the most room for parallel power traces on the bottom side. Alternatively, you might be able to "get creative" with added discrete wires, if you wanted to push N higher.
At any rate, here's what you could do:
In the PSU, starting right at the output of the rectifier bridge, use parallel traces or wires for both the rectified (DC+) and ground (-) conductors, using the same number of conductors for each of those as the number of smoothing caps you will parallel for each rail.
For example, for the positive rail, if you use three smoothing caps, then run three conductors from the rectifier + output, one to the plus of each cap. And run three conductors from the rectifier's Gnd or - output, one to the neg/gnd end of each cap. Then run three parallel V+ rail conductors, instead of one, all the way to the amp's V+ power pin(s) (one from each cap), and run three ground rails (one from each cap) almost all the way to the chip's V+ pin(s).
At the amp, as close to the chip's power pins as you can get them, put one decoupling cap across each of the three sets of parallel power and ground rails.
That's it!
That should give you much-more-robust performance than the typical chipamp, stronger and more accurate in both bass and treble, and with much better timing and time-alignment accuracies, and transient response performance characteristics, which should help, quite significantly, in providing a very powerful and rich yet crystal-clear, precise, and accurate soundstage image.
Sorry about the long post.
CHeers,
Tom
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Low ESR and low ESL for that matter is verry important in SMPS, but linear PSU's are not that much affected by those factors, so you could do just well with both configs, granted more paraleled caps gives some advantage but not that big as to force you to use it.
Nice day to all
Yeah, low ESL would probably be wasted because the power and ground rails' self-inductances would probably swamp it out, anyway.
Low ESR might be needed or desirable in order to be able to pass the ripple current without as much self-heating of the caps. Paralleling higher-ESR caps can help with that.
True there. I've seen some class A amps where the 10,000uF res cap can get really toasty. It's important to choose a cap with a high temperature rating to make sure it'll last long enough under those sort of conditions. With multiple caps, this problem is much less important, but when I've built Class A amplifier's I've always gone with two 4,700uF caps in favour of a 10,000uF one. For Class B amps, when the current is not constant, then it probably doesn't matter. It really depends on how much current for how much time you want from your power supply.
I think this thread is of interest to many of us, so my 2 cent.
If I look at the esl of big caps (and was has been in the old days) it seems to me that now days most "big" electrolytic caps have to be made up of multiple internally connected smaller caps with the shortest possible path between them. The thereby achievable low esl is hard to beat by a bank of external parallel connected caps. I do not know, but I could imagine that a smart manufacturer would also know how to take advantage of the possibility to stagger and/or damp the resonances of the internal caps and adjust the esr for proper damping. When I look at some short and very thick Rifa caps (with there superb ratings) I look at something that will be hard to beat with DIY paralleled caps (except for cooling and lower cost). Remember the smallest possible loop Gootee often talks about? It gotta be inside those big SMPS caps....
If I look at the esl of big caps (and was has been in the old days) it seems to me that now days most "big" electrolytic caps have to be made up of multiple internally connected smaller caps with the shortest possible path between them. The thereby achievable low esl is hard to beat by a bank of external parallel connected caps. I do not know, but I could imagine that a smart manufacturer would also know how to take advantage of the possibility to stagger and/or damp the resonances of the internal caps and adjust the esr for proper damping. When I look at some short and very thick Rifa caps (with there superb ratings) I look at something that will be hard to beat with DIY paralleled caps (except for cooling and lower cost). Remember the smallest possible loop Gootee often talks about? It gotta be inside those big SMPS caps....
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Although some of the capacitor manufacturers are certainly doing a wonderful job, I wouldn't give up on trying to get even-lower impedance, just yet.
Paralleling a number "n" of the best-designed capacitors, preferably using two closely-spaced copper planes for the connections, would have to lower the inductance even further, maybe not all the way down to 1/n as much, but probably as close as you wanted, especially if there were no other constraints on the board size and cap positioning.
Even just using "standard" electrolytics from the old days, you can get inductance down to less than 0.5 nH, just by using a thin PCB (1 mm) and leaving all of the copper on both sides of the PCB. You can just drill one hole for each cap (and remove the copper around the edges of the holes) and mount something like 100x 1000uF, and get below 0.5 nH (until you connect it to something).
Actually, most capacitors don't have much intrinsic inductance, anyway, except for the equivalent of the self-inductance of a piece of wire that is the same length as the capacitor's lead spacing (plus the actual remaining lead lengths, after mounting), probably on the order of 1 nH per mm of lead spacing plus lead length. But the total parasitic resistance (ESR) is also reduced, by paralleling.
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Note that my earlier posts in this thread about paralleling caps using separate parallel traces were a bit misguided. While it could theoretically be made to work, the mutual inductances would be difficult to eliminate, in most cases, which would inhibit the reduction of the total ESL due to paralleling (i.e. it would not go down to very near 1/n as might have been expected). So it would probably be much more easily made effective by using closely-spaced copper planes, for the connections.
Paralleling a number "n" of the best-designed capacitors, preferably using two closely-spaced copper planes for the connections, would have to lower the inductance even further, maybe not all the way down to 1/n as much, but probably as close as you wanted, especially if there were no other constraints on the board size and cap positioning.
Even just using "standard" electrolytics from the old days, you can get inductance down to less than 0.5 nH, just by using a thin PCB (1 mm) and leaving all of the copper on both sides of the PCB. You can just drill one hole for each cap (and remove the copper around the edges of the holes) and mount something like 100x 1000uF, and get below 0.5 nH (until you connect it to something).
Actually, most capacitors don't have much intrinsic inductance, anyway, except for the equivalent of the self-inductance of a piece of wire that is the same length as the capacitor's lead spacing (plus the actual remaining lead lengths, after mounting), probably on the order of 1 nH per mm of lead spacing plus lead length. But the total parasitic resistance (ESR) is also reduced, by paralleling.
-----
Note that my earlier posts in this thread about paralleling caps using separate parallel traces were a bit misguided. While it could theoretically be made to work, the mutual inductances would be difficult to eliminate, in most cases, which would inhibit the reduction of the total ESL due to paralleling (i.e. it would not go down to very near 1/n as might have been expected). So it would probably be much more easily made effective by using closely-spaced copper planes, for the connections.
Esr cannot much be reduced because the main contribution is from the liquid. Just thinck for instance what would be the difference between a cap of 10000uF and a bank of 10x1000? Materials are the same (aluminium, liquid), voltage is the same (roughness of the etching, thickness of oxilayer), capacitance and currentdensity is the same (area). Look how much esr changes with aging, temp, frequency a.s.o. The rest of the esr is not much of a "R", might even be better than in a lousy built solid cap and is also pretty stable if welded. I personally prefer a rod connection any time instead of a dozen tiny soldered pins, even if the rod is tied to a internal "fuse" that migth increase R a bit. Esr makes us easely think of the qualities of a resistor and we may also thinck a wet caps esr is the same animal than a solid caps esr....
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Hi gootee.
Off course you know that reducing esl, 1/n wont be close to possible even in theory, the more caps you ad the more diminishing results you get. And for a cap to be of low esl construction it has to be short and thick and "thicker" means longer interconnections. What you win in the cap you will loose at the interconnection and vice versa. But despite of that, I am glad someone finally gave proper attention to where it really should be, not at the esl of the caps, but at the way they are connected to the source, to each other, and to the load. I am now days more dealing with higher impedance tube circuits and esl is not much of a problem. in the old days, when I specialized into Rf-heating, paralleling caps and routing connections could get very expensive when done the wrong way. Conductors as wide as they are long, triple sandwiching with optimized distance between them (to keep proximity losses and/or electromagnetic forces in check) all those options I have all least tried, but more often than once the results where not as good as theory might promise. At high power frequencies and at currents of hundreds sometimes even thousands of amps results could often easily be seen in the form of heat patterns, bulging conductors a.s.o.
Capacitor banks of (necessarily) low esr high power caps proved to be a highly risky business. If they got unintentionally exited at some unwanted but unavoidable resonance it was just as dangerous as it was expensive. May be that is also one of the reasons I seem now days allergic to paralleling capacitor. Btw, the spacing of the connections of the caps would still leave much room for improvement, especially at low voltages the spacing is far to wide.
Off course you know that reducing esl, 1/n wont be close to possible even in theory, the more caps you ad the more diminishing results you get. And for a cap to be of low esl construction it has to be short and thick and "thicker" means longer interconnections. What you win in the cap you will loose at the interconnection and vice versa. But despite of that, I am glad someone finally gave proper attention to where it really should be, not at the esl of the caps, but at the way they are connected to the source, to each other, and to the load. I am now days more dealing with higher impedance tube circuits and esl is not much of a problem. in the old days, when I specialized into Rf-heating, paralleling caps and routing connections could get very expensive when done the wrong way. Conductors as wide as they are long, triple sandwiching with optimized distance between them (to keep proximity losses and/or electromagnetic forces in check) all those options I have all least tried, but more often than once the results where not as good as theory might promise. At high power frequencies and at currents of hundreds sometimes even thousands of amps results could often easily be seen in the form of heat patterns, bulging conductors a.s.o.
Capacitor banks of (necessarily) low esr high power caps proved to be a highly risky business. If they got unintentionally exited at some unwanted but unavoidable resonance it was just as dangerous as it was expensive. May be that is also one of the reasons I seem now days allergic to paralleling capacitor. Btw, the spacing of the connections of the caps would still leave much room for improvement, especially at low voltages the spacing is far to wide.
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seriously 0.5nH with standard electrolytis? Are you kiddn me? Please tell me more about how you did that and especially how you measured it
It was done by a famous electromagnetics engineer from New Zealand named Terry Given (at home with a hand drill and a simple soldering iron and a blank 2-sided PCB) and measured with his HP 3577A vector network analyzer, from 5 Hz to 220 MHz. Results were reported on diyaudio.com, plots and all.
So yes, you really CAN reduce ESL (and ESR) by paralleling caps, even electrolytics. It's done all the time. Look up the stuff on the web by Bruce Archambeault and Henry W. Ott, among many others. Or just TRY it.
"In theory", reducing ESL works by the same equations that we use for reducing resistance by paralleling resistors. So yes, in theory, it CAN be done, and can be made as low as you want. And in reality, if the caps and their connections don't have any _mutual_ inductance, reality would match theory. Otherwise, the equations get more complicated and the effect is partially negated.
Here is a link to (most of) the collected links to the Terry Given posts about the cap array:
http://www.diyaudio.com/forums/chip-amps/224914-lm3886-component-selection-3.html#post3282640
I am probably going to use such arrays as the power/gnd rails for my next amplifier build. I'll mount the amplifier components on a daughterboard that is a mm or two above the cap arrays, over the line where the cap arrays meet (one 2-sided array for each rail, on either one or two 2-sided pcbs, total), so that the power and gnd connections will only be two or three (or four) mm long (I'm still deciding on how to interconnect, actually). If I use an LME49830 with lateral mosfets, for example, the power and gnd pins could go straight down through the daughterboard and directly into the array boards, if I can get the layout correct for that AND still be able to solder them; i.e. the ones that needed to go to the TOP side of the array PCB would need to all be at the edge of the daughterboard (unless I make some 1/2-inch holes that I can put the soldering iron through). The daughter board shouldn't need any decoupling caps, and its layout ought to be much easier (and thus better), since power and ground won't need to be on there, except right where they're needed (and I imagine I will use some ground plane on the daughterboard, actually).
So yes, you really CAN reduce ESL (and ESR) by paralleling caps, even electrolytics. It's done all the time. Look up the stuff on the web by Bruce Archambeault and Henry W. Ott, among many others. Or just TRY it.
"In theory", reducing ESL works by the same equations that we use for reducing resistance by paralleling resistors. So yes, in theory, it CAN be done, and can be made as low as you want. And in reality, if the caps and their connections don't have any _mutual_ inductance, reality would match theory. Otherwise, the equations get more complicated and the effect is partially negated.
Here is a link to (most of) the collected links to the Terry Given posts about the cap array:
http://www.diyaudio.com/forums/chip-amps/224914-lm3886-component-selection-3.html#post3282640
I am probably going to use such arrays as the power/gnd rails for my next amplifier build. I'll mount the amplifier components on a daughterboard that is a mm or two above the cap arrays, over the line where the cap arrays meet (one 2-sided array for each rail, on either one or two 2-sided pcbs, total), so that the power and gnd connections will only be two or three (or four) mm long (I'm still deciding on how to interconnect, actually). If I use an LME49830 with lateral mosfets, for example, the power and gnd pins could go straight down through the daughterboard and directly into the array boards, if I can get the layout correct for that AND still be able to solder them; i.e. the ones that needed to go to the TOP side of the array PCB would need to all be at the edge of the daughterboard (unless I make some 1/2-inch holes that I can put the soldering iron through). The daughter board shouldn't need any decoupling caps, and its layout ought to be much easier (and thus better), since power and ground won't need to be on there, except right where they're needed (and I imagine I will use some ground plane on the daughterboard, actually).
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Gorgon,
If you want to become informed, you must do the research.
Much of what gets argued about on this Forum has already been published on this Forum.
This Forum is a fantastic source of very good information that some times is real state of the art, that is equally as good as what is being reported in learned research papers that are often a year or more out of date.
If you want to become informed, you must do the research.
Much of what gets argued about on this Forum has already been published on this Forum.
This Forum is a fantastic source of very good information that some times is real state of the art, that is equally as good as what is being reported in learned research papers that are often a year or more out of date.
Hi gootee, and thank you for the link.
Now, Terry made a board of 120x120mm and stuffed it with 100x1000uF caps
of 10-20nH caps. That should giv theoretically a 10-20nH/100=0,1-0,2nH.
He got 1,3nH. It proves that the point I was trying to make holds true
It is a thing of diminishing returns.
I would also like to point out that caps of max 12mm diam have to be very low
voltage. Now if you do the same thing with 63-100V caps your board size will increase significantly and so will your inductance. You will end up gettingsometing in the range of at least 3nH. Now compare that to the esl of a otherwise similar single cap with typically 12nH (at most) and you have a improvement of roughly 4. Is that worth the effort? You decide for yourself
Now, Terry made a board of 120x120mm and stuffed it with 100x1000uF caps
of 10-20nH caps. That should giv theoretically a 10-20nH/100=0,1-0,2nH.
He got 1,3nH. It proves that the point I was trying to make holds true
It is a thing of diminishing returns.
I would also like to point out that caps of max 12mm diam have to be very low
voltage. Now if you do the same thing with 63-100V caps your board size will increase significantly and so will your inductance. You will end up gettingsometing in the range of at least 3nH. Now compare that to the esl of a otherwise similar single cap with typically 12nH (at most) and you have a improvement of roughly 4. Is that worth the effort? You decide for yourself
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