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Old 25th July 2012, 02:03 PM   #11
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Thanks everybody, i guess i got all the answers i needed and all were unanimous in thier opinion
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Old 31st March 2013, 03:03 AM   #12
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I think this thread is of interest to many of us, so my 2 cent.
If I look at the esl of big caps (and was has been in the old days) it seems to me that now days most "big" electrolytic caps have to be made up of multiple internally connected smaller caps with the shortest possible path between them. The thereby achievable low esl is hard to beat by a bank of external parallel connected caps. I do not know, but I could imagine that a smart manufacturer would also know how to take advantage of the possibility to stagger and/or damp the resonances of the internal caps and adjust the esr for proper damping. When I look at some short and very thick Rifa caps (with there superb ratings) I look at something that will be hard to beat with DIY paralleled caps (except for cooling and lower cost). Remember the smallest possible loop Gootee often talks about? It gotta be inside those big SMPS caps....

Last edited by gorgon53; 31st March 2013 at 03:21 AM.
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Old 31st March 2013, 10:57 PM   #13
gootee is offline gootee  United States
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Although some of the capacitor manufacturers are certainly doing a wonderful job, I wouldn't give up on trying to get even-lower impedance, just yet.

Paralleling a number "n" of the best-designed capacitors, preferably using two closely-spaced copper planes for the connections, would have to lower the inductance even further, maybe not all the way down to 1/n as much, but probably as close as you wanted, especially if there were no other constraints on the board size and cap positioning.

Even just using "standard" electrolytics from the old days, you can get inductance down to less than 0.5 nH, just by using a thin PCB (1 mm) and leaving all of the copper on both sides of the PCB. You can just drill one hole for each cap (and remove the copper around the edges of the holes) and mount something like 100x 1000uF, and get below 0.5 nH (until you connect it to something).

Actually, most capacitors don't have much intrinsic inductance, anyway, except for the equivalent of the self-inductance of a piece of wire that is the same length as the capacitor's lead spacing (plus the actual remaining lead lengths, after mounting), probably on the order of 1 nH per mm of lead spacing plus lead length. But the total parasitic resistance (ESR) is also reduced, by paralleling.

-----

Note that my earlier posts in this thread about paralleling caps using separate parallel traces were a bit misguided. While it could theoretically be made to work, the mutual inductances would be difficult to eliminate, in most cases, which would inhibit the reduction of the total ESL due to paralleling (i.e. it would not go down to very near 1/n as might have been expected). So it would probably be much more easily made effective by using closely-spaced copper planes, for the connections.
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Old 3rd April 2013, 02:41 AM   #14
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Esr cannot much be reduced because the main contribution is from the liquid. Just thinck for instance what would be the difference between a cap of 10000uF and a bank of 10x1000? Materials are the same (aluminium, liquid), voltage is the same (roughness of the etching, thickness of oxilayer), capacitance and currentdensity is the same (area). Look how much esr changes with aging, temp, frequency a.s.o. The rest of the esr is not much of a "R", might even be better than in a lousy built solid cap and is also pretty stable if welded. I personally prefer a rod connection any time instead of a dozen tiny soldered pins, even if the rod is tied to a internal "fuse" that migth increase R a bit. Esr makes us easely think of the qualities of a resistor and we may also thinck a wet caps esr is the same animal than a solid caps esr....

Last edited by gorgon53; 3rd April 2013 at 03:09 AM.
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Old 4th April 2013, 12:09 AM   #15
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Hi gootee.
Off course you know that reducing esl, 1/n wont be close to possible even in theory, the more caps you ad the more diminishing results you get. And for a cap to be of low esl construction it has to be short and thick and "thicker" means longer interconnections. What you win in the cap you will loose at the interconnection and vice versa. But despite of that, I am glad someone finally gave proper attention to where it really should be, not at the esl of the caps, but at the way they are connected to the source, to each other, and to the load. I am now days more dealing with higher impedance tube circuits and esl is not much of a problem. in the old days, when I specialized into Rf-heating, paralleling caps and routing connections could get very expensive when done the wrong way. Conductors as wide as they are long, triple sandwiching with optimized distance between them (to keep proximity losses and/or electromagnetic forces in check) all those options I have all least tried, but more often than once the results where not as good as theory might promise. At high power frequencies and at currents of hundreds sometimes even thousands of amps results could often easily be seen in the form of heat patterns, bulging conductors a.s.o.
Capacitor banks of (necessarily) low esr high power caps proved to be a highly risky business. If they got unintentionally exited at some unwanted but unavoidable resonance it was just as dangerous as it was expensive. May be that is also one of the reasons I seem now days allergic to paralleling capacitor. Btw, the spacing of the connections of the caps would still leave much room for improvement, especially at low voltages the spacing is far to wide.

Last edited by gorgon53; 4th April 2013 at 12:30 AM.
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Old 4th April 2013, 10:43 PM   #16
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Quote:
Originally Posted by gootee View Post

Even just using "standard" electrolytics from the old days, you can get inductance down to less than 0.5 nH, just by using a thin PCB (1 mm) and leaving all of the copper on both sides of the PCB.

.
seriously 0.5nH with standard electrolytis? Are you kiddn me? Please tell me more about how you did that and especially how you measured it
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Old 5th April 2013, 03:21 AM   #17
gootee is offline gootee  United States
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It was done by a famous electromagnetics engineer from New Zealand named Terry Given (at home with a hand drill and a simple soldering iron and a blank 2-sided PCB) and measured with his HP 3577A vector network analyzer, from 5 Hz to 220 MHz. Results were reported on diyaudio.com, plots and all.

So yes, you really CAN reduce ESL (and ESR) by paralleling caps, even electrolytics. It's done all the time. Look up the stuff on the web by Bruce Archambeault and Henry W. Ott, among many others. Or just TRY it.

"In theory", reducing ESL works by the same equations that we use for reducing resistance by paralleling resistors. So yes, in theory, it CAN be done, and can be made as low as you want. And in reality, if the caps and their connections don't have any _mutual_ inductance, reality would match theory. Otherwise, the equations get more complicated and the effect is partially negated.

Here is a link to (most of) the collected links to the Terry Given posts about the cap array:

LM3886 component selection

I am probably going to use such arrays as the power/gnd rails for my next amplifier build. I'll mount the amplifier components on a daughterboard that is a mm or two above the cap arrays, over the line where the cap arrays meet (one 2-sided array for each rail, on either one or two 2-sided pcbs, total), so that the power and gnd connections will only be two or three (or four) mm long (I'm still deciding on how to interconnect, actually). If I use an LME49830 with lateral mosfets, for example, the power and gnd pins could go straight down through the daughterboard and directly into the array boards, if I can get the layout correct for that AND still be able to solder them; i.e. the ones that needed to go to the TOP side of the array PCB would need to all be at the edge of the daughterboard (unless I make some 1/2-inch holes that I can put the soldering iron through). The daughter board shouldn't need any decoupling caps, and its layout ought to be much easier (and thus better), since power and ground won't need to be on there, except right where they're needed (and I imagine I will use some ground plane on the daughterboard, actually).

Last edited by gootee; 5th April 2013 at 03:41 AM.
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Old 5th April 2013, 10:47 AM   #18
AndrewT is online now AndrewT  Scotland
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Gorgon,
If you want to become informed, you must do the research.
Much of what gets argued about on this Forum has already been published on this Forum.
This Forum is a fantastic source of very good information that some times is real state of the art, that is equally as good as what is being reported in learned research papers that are often a year or more out of date.
__________________
regards Andrew T.
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Old 5th April 2013, 02:30 PM   #19
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Quote:
Originally Posted by AndrewT View Post
Gorgon,
If you want to become informed, you must do the research.
Much of what gets argued about on this Forum has already been published on this Forum.
This Forum is a fantastic source of very good information that some times is real state of the art, that is equally as good as what is being reported in learned research papers that are often a year or more out of date.
please read more carefully what i said
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Old 5th April 2013, 02:47 PM   #20
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Hi gootee, and thank you for the link.

Now, Terry made a board of 120x120mm and stuffed it with 100x1000uF caps
of 10-20nH caps. That should giv theoretically a 10-20nH/100=0,1-0,2nH.
He got 1,3nH. It proves that the point I was trying to make holds true
It is a thing of diminishing returns.
I would also like to point out that caps of max 12mm diam have to be very low
voltage. Now if you do the same thing with 63-100V caps your board size will increase significantly and so will your inductance. You will end up gettingsometing in the range of at least 3nH. Now compare that to the esl of a otherwise similar single cap with typically 12nH (at most) and you have a improvement of roughly 4. Is that worth the effort? You decide for yourself
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