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Old 2nd June 2012, 12:13 PM   #1
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Default 576W SMPS for car audio amplifier

Hi everybody,

I'm trying to design a 12v to 24v(&24A) flyback SMPS for a low impedance class D audio amplifier.

First of all I want to simulate on it LTSpice to be sure that is well designed, but I've found some problems. I don't know if the SMPS its bad designed or bad simulated.

Everything works perfectly except the power consumption, I think that the problem is at the transformer model because the magnetization inductance sink 180A from the battery .

If anyone knows about this please tell me, I don't know what to do.

P.D.: This is my first post at this forum, be patient with me please .
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Old 2nd June 2012, 01:29 PM   #2
DUG is offline DUG  Canada
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Good Morning

The sg3525 data sheet says the absolute maximum output is 500mA

this would only drive the FET gate to 5V (if it did even that) because of the 10R to ground.

Rather than drive a single FET with both outputs through diodes, use two FET's each with its own drive (A & B), put the 10R in series with each gate line and you can still use a single inductor. You will not need a resistor to ground on the gate lines.

Since this is a flyback design and has a common ground, there is not really a need for a second winding on the transformer. Connect the output diode directly to the FET drain/inductor line.

I'm not sure of the purpose of Lm...is it just for LTSpice?

The feedback section of R1/U1 seems to be operating in a "linear" fashion with the threshold of the SG setting the regulation point. If you added a Zener diode in place of part of R1 the regulation point would be more well defined.

I was told at a SMPS seminar many years ago that a problem had occurred with a flyback design using Schottky diodes alone. The problem was that they don't conduct for a very small fraction of a second and this allowed the flyback spike to destroy the switching FET due to drain voltage ratings. I am not sure this is true but there seems to be snubbers or flyback clamps on FET drain lines in a lot of designs. The solution that was presented at that time was to place an ultrafast diode in parallel with the Schottky diode.

100uH might be a little high in value for power you are trying to put through it. If the inductor value is too high, the current will not rise to a very large amount in the time allowed and the energy stored ( I^2 * L ) won't be very high. This I^2 * L stored energy , multiplied by the pulse rate (switching frequency) results on your power output. If the inductor value is too low then the duty cycle that the regulator will adjust to get your power output will be low. It will work but the FET switching times will be a higher % of the overall "on time" and this will result in lower efficiency and a warmer FET, raising Rds ON values for the FET...additionally lowering efficiency further.

MAXIM IC had some good ap notes for inductor calculations. Other companies will also have good ap noted.

have fun
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Old 2nd June 2012, 02:18 PM   #3
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Hi Dug,

thanks a lot for your answer.

resolving your question, the Lm is the magnetization inductance of the ideal model of a transformer, the problem is that if I delete it the voltage won't rise to 24V (you can see it at the new image), why is happening this?.

Apart of that, wich will be the best inductance for the primary?
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Old 2nd June 2012, 08:38 PM   #4
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There is no such thing as magnetizing inductance part of a flyback transformer. The whole inductance is magnetizing inductance and how it works is 2 coupled inductors rather than a typical transformer, that is primary and secondary currents flow in different moments and the energy is being stored and released in the magnetic field each cycle.

The feedback loop doesn't look very robust, it seems to rely on the opto's CTR completely and SG's error amp is just a follower.... try decreasing R1 and put a 20V zener in series.

Last not least why flyback and not push-pull?
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Old 2nd June 2012, 09:31 PM   #5
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I don't care about the converter type, I'm just trying different types looking for the best performance for that power.

Thank you all for the help
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Old 3rd June 2012, 04:20 PM   #6
DUG is offline DUG  Canada
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After I posted, I remembered another function of the SG chip.

each output will have a maximum duty cycle of less than 50% since it is designed for push-pull output transformers.

The duty cycle limit is to allow the stored energy in the core time to get dumped into the load/filter.

If you are running one FET or even one core, there will be no time for this.

You should use two FET's (each its own 10R series in the gate cct) and two cores and of course two rectifiers

Then each core has time to dump its energy
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Old 9th June 2012, 05:40 PM   #7
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Hi everybody again,

I changed the topology to a push-pull converter like you suggested. Everything it's working perfectly, but the current through the transformer (L1 & L2) continues working wrong (see it at the image).

I don't know why the current through L1 is greater than L2, what I'm doing wrong? The resistance in serie of both is 0.02 ohm.

Thanks.
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Old 9th June 2012, 08:31 PM   #8
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I'm not sure if you modulate correctly.
Duty cycle of 0.4 at 100kHz means M1 is open for 4us, 1us neither, 4us M2 open, 1us neither etc. It looks like you open M1 for 6us and M2 for 4us.
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Old 9th June 2012, 08:53 PM   #9
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Ok, thanks you a lot. I was modulating bad, now its the problem solved.

But for the transformer, wich induction and the series resistance will be a good value? I don't know if the values I use are common for these tipe of SMPS.
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Old 9th June 2012, 11:38 PM   #10
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I haven't made exact calcs. but 4 turns over etd44 gives around 35uH for each primary.
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